Texas Instruments TL16C750EEVM User manual

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TL16C750EEVM User's Guide
User's Guide
SLLU317–January 2020
TL16C750EEVM User's Guide
This document covers how the user can set up and use the TL16C750EEVM.
Contents
1 Introduction ................................................................................................................... 2
2 5 V Processor to 3.3 V VCC on TL16C750E ............................................................................. 2
3 Input Power .................................................................................................................. 4
4 Onboard 3.3 V LDO Regulator ............................................................................................ 5
5 Using the EVM with the DUT at 3.3 V or lower ......................................................................... 6
6 Loopback mode ............................................................................................................. 7
7 Mode Select ................................................................................................................. 9
8 Reset ........................................................................................................................ 10
9 Silkscreen Errors on EVM ................................................................................................ 10
10 Board Layout................................................................................................................ 11
11 Schematic and Bill of Materials........................................................................................... 12
List of Figures
1 High to low shunt image .................................................................................................... 2
2 5.5 V to 3.3 V interface image ............................................................................................. 3
3 Input Power Image .......................................................................................................... 4
4 3.3 V LDO highlight image ................................................................................................. 5
5 DUT below 3.3 V............................................................................................................. 6
6 3.3 V only control image.................................................................................................... 7
7 Loopback mode.............................................................................................................. 8
8 Mode select................................................................................................................... 9
9 Reset image ................................................................................................................ 10
10 EVM top ..................................................................................................................... 11
11 EVM bottom................................................................................................................. 11
12 Schematic page 1.......................................................................................................... 12
13 Schematic page 2.......................................................................................................... 13
List of Tables
1 Bill of Materials ............................................................................................................. 14
Trademarks
All trademarks are the property of their respective owners.

Introduction www.ti.com
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TL16C750EEVM User's Guide
1 Introduction
1.1 Features
• 8x sampling mode for 2x Baud rate support
• Fractional Baud rate support
• 128 Byte FIFO depth
• 5V processor to 3.3V DUT level translation
1.2 Description
This document will cover how to set up the TL16C750EEVM for evaluation.
2 5 V Processor to 3.3 V VCC on TL16C750E
The below sections describes how to set up the EVM when using a 5 V digital logic processor to interface
with the TL16C750E used at a 3.3 V logic.
2.1 Using the 5 V to 3.3 V level shifters
To set up and use the EVM with 5 V to 3.3 V level shifting feature, a few adjustments need to be made in
terms of the jumper connections. Shunts should be applied to J9, J31 position 1 and 2, J30 position 2 and
3, J29 position 2 and 3, J24, and J19. An example highlighting this set up is seen in Figure 1.
Figure 1. High to low shunt image

www.ti.com 5 V Processor to 3.3 V VCC on TL16C750E
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TL16C750EEVM User's Guide
2x8 male headers are provided to connect between a processor and the EVM for the level translation.
Header denoted as J2 allows for the bidirectional data pins (D0-D7) to be accessed. The 5 V input pins
RESET, A0, A1, A2, CS, IOW, and IOR can be accessed at J22. The INT, TXRDY, and RXRDY lines
each have their own 1x1 headers denoted as J6, J8, and J17 respectively. The 5 V inputs RI, CD, DSR,
CTS, and RX can be found at J23. The 5 V outputs DTR, RTS, OP, and TX can be located at J20.The 5V
interfacing headers are highlighted in Figure 2.
Figure 2. 5.5 V to 3.3 V interface image

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3 Input Power
The EVM receives its power through the banana jack inputs denoted as J27 for ground and J26 for a 5 V
input to a power supply. When power is applied to the EVM through these banana jacks, LED D5 lights up
to signify that power is present. The expected voltage on the input power J26 is 5 V as this is a common
processor voltage range (a larger voltage should not be used). The input voltage can be lower depending
on VDO of the LDO (this is output current dependent). VINPUT should be greater than VLDO + VDO + VFif the
LDO is being used. VDO is the drop out voltage of the LDO, VLDO is the regulated voltage of the LDO, and
VFis the forward voltage of the schottky diode in front of the LDO denoted as D7. If more than 70 mA is
being sourced by the LDO then D7 should be removed, and the connection between D7 can be shorted.
Figure 3. Input Power Image

www.ti.com Onboard 3.3 V LDO Regulator
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4 Onboard 3.3 V LDO Regulator
This EVM uses the TPS70633 for 3.3 V regulation denoted on the EVM as U10. For the 3.3 V regulator to
be selected to provide power to the TL16C750E and onboard level shifters, J29 must be configured such
that position 2 and position 3 are shunted together, see Figure 4. If the onboard LDO is selected to be
used, banana jack J10 should not be used as J10 is connected directly to the 3.3 V LDO net. The figure
above shows J10 as do not use when the LDO is being used.
Figure 4. 3.3 V LDO highlight image

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5 Using the EVM with the DUT at 3.3 V or lower
When the TL16C750E device needs to be tested at lower than 3.3 V, the jumper at J29 should be
removed and a power supply can be connected to J10 instead. J31 should also include a shunt from
position 1 and 2 where the board denotes if VUART ≤3V6. J30 should be shunted from position 2 and 3
where the board denotes if VUART ≤3V6. Jumpers denoted as J9, J25, J29, J24, and J19 should not
have shunts. Figure 5 provides example.
Figure 5. DUT below 3.3 V
If used at 3.3 V, the configuration mention above can be used with the power supply set to 3.3 V or J29
can be shunted to positions 2 and 3 so that the onboard LDO can be used. The 5 V input should be used
in this instance as well to power the LDO but J10 would be removed if the 5 V input is to be used. The
jumper positions described previously and in Figure 5 still apply.

www.ti.com Loopback mode
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When the EVM is used in the 3.3 V and lower set up, the processor interface headers used should be the
ones located towards the center of the PCB. J3 provides access to output pins INT, TXRDY, and RXRDY.
J12 allow access to the bidirectional data pins D0-D7. J14 are for the input pins RESET, A0, A1, A2, CS,
IOW, and IOR. J18 provides access to the inputs RI, CD, DSR, CTS, and RX. Finally J13 allows access to
DTR, RTS, OP, and TX. The Figure 6 highlights all the jumper locations for connecting the processor pins.
Figure 6. 3.3 V only control image
6 Loopback mode
While TL16C750E does include an option to perform a loopback test through software, a hardware
loopback test can be performed by shunting J21 like the Figure 7.

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Figure 7. Loopback mode

www.ti.com Mode Select
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7 Mode Select
This EVM allows for the device to switch from interfacing modes. When J1 is left unshunted or shunted at
position 2 and 3, the TL16C750E is in Intel mode. This requires lines CS, IOW, and IOR to be used to
read or write from the device. If positions 1 and 2 are shunted on J1, Motorola mode is selected and the
TL16C750E is requires CS and IOW to toggle for communication. Note that the IOR pin needs to be held
in a logic high state to avoid any device issues (this is done through the pull up resistor R2 on the PCB).
Figure 8. Mode select

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TL16C750EEVM User's Guide
8 Reset
Resetting the TL16C750E can be done at J22 position 1 and 2 and J14 position 1 and 2 by toggling the
logic level. Driving the logic level low places the device in reset.
Alternatively, a hardware reset switch is provided and denoted as S1. A reset is observed by D4 turning
on.
Figure 9. Reset image
9 Silkscreen Errors on EVM
Location Current Error Should Read
J9 Level Shifter Disabled Level Shifter Enabled
J25 Disable Enable
J24 OFF ON
J19 Disable Enable