Texas Instruments TPA3223EVM User manual

User’s Guide
TPA3223 Evaluation Module
ABSTRACT
This user's guide describes the characteristics, operation, and use of the TPA3223 evaluation module. A
complete printed-circuit board (PCB) description, schematic diagram, and bill of materials are also included.
Table of Contents
1 Quick Start (BTL MODE).........................................................................................................................................................3
1.1 Required Hardware............................................................................................................................................................ 3
1.2 Connections and Board Configuration (BTL MODE)......................................................................................................... 4
1.3 Power-Up........................................................................................................................................................................... 5
2 Setup By Mode........................................................................................................................................................................7
2.1 BTL MODE (Stereo - 2 Speaker Outputs)..........................................................................................................................7
2.2 PBTL MODE (Mono – 1 Speaker Output)..........................................................................................................................7
3 Hardware Configuration.......................................................................................................................................................10
3.1 Indicator Overview (OTW_CLIP and FAULT)...................................................................................................................10
3.2 PWM Frequency Adjust................................................................................................................................................... 10
3.3 Modulation Modes (AD Mode and HEAD Mode)..............................................................................................................11
3.4 Output Mode Selection.....................................................................................................................................................11
3.5 Audio Front End................................................................................................................................................................11
3.6 EVM Power Tree..............................................................................................................................................................12
3.7 LC Response and Overview............................................................................................................................................ 12
3.8 Reset Circuit and POR.....................................................................................................................................................13
3.9 Analog-Input-Board Connector (J28)............................................................................................................................... 14
4 EVM Design Documents.......................................................................................................................................................16
4.1 TPA3223 Board Layouts.................................................................................................................................................. 16
4.2 TPA3223 Board Layouts.................................................................................................................................................. 18
4.3 TPA3223EVM Schematics............................................................................................................................................... 19
4.4 TPA3223EVM Bill of Materials......................................................................................................................................... 22
List of Figures
Figure 1-1. Output Configuration BTL......................................................................................................................................0
Figure 1-2. EVM Board (Top Side)...........................................................................................................................................0
Figure 1-3. EVM Board (Bottom Side)..................................................................................................................................... 0
Figure 1-4. Output Configuration PBTL - 4 Inductors.............................................................................................................. 0
Figure 1-5. EVM Board With Connectors and Jumpers...........................................................................................................0
Figure 1-6. Filter Frequency Response................................................................................................................................... 0
Figure 1-7. RESET Circuit....................................................................................................................................................... 0
Figure 1-8. AIB EVM Connector.............................................................................................................................................. 0
Figure 1-9. TPA3223EVM Top Composite Assembly.............................................................................................................. 0
Figure 1-10. TPA3223EVM Bottom Composite Assembly.......................................................................................................0
Figure 1-11. TPA3223 EVM Board Dimensions.......................................................................................................................0
Figure 1-12. TPA3223EVM Schematic 1................................................................................................................................. 0
Figure 1-13. TPA3223EVM Schematic 2................................................................................................................................. 0
Figure 1-14. TPA3223EVM Schematic 3................................................................................................................................. 0
Figure 1-1. Output Configuration BTL..........................................................................................................................................3
Figure 1-2. EVM Board (Top Side)...............................................................................................................................................4
Figure 1-3. EVM Board (Bottom Side)......................................................................................................................................... 4
Figure 2-1. Output Configuration PBTL - 4 Inductors.................................................................................................................. 7
Figure 2-2. EVM Board With Connectors and Jumpers...............................................................................................................8
Figure 3-1. Filter Frequency Response..................................................................................................................................... 13
Figure 3-2. RESET Circuit......................................................................................................................................................... 14
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Figure 3-3. AIB EVM Connector................................................................................................................................................ 14
Figure 4-1. TPA3223EVM Top Composite Assembly................................................................................................................ 16
Figure 4-2. TPA3223EVM Bottom Composite Assembly...........................................................................................................17
Figure 4-3. TPA3223 EVM Board Dimensions...........................................................................................................................18
Figure 4-4. TPA3223EVM Schematic 1..................................................................................................................................... 19
Figure 4-5. TPA3223EVM Schematic 2..................................................................................................................................... 20
Figure 4-6. TPA3223EVM Schematic 3..................................................................................................................................... 21
List of Tables
Table 1-1. Jumper and Switch Configurations (BTL Mode)..................................................................................................... 0
Table 1-2. Jumper and Switch Configurations (PBTL Mode)...................................................................................................0
Table 1-3. Fault and Clip Overtemperature Status.................................................................................................................. 0
Table 1-4. Frequency Adjust Primary Mode Selection (J16)....................................................................................................0
Table 1-5. HEAD and AD Mode Selection............................................................................................................................... 0
Table 1-6. Output Mode and Modulation Mode Selection........................................................................................................0
Table 1-7. Power Supply Summary......................................................................................................................................... 0
Table 1-8. AIB Connector (J28) Pinout.................................................................................................................................... 0
Table 1-9. AIB Power Rail Specifications.................................................................................................................................0
Table 1-10. TPA3223EVM Bill of Materials(1) ..........................................................................................................................0
Table 1-1. Jumper and Switch Configurations (BTL Mode)......................................................................................................... 5
Table 2-1. Jumper and Switch Configurations (PBTL Mode).......................................................................................................9
Table 3-1. Fault and Clip Overtemperature Status.................................................................................................................... 10
Table 3-2. Frequency Adjust Primary Mode Selection (J16)......................................................................................................10
Table 3-3. HEAD and AD Mode Selection..................................................................................................................................11
Table 3-4. Output Mode and Modulation Mode Selection.......................................................................................................... 11
Table 3-5. Power Supply Summary........................................................................................................................................... 12
Table 3-6. AIB Connector (J28) Pinout...................................................................................................................................... 14
Table 3-7. AIB Power Rail Specifications...................................................................................................................................15
Table 4-1. TPA3223EVM Bill of Materials(1) ..............................................................................................................................22
Trademarks
All trademarks are the property of their respective owners.
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1 Quick Start (BTL MODE)
The following section describes the necessary hardware, connections, configuration, and steps to quick start the
EVM into BTL mode with stereo audio playing out of two speakers.
Figure 1-1 illustrates the BTL mode output configuration.
Class-D
Amplifier
OUT-A
OUT-B
OUT-C
OUT-D
Figure 1-1. Output Configuration BTL
1.1 Required Hardware
The following hardware is required for this EVM:
• TPA3223EVM
• Power supply 5–14 A, 12–45 VDC
• Two 3–8 Ω speaker or resistor loads (make sure that speaker/load is appropriately sized for required wattage
output)
• Four speaker, banana cables
• Four XLR or two RCA input cables
• Analog output audio source
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1.2 Connections and Board Configuration (BTL MODE)
Figure 1-2 shows the EVM board.
Figure 1-2. EVM Board (Top Side)
Figure 1-3. EVM Board (Bottom Side)
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Use the following steps when connecting and configuring the board for BTL MODE:
1. Ensure the power supply is OFF. Connect the power supply positive terminal to J1 PVDD (red) and negative
terminal to J1 GND (black).
2. Connect the left channel speaker, power resistor load (3–8 Ω) to the TPA3223EVM positive output terminal
(J9 OUT1+ (red)) and other side of the speaker, power resistor to the TPA3223EVM negative output terminal
(J9 OUT1– (black)).
3. Connect the right channel speaker, power resistor load (3–8 Ω) to the TPA3223EVM positive output terminal
(J2 OUT2+ (red)) and other side of the speaker, power resistor to the TPA3223EVM negative output terminal
(J2 OUT2– (black)).
4. Check to make sure that the power supply is connected to J1 only and speakers are connected to J9 or J2
only, as their colors are the same.
5. Input Configuration:
a. Differential Inputs: connect one differential XLR audio input to each DIFF IN1 (J14) and DIFF IN2
(J15). Install jumpers J10, J11, J20, and J21 to position 1:2 which is labeled as RCA or XLR. Jumpers
J4 and J12 must be uninstalled for DIFF input.
b. Single-Ended Inputs: connect one single-ended RCA audio input to IN1P (J3) and IN2P (J18). Install
jumpers J10, J11, J20, and J21 to position 1:2 which is labeled as RCA or XLR. Jumpers J4 and J12
must be installed for SE input.
c. Audio Interface Board Input: Install jumpers J10, J11, J20, and J21 to position 2:3 which is labeled as
AIB. Jumpers J4 and J12 must be installed for SE input from the AIB or uninstalled for DIFF input from
the AIB.
6. Ensure that RESET S1 and MUTE S2 are in the lower positions of RESET and MUTE, respectively.
7. Check Table 1-1 for all jumper and switch configurations
Table 1-1. Jumper and Switch Configurations (BTL Mode)
Component Component Description Configuration for BTL
J23 Gain/CLKSYNC Select MSTR (Primary) 20 dB
J24 N/A IN
J4, J12 Input DIFF/SE Select OUT = DIFF IN, IN = DIFF IN
J10, J11, J20, J21 AIB Input Select Position 1:2 for XLR/RCA, Position 2:3
for AIB
J6 HEAD/AD Mode Select IN
J7, J8 PBTL/BTL Select OUT
S1 RESET Control RESET
S2 MUTE Control MUTE
J13 Auto Retry OUT
J29 PVDD-IN IN
J26 12V-IN IN
J5 5V-IN IN
J27 3.3V-IN IN
J17 OSC Output No Connection
J16 FREQ_ADJ Position 3:4 MASTER (Primary)
MODE
1.3 Power-Up
Ensure that required connections and configurations have been checked. The TPA3223EVM board can now be
powered on.
1. Enable the power supply at 12 V to 45 V and ensure that LED D5 illuminates. LEDs D2 and D4 must not be
illuminated.
2. Bring the EVM out of RESET state by switching RESET (S1) to NORMAL. You can see the FAULT LED (D4)
blink once quickly, then remain unilluminated.
3. Bring the EVM out of MUTE state by switching MUTE (S2) to NORMAL.
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4. Note that the EVM does not have volume control, configure your analog input for a reasonable audio level
before beginning audio playback.
5. Enable audio input playback and the EVM begins driving audio out of the left and right speakers. If resistor
loads are used for testing instead of speakers, then the load will now be energized.
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2 Setup By Mode
The following sections describe the setup and configuration for each output mode. The TPA3223EVM allows for
two output modes: Stereo BTL and Mono PBTL.
2.1 BTL MODE (Stereo - 2 Speaker Outputs)
This mode is the same as described in Quick Start (BTL MODE).
2.2 PBTL MODE (Mono – 1 Speaker Output)
This mode provides one speaker output that is more powerful than each BTL output and is useful when mono
audio is to be played or when more power is needed.
Figure 2-1 illustrates the PBTL mode output configuration with 4 inductors.
Class-D
Amplifier
OUT-A
OUT-B
OUT-C
OUT-D
Figure 2-1. Output Configuration PBTL - 4 Inductors
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2.2.1 Connections and Board Configuration
Figure 2-2 illustrates the connectors and jumpers on the EVM.
Figure 2-2. EVM Board With Connectors and Jumpers
Use the following steps when connecting and configuring the board:
1. Ensure the power supply is OFF. Connect power supply positive terminal to J1 PVDD (red) and negative
terminal to J1 GND (black).
2. Connect one speaker, power resistor load (3–8 Ω) to TPA3223EVM positive output terminal (J9 OUT1+
(red)) and other side of speaker, power resistor to TPA3223EVM negative output terminal (J9 OUT1–
(black)).
3. Use a short banana cable to connect J2 OUT2+ to J9 OUT1+ and a second short banana cable to connect
J2 OUT2– to J9 OUT1–. This connection forms the parallel connection of both OUTx+ to the one side of the
speaker and parallel connection of both OUTx– to the other side of the speaker.
4. Check to make sure that the power supply is connected to J1 only and the speaker is connected to J9 or J2
only, as the colors are the same.
5. Input Configuration:
a. Differential Inputs: connect one differential XLR audio input to DIFF IN1 (J14). Install jumpers J10, J11,
J20, and J21 to position 1:2, which is labeled as RCA or XLR. Jumpers J4 and J12 must be uninstalled
for DIFF input.
b. Single-Ended Inputs: connect one single-ended RCA audio input to IN1P (J3). Install jumpers J10, J11,
J20, and J21 to position 1:2, which is labeled as RCA or XLR. Jumpers J4 and J12 must be installed for
SE input.
c. Audio Interface Board Input: Install jumpers J10, J11, J20, and J21 to position 2:3, which is labeled as
AIB. Jumpers J4 and J12 must be installed for SE input from the AIB or uninstalled for DIFF input from
the AIB.
6. Ensure that RESET S1 and MUTE S2 are in the lower positions of RESET and MUTE, respectively.
7. Check Table 2-1 for all jumper and switch configurations necessary.
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Table 2-1. Jumper and Switch Configurations (PBTL Mode)
Component Component Description Configuration for PBTL
J23 Gain/CLKSYNC Select MSTR(Primary) 20 dB
J24 5V IN
J4, J12 Input DIFF/SE Select OUT = DIFF IN, IN =SE IN
J10, J11, J20, J21 AIB Input Select Position 1:2 for XLR/RCA, Position 2:3
for AIB
J6 HEAD/AD Mode Select IN
J7, J8 PBTL/BTL Select Position 2:3 for PBTL
S1 RESET Control RESET
S2 MUTE Control MUTE
J13 Auto Retry OUT
J29 PVDD-IN IN
J26 12V-IN IN
J5 5V-IN IN
J27 3.3V-IN IN
J17 OSC Output No Connection
J16 FREQ_ADJ Position 3:4 MASTER(Primary) MODE
2.2.2 Power-Up
Ensure that required connections and configurations have been checked. The TPA3223EVM board can now be
powered on.
1. Enable the power supply at 12 V to 45 V and ensure that LED D5 illuminates. LEDs D2 and D4 must not be
illuminated.
2. Bring the EVM out of RESET state by switching RESET (S1) to NORMAL. You can see the FAULT LED (D4)
blink once quickly, then remain unilluminated.
3. Bring the EVM out of MUTE state by switching MUTE (S2) to NORMAL.
4. Note that the EVM does not have volume control, configure your analog input for a reasonable audio level
before beginning audio playback.
5. Enable audio input playback and the EVM should begin driving audio out of the left and right speakers. If
resistor loads are used for testing instead of speakers, then the load will now be energized.
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3 Hardware Configuration
3.1 Indicator Overview (OTW_CLIP and FAULT)
The TPA3223EVM is equipped with LED indicators that illuminate when the FAULT or OTW_CLIP pin goes low.
See Table 3-1 and the TPA3223 data sheet (SLASEF0) for more details.
Table 3-1. Fault and Clip Overtemperature Status
FAULT
LED Status
OTW_CLIP
LED Status Description
ON ON Overtemperature (OTE) or overload (OLP) or undervoltage (UVP). Junction temperature higher
than 125°C (Overtemperature warning)
ON OFF Overload (OLP) or undervoltage (UVP). Junction temperature lower than 125°C
OFF ON Junction temperature higher than 125°C (Overtemperature warning)
OFF OFF Junction temperature lower than 125°C and no OLP or UVP faults (normal operation)
3.2 PWM Frequency Adjust
The TPA3223EVM allows for three oscillator frequency options by external configuration of the FREQ_ADJ pin.
The frequency adjust can be used to reduce interference problems while using a radio receiver tuned within the
AM band. These values must be chosen so that the nominal and the lower value switching frequencies together
results in the fewest cases of interference throughout the AM band. The oscillator frequency can be selected by
the value of the FREQ_ADJ resistor connected to GND in Primary mode according to Table 3-2.
Table 3-2. Frequency Adjust Primary Mode Selection (J16)
FREQ_ADJ (J16) Mode Resistor Selected to GND or Pullup
Primary MODE 10 kΩ
Primary MODE AM1 30 kΩ
Primary MODE AM2 49.9 kΩ
Peripheral MODE Pullup to 5 V
Selecting Peripheral Mode configures the OSC_I/O pins as inputs to be synchronized from an external
differential clock. In a Primary or Peripheral system, interchannel delay is automatically set up between the
switching phases of the audio channels, which can be illustrated by no idle channels switching at the same
time. The audio output will not be influenced, but the switch timing is changed to minimize noise coupling
between audio channels through the power supply. This configuration will optimize audio performance and result
in better operating conditions for the power supply. The inter-channel delay will be set up for a peripheral device
depending on the polarity of the OSC_I/O connection such that peripheral mode 1 (secondary) is selected by
connecting the OSC_I/O of the Primary device with the OSC_I/O of the peripheral device with the same polarity
(+ to + and – to –), while peripheral mode 2 (tertiary) is selected by connecting the OSC_I/Os with the inverse
polarity (+ to – and – to +).
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3.3 Modulation Modes (AD Mode and HEAD Mode)
The TPA3223EVM supports both AD modulation as well as HEAD modulation. In AD mode, each of the two
half-bridge outputs are continuously switching. AD mode is the default mode for the TPA3223EVM. The EVM
also supports HEAD mode modulation. HEAD mode also switches both half bridge outputs but also optimizes
the switching for lower power loss at idle as well as increased EMI performance at cost of some performance.
The device accomplishes this by reducing its duty cycle at idle and while playing small signals. At higher output
levels HEAD mode will also reduce the switching on one of the half bridges. The modulation mode can be
controlled through jumper J6 on the EVM as follows:
Table 3-3. HEAD and AD Mode Selection
J6 Jumper State Modulation Mode
IN AD Mode
OUT HEAD Mode
More information on the differences between HEAD mode and AD mode as well as performance data is found in
the TPA3223 data sheet (SLASEF0).
3.4 Output Mode Selection
The TPA3223 does not use discrete mode pins and therefore relies solely on the states of the IN2_M and IN2_P
pins. Connecting the IN2_M and IN2_P pins to regular high output impedance audio outputs by removing J7
and J8 puts the TPA3223 into BTL mode (2 x stereo outputs). Tying the IN2_M and IN2_P pins to GND by
installing J7 and J8 on pins 2-3 puts the TPA3223 into PBTL mode (1 x mono output). Tying the IN2_M and
IN2_P pins to 5V by installing J7 and J8 on pins 1-2 puts the TPA3223 into 1x BTL mode (1 x mono output). This
is summarized in Table 3-4:
Table 3-4. Output Mode and Modulation Mode Selection
Input Jumpers J7
and J8 Input Mode Output
Configuration Description
IN2_M IN2_P
OUT OUT
1N / 2N + 1
2 × BTL Stereo, BTL output configuration
2-3
(GND)
2-3
(GND) 1 × PBTL Mono, Paralleled BTL configuration. Connect OUT1+ to OUT2+ and OUT1– to OUT2–
1-2 (5V) 1-2 (5V) 1 × BTL Mono, BTL configuration. OUT1+ and OUT1– active
3.5 Audio Front End
The TPA3223EVM includes options for single-ended or differential input signals. A configurable front end is
built into the TPA3223 so that both single-ended and differential inputs can achieve the full scale output of the
TPA3223 device without need for external front end op-amp. Note that when EVM RCA or XLR connectors are
used, jumpers J11, J10, J21, and J20 must be installed in position 1:2 named XLR or RCA.
• Single-ended input can be provided through RCA to inputs J3 and J18. Uninstall jumpers J4 and J12 using
SE input so that the TPA3223 front-end will be configured for SE input.
• Differential input can be provided through XLR to inputs J14 and J15. Install jumpers J4 and J12 when using
DIFF input so that the TPA3223 front-end will be configured for DIFF input.
Input can also be provided through an audio plug-in board on J28. For this input type, change jumpers J11, J10,
J21, and J20 to position 2:3 named AIB.
See the EVM schematic section (Section 1.4.3) for complete details.
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3.6 EVM Power Tree
The TPA3223EVM includes a few options for power configuration so that various input types can be evaluated.
3.6.1 TPA3223 Supplies
The TPA3223 device has a few power supplies which each have their own voltage range and rules. Details for
each supply are as shown:
•PVDD – This is the main device supply which accepts from 10 V to 45 V. Power output of the device is
derived solely from PVDD and therefore it is important to configure this supply according to the chosen output
configuration and load. Complete details are included in the TPA3223 datasheet.
•VDD – This supply is used for the non-PVDD power of the device for blocks such as the front-end and control
circuitry. VDD is powered by 5 V directly and tied to GVDD and AVDD pins.
•GVDD and AVDD – These pins are used for the gate drive and analog supply of the device. GVDD and
AVDD accept only 5 V which can be provided through the TP or the 5V through J24.
Table 3-5. Power Supply Summary
PVDD (V) VDD (V) AVDD (V) GVDD (V)
10.0 to 45.0 5.0 5.0 (Tied to VDD) 5.0 (Tied to VDD)
3.6.2 TPA3223EVM Power Options
TPA3223 requires that 5 V is provided externally to VDD, AVDD, and GVDD. The major input configurations are
listed in the following sections by the supplies available.
3.6.2.1 PVDD Only (12 V to 45 V)
This power mode is the default setup when the board is tested and shipped. The user can connect any valid
supply voltage to J1 and the onboard LDOs will generate the required non-PVDD voltages. PVDD itself always
connects directly to the TPA3223 PVDD pins. Setup for this mode is the same as described in Quick Start (BTL
MODE).
3.6.2.2 PVDD (12 V to 45 V) and One Non-5-V Supply
This power mode is useful for certain applications where a system has one higher voltage used for PVDD and
a second lower voltage that may be used for device pullups and other supplies (VDD, GVDD, and AVDD). The
PVDD voltage can still be connected to J1 but jumpers J29 and J26 must be removed.
In the case of the TPA3223EVM, only 12V can be accepted as a non-5-V Supply and should be connected to pin
2 of J26 (12V).
3.6.2.3 PVDD (12 V to 45 V) and 5-V Supply
This power mode is most useful for systems in which a 5-V supply is already available due to additional circuitry
like an MCU or wireless module. On the EVM, this method is also the preferred way to measure efficiency of
the TPA3223 device. The PVDD voltage can still be connected to J1 but jumper J29 must be removed. The 5-V
supply must be connected to TP40.
The same 5-V input is used for the TPA3223 supplies (AVDD, VDD, and GVDD), the EVM reset control (U7), all
TPA3223 device pullups (RESET, HEAD, FREQ_ADJ, FAULT, OTW_CLIP), and status LEDs D4 and D2.
The 5-V supply can be isolated by by disconnecting J24. Once J24 jumper is removed, 5 V can be fed to only
the TPA3223 supplies through Pin 2 on the jumper and all other 5 V are being powered through 5 V LDO.
Either approach can be used to measure efficiency, but the most accurate numbers will be with the 5-V supply
separated so the TPA3223 supply voltage is isolated and measured independently of board LEDs, reset control,
and so forth.
3.7 LC Response and Overview
Included near the output of the TPA3223 device are four output LC filters. These output filters filter the PWM
output leaving only the audio content at high power which is fed to the speakers. The board uses a Sagami
10-µH inductor and 1-µF film capacitor to form this LC filter. Using the equations listed in LC Filter Design
(SLAA701), the filter low pass cut-off is as follows:
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cut off
1 1 50.3 kHz
2 L C 2 10 H 1 F
-= = =
p ´ p m ´ m
F
(2)
The frequency response of the filter per output load is illustrated in Figure 3-1.
6 Ÿ
3 Ÿ
4 Ÿ
2 Ÿ
8 Ÿ
Figure 3-1. Filter Frequency Response
Figure 3-1 is taken directly from the LC Filter Calculator tool available on TI.com (SLAC729). The tool is
configured for BTL common mode with values of 10 µH and 1 µF for the filter. This tool is also helpful when
designing a different board featuring one of TI’s class-D amplifiers.
The Sagami inductor used (7G14D-100M-R) has a saturation current of 15 A. This was selected for the EVM
since the TPA3223 supports a maximum short-circuit output current of 9 A. The inductance versus current curve
for a selected inductor is very important. It is essential for the inductor to maintain at least 5 µH of inductance
at the maximum short-circuit current of the power amplifier. The Sagami inductance versus current curve is
available in the 7G14D-100M-R data sheet on the Sagami web site.
Although not required, shielded inductors are used on the EVM to reduce EMI.
3.8 Reset Circuit and POR
The TPA3223EVM includes RESET supervision so that the TPA3223 device remains in reset until all power rails
are up and stable. The RESET supervisor also maintains that the device is put into reset if one of the power rails
experiences a brown out. This circuit combined with the RESET switch (S1) helps make sure that the TPA3223
can be placed in reset easily, as needed, or automatically if there is a power supply issue. Figure 3-2 illustrates
the circuit.
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Figure 3-2. RESET Circuit
3.9 Analog-Input-Board Connector (J28)
The Analog-Input-Board (AIB) connector allows for cross compatibility with several Analog Plug-in Modules
(APMs) offered by TI. This generic connector provides access to common board connections such as analog
input, analog output, Fault and overtemperature warning (OTW) error reporting, common board voltages (12 V,
3.3 V, and so forth), and EVM reset. These plug-in modules allow for an application-specific front end to be
plugged into the TPA3223EVM with ease. Examples of plug-in modules include front ends for guitar amplifier,
karaoke, wireless sub-woofer, and front-end audio crossover.
Figure 3-3. AIB EVM Connector
As Figure 3-3 shows, the AIB connector includes the following pins, associated specifications are listed in Table
3-7.
Table 3-6. AIB Connector (J28) Pinout
Pin
#Function Description Audio EVM Input/Output
1 Amp Out A Speaker-level output from audio Class-D EVM (SE or one side of BTL) O
2 Amp Out B Speaker-level output from audio Class-D EVM (SE or one side of BTL) O
3 PVDD PVDD voltage supply from audio Class-D EVM (variable voltage depending on Class-D EVM use) O
4 GND Ground reference between audio plug-in module and audio class-D EVM -
5 NC - -
6 NC - -
7 3.3 V 3.3-V supply from EVM; used for powering Audio Plug-in Module O
8 3.3 V 3.3-V supply from EVM; used for powering Audio Plug-in Module O
9 12 V 12-V supply from EVM; used for powering Audio Plug-in Module O
10 EN and RESET Assert enable and reset control for audio class-D EVM (active low) I
11 Analog IN_A Analog audio input A (analog in EVM) , MCLK I2S Bus (digital in EVM) I
12 NC - -
13 Analog IN_B Analog audio input B (analog in EVM) , BCLK I2S Bus (digital in EVM) I
14 CLIP_OTW Clipping detection, overtemperature warning, or both from audio class-D EVM (active low) O
15 Analog IN_C Analog audio input C (analog in EVM) , FS/LRCLK I2S Bus (digital in EVM) I
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Table 3-6. AIB Connector (J28) Pinout (continued)
Pin
#Function Description Audio EVM Input/Output
16 FAULT Fault detection from audio Class-D EVM (Active Low) O
17 Analog IN_D Analog audio Input D (analog in EVM) , SDIN I2S Bus (digital in EVM) I
18 NC - -
19 NC - -
20 NC - -
21 GND Ground reference between audio plug-in module and audio class-D EVM -
22 GND Ground reference between audio plug-in module and audio class-D EVM -
23 NC - -
24 NC - -
25 NC - -
26 NC - -
27 Amp Out C Speaker-level output from audio class-D EVM (SE or one side of BTL) O
28 Amp Out D Speaker-level output from audio class-D EVM (SE or one side of BTL) O
Table 3-7. AIB Power Rail Specifications
EVM Power Rails Always Available Voltage Range Max Current Source
PVDD Yes 15–80 V 500 mA External Source
12 V Yes 12 V 500 mA LDO
3.3 V Yes 3.3 V 100 mA LDO
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4 EVM Design Documents
This section contains the EVM board layouts, schematics, and bill of materials (BOM).
4.1 TPA3223 Board Layouts
Figure 4-1 and Figure 4-2 illustrate the EVM board layouts.
Figure 4-1. TPA3223EVM Top Composite Assembly
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Figure 4-2. TPA3223EVM Bottom Composite Assembly
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4.2 TPA3223 Board Layouts
Figure 4-3 shows the EVM board dimensions.
Figure 4-3. TPA3223 EVM Board Dimensions
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4.3 TPA3223EVM Schematics
Figure 4-4 through Figure 4-6 illustrate the TPA3223 EVM schematics.
Note: TPA3223EVM with the AMPS174A marking have 5V-PU connected to 5V(5Vto3.3V) supply net externally via wire. This is required for A revision
boards for proper operation.
100k
R48
IN1P
IN1M
OUT1+
OUT1-
IN2P
IN2M
OUT2+
OUT2-
RCA
INPUT 1 XLR
100k
R43
100k
R9
AUDIO
BOARD
IN2+_AIB
IN2-_AIB
IN1-_AIB
IN1+_AIB
FROM DUT OTW_CLIP
FAULT J30
GND
ALIGNMENT
HEADER
AIB
RESET-SW
RESET 1.00k
R57
INTERFACE
OUT1M
OUT1P
OUT2P
OUT2M
RST-AIB
3.3V
GND GND
3.3V
12V
PVDD
TO DUT
From DUT
TO DUT
TO DUT
From DUT
TO DUT
100k
R45
1000pF
500V
C21
100k
R25
1000pF
500V
C57
100k
R70
AUGNDL
AUGNDL
AUGNDL
AUGNDR
AUGNDR
AUGNDR
RCA
INPUT 2 XLR
1
2
3
J10
IN1+
1
2
3
J11
IN1-
22pF
50V
C20
22pF
50V
C23
GND
220pF
50V
C26
GND 220pF
50V
C37
IN1-_XLR
22pF
50V
C62
22pF
50V
C65
GND
220pF
50V
C45
GND 220pF
50V
C61
1
2
3
J20
IN2+
1
2
3
J21
IN2-
IN2-_XLR
GND
GND
GND
TP17
IN1+
TP29
IN1-
TP30
IN2+
TP31
IN2-
1
3
56
4
2
7
910
8
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
28 27
J28
MH1
MH2 1
2
3
4
+
GND
SHIELD
J14
DIFF IN1
MH1
MH2 1
2
3
4
+
GND
SHIELD
J15
DIFF IN2
1
2
3
J3
IN1P
1
2
3
J18
IN2P
10.0k
R20
IN1+_AIB
IN1-_AIB
IN2+_AIB
IN2-_AIB
3.3V
IN1+_RCA-XLR
IN1-_XLR
IN2+_RCA-XLR
IN2-_XLR
IN2+_RCA-XLR
IN1+_RCA-XLR
OUT1M OUT1P
OUT2POUT2M
1
2
3
J7
IN2P
5V-PU
GND
1
2
3
J8
IN2M
5V-PU
J4
IN1 SE
J12
IN2 SE
4.7uF
C17
4.7uF
C28
4.7uF
C55
4.7uF
C63
2.00k
R11
2.00k
R14
2.00k
R18
2.00k
R22
0R67
0
R52
0
R59
0
R60
0
R62
0
R4
0
R12
0
R44
0
R46
18.0k
R47
18.0k
R49
18.0k
R50
18.0k
R51
0R63
0R64
0R65
0R66
Figure 4-4. TPA3223EVM Schematic 1
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Q2
5V-PU
GND GND
Orange
D2
OTW_CLIP
5V-PU
GND GND
MONITORS
GND GND
GND GND
GND GND
GND GND
GND
PVDD
GND
GND
PVDD
GNDGND
GNDGND
RESET
GND
GND
GVDD
GND
IN1_P
IN1_M
5V-PU
SLAVE MODE
MASTER MODE (600 kHz)
MASTER MODE AM1 (533 kHz)
MASTER MODE AM2 (480 kHz)
GND
FREQUENCY
ADJUST
OUT2_M
IN2_M
IN2_P
1.00k
R29
1.00k
R31
100pF
50V
C64
100pF
50V
C58
100pF
50V
C30
100pF
50V
C19
OUT1_P
OUT1_M
OUT1+
OUT1-
OUT2+
OUT2-
12
34
56
78
J16
1uF
50V
C56
3.30
R54
GND
GND
GND
GND
1uF
50V
C53
1uF
50V
C51
1uF
50V
C50
TP2 OUT1_P
TP5 OUT1_M
TP9 OUT2_M
1 2
J13
FAULT
VDD
GVDD
FAULT
OTW_CLIP
GND
OSCILLATOR
SYNC
INTERFACE
4
1
2
3
J17
1uF16V
C41
TP26
FREQ_ADJ
TP21
IN1M
TP22
IN2P
TP23
IN2M
TP19
AVDD
TP15
GVDD
TP16
VDD
1000pF
100V
C25
1000pF
100V
C36
1000pF
100V
C44
1000pF
100V
C60
TP20
IN1P
OUT1+
OUT1-
OUT2-
OUT2+
IN1P
IN1M
IN2P
IN2M
FROM ANALOG
TO
ANALOG
FRONT END
GNDGND
6
4
5
13
S1
RESET
GND
GND
0.1uF
50V
C18
GND
PVDD
GND
GND
RESET CONTROL
RESET-SW
RESET
RESET-SW
TO AIB
OTW_CLIP
FAULT
CONTROLLER
RESET-SW
1uF
100V
C32
1uF
100V
C33
1uF
100V
C47
1uF
100V
C48
1uF
100V
C42
1uF
100V
C34
0.033uF
25V
C27
0.033uF
25V
C29
OUT2_P
TP7 OUT2_P
0.033uF
25V
C52
0.033uF
25V
C54
GND
OSCM
OSCP
OSCM
OSCP
FREQ_ADJ
FREQ_ADJ
TP1
OTW_CLIP
TP14
FAULT
5V-PU
GND
TP18
HEAD
10.0k
R68
HEAD
CMUTE
IN1_P
IN1_M
IN2_P
IN2_M
GAIN/SLV
VDD
AVDD
GAIN/SLV MATRIX
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
J23
Gain/SLV Select
GND GND GNDGND GND GND GND GND
M1
M2
M3
M4
S1
S2
S3
S4
AVDD
GND
6
4
5
13
S2
CMUTE
GND
PVDD
1uF
16V
C66
Using 10uH and 1uF, Cut-off is 50kHz
1uF
250V
C24
1uF
250V
C35
1uF
250V
C43
1uF
250V
C59
AUGNDR
AUGNDR
AUGNDR
AUGNDL
AUGNDL
AUGNDL
OUT1_P
OUT1_M
OUT2_P
OUT2_M
TP24
GAIN/SLV
1.00k
R38
0.033uF
25V
C16
GND
5V-PU
5V-PU
5V-PU
FRONT END
1.00k
R32
3.30
R55
3.30
R56
3.30
R53
1
2
3
J22
VDD SEL
5Vto3.3V
TP35
CMUTE
J9
J2
TP13
RESET
VDD-SEL
GVDD
20.0k
R69
10.0k
R79
10.0k
R80
GND
5V-PU
J24
J6
HEAD
TP6
GND
TP3
OUT1+
TP10
OUT1-
TP11
OUT2+
TP12
OUT2-
Q1
OTW_CLIP
FAULT
63V
1000uF
C31
63V
1000uF
C46
100V
0.1uF
C22
100V
0.1uF
C67
100
R5
100
R10
100
R19
100
R23
3.32
R75
FAULT OTW_CLIP
Red
D4
FAULT
100
R35
100
R33
0
R30
47.0k
R1
NT1
Net-Tie
NT2
Net-Tie
49.9kR15
30.0kR17
GND 1
GND 2
RESET 3
VDD
4
MR
5
TPS3802K33D CKR
U7
100k
R61
100k
R42
100k
R76
100k
R77
100k
R6
5.60k
R41
39.0k
R71
75.0k
R78
75.0k
R73
47.0k
R72
51.0k
R21
16.0k
R36
47.0k
R27
47.0k
R24
47.0k
R28
4.02k
R26
51.0k
R74
39.0k
R34
1
2
ATS-TI1OP-519-C1-R3
HS1
10uH
L2
10uH
L3
10uH
L4
10uH
L5
AVDD
2
GVDD
1
PVDD
29
PVDD
30
PVDD
31
PVDD
36
PVDD
37
PVDD
38
VDD
22
I N1_M
14
I N1_P
15
I N2_M
7
I N2_P
8
BST1_M 24
BST1_P 23
BST2_M 44
BST2_P 43
OUT1_M 32
OUT1_P 27
OUT1_P 28
OUT2_M 39
OUT2_M 40
OUT2_P 35
CMUTE
6
FAULT 19
OTW_CLI P 20
RESET
13
GAI N/CLKSYNC
21
HEAD
12
OSCM
11
OSCP
10
NC 3
NC 17
NC 18
FREQ_ADJ 9
GND 4
GND 5
GND 16
GND 25
GND 26
GND 33
GND 34
GND 41
GND 42
TPA3223DDVR
U4
TP4
TP8
TP40
L6
0
R81
0
R82
Figure 4-5. TPA3223EVM Schematic 2
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