Texas Instruments TPS5420EVM-175 SWIFT User manual

1 Introduction
1.1 Background
User's GuideSLVU163 – April 2006
TPS5420EVM-175 SWIFT™ Regulator Evaluation Module
Contents1 Introduction .......................................................................................... 12 Test Setup and Results ............................................................................ 33 Board Layout ........................................................................................ 84 Schematic and Bill of Materials ................................................................. 11
List of Figures
1 Measured Efficiency, TPS5420 ................................................................... 42 Load Regulation .................................................................................... 43 Line Regulation ..................................................................................... 54 Load Transient Response, TPS5420 ............................................................ 55 Measured Loop Response, TPS5420, VIN = 25 V ............................................. 66 Measured Output Voltage Ripple, TPS5420 .................................................... 67 Input Voltage Ripple, TPS5420 ................................................................... 78 Power Up, VOUT Relative to VIN ............................................................... 79 Start-Up Waveform, VOUT Relative to ENA ................................................... 810 Top-Side Layout .................................................................................... 911 Bottom-Side Layout (Looking From Top Side) ................................................ 1012 Top-Side Assembly ............................................................................... 1113 TPS5420EVM-175 Schematic ................................................................... 12
List of Tables
1 Input Voltage and Output Current Summary .................................................... 22 TPS5420EVM-175 Performance Specification Summary ..................................... 23 Output Voltages Available ......................................................................... 34 EVM Connectors and Test Points ................................................................ 35 TPS5420EVM-175 Bill of Materials ............................................................. 13
This user's guide contains background information for the TPS5420 as well as support documentation forthe TPS5420EVM-175 evaluation module (HPA175). Also included are the performance specifications, theschematic, and the bill of materials for the TPS5420EVM-175.
The TPS5420 dc/dc converter is designed to provide up to a 2-A continuous, 3-A peak output from aninput voltage source of 5.5 V to 36 V. Rated input voltage and output current range for the evaluationmodule is given in Table 1 . This evaluation module is designed to demonstrate the smallprinted-circuit-board areas that may be achieved when designing with the TPS5420 regulator and doesnot reflect the high input voltages that may be used when designing with this part. The switchingfrequency is internally set at a nominal 500 kHz. The high-side MOSFET is incorporated inside the
SWIFT, PowerPAD are trademarks of Texas Instruments.
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1.2 Performance Specification Summary
1.3 Modifications
1.3.1 Output Voltage Set Point
R2 10 k1.221 V
VO1.221 V
(1)
Introduction
TPS5420 package along with the gate drive circuitry. The low drain-to-source on resistance of theMOSFET allows the TPS5420 to achieve high efficiencies and helps to keep the junction temperature lowat high output currents. The compensation components are provided internal to the integrated circuit (IC),whereas an external divider allows for an adjustable output voltage. Additionally, the TPS5420 provides anenable input. The absolute maximum input voltage is 36 V.
Table 1. Input Voltage and Output Current Summary
EVM INPUT VOLTAGE RANGE OUTPUT CURRENT RANGE
TPS5420EVM-175 VIN = 10 V to 36 V 0 A to 2 A
A summary of the TPS5420EVM-175 performance specifications is provided in Table 2 . Specifications aregiven for an input voltage of VIN = 12 V and an output voltage of 5 V, unless otherwise specified. TheTPS5420EVM-175 is designed and tested for VIN = 10 V to 36 V. The ambient temperature is 25 °C for allmeasurements, unless otherwise noted. Maximum input voltage for the TPS5420EVM-175 is 36 V.
Table 2. TPS5420EVM-175 Performance Specification Summary
SPECIFICATION TEST CONDITIONS MIN TYP MAX UNIT
VIN voltage range 10 36 VOutput voltage set point 5.0 VOutput current range V
IN
= 10 V to 36 V 0 2.5 ALine regulation I
O
= 1 A, VIN = 3 V - 6 V ±0.11%Load regulation VIN = 25 V, I
O
= 0 A to 2.5 A ±0.1%Load transient response Voltage change I
O
= 0.75 A to 2.25 A -40 mVRecovery time 200 µsVoltage change I
O
= 2.25 A to 0.75 A +40 mVRecovery time 200 µsLoop bandwidth VIN = 25 V 25.0 kHzPhase margin VIN = 25 V 55 °Input ripple voltage I
O
= 3 A 275 300 mVppOutput ripple voltage 32 mVppOutput rise time 7 msOperating frequency 500 kHzMaximum efficiency VIN = 10 V, V
O
= 5 V, I
O
= 0.75 A 93.2%
The TPS5420EVM-175 is designed to demonstrate the small size that can be attained when designingwith the TPS5420. A few changes can be made to this module.
To change the output voltage of the EVM, it is necessary to change the value of resistor R2. Changing thevalue of R2 can change the output voltage above 1.25 V. The value of R2 for a specific output voltage canbe calculated using Equation 1 .
Table 3 lists the R2 values for some common output voltages. Note that VIN must be in a range so thatthe minimum on-time is greater than 200 ns, and the maximum duty cycle is less than 87%. The valuesgiven in Table 3 are standard values, not the exact value calculated using Equation 1 .
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1.3.2 Input Voltage Range
2 Test Setup and Results
2.1 Input / Output Connections
2.2 Efficiency
Test Setup and Results
Table 3. Output Voltages Available
Output Voltage (V) R2 Value (k Ω)
1.8 21.52.5 9.533.3 5.905 3.24
The EVM is designed to operate from a 10-V to 36-V input voltage range. The TPS5420 is specified tooperate over an input voltage range of 5.5 V to 36 V.
This section describes how to properly connect, set up, and use the TPS5420EVM-175 evaluationmodule. The section also includes test results typical for the TPS5420EVM-175 and covers efficiency,output voltage regulation, load transients, loop response, output ripple, input ripple, and start-up.
The TPS5420EVM-175 is provided with input/output connectors and test points as shown in Table 4 . Apower supply capable of supplying 2 A should be connected to J1 through a pair of 20 AWG wires. Theload should be connected to J3 through a pair of 20 AWG wires. The maximum load current capabilityshould be 2 A. Wire lengths should be minimized to reduce losses in the wires. Test-point TP1 provides aplace to monitor the VIN input voltages with TP2 providing a convenient ground reference. TP3 is used tomonitor the output voltage with TP4 as the ground reference.
Table 4. EVM Connectors and Test Points
Reference Designator Function
J1 VIN, 10 V to 36 VJ2 OUT, 5 V at 2 A maximumJP1 2-pin header for enable. Connect EN to ground to disable, open to enable.TP1 VIN test point at VIN connectorTP2 GND test point at VINTP3 Output voltage test point at OUT connectorTP4 GND test point at OUT connectorTP5 Test point between voltage divider network and R3. Used for loop response measurements.TP6 PH test point
The TPS5420EVM-175 efficiency peaks at load current of about 0.75 A, and then decreases as the loadcurrent increases towards full load. Figure 1 shows the efficiency for theTPS5420EVM-175 at an ambienttemperature of 25 °C. The efficiency is lower at higher ambient temperatures, due to temperature variationin the drain-to-source resistance of the MOSFETs.
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EFFICIENCY
vs
OUTPUT CURRENT
75
80
85
90
95
100
00.5 11.5 2
I - Output Current - A
O
Efficiency - %
V = 10 V
IN
V = 15 V
IN
V = 20 V
IN
V = 25 V
IN
V = 30 V
IN
V = 36 V
IN
2.3 Output Voltage Regulation
LOAD REGULATION
vs
OUTPUT CURRENT
-0.30
-0.20
-0.10
0
0.10
0.20
0.30
00.5 11.5 2
I - Output Current - A
O
Output Regulation - %
Test Setup and Results
Figure 1. Measured Efficiency, TPS5420
The output voltage load regulation of the TPS5420EVM-175 is shown in Figure 2 ; the output voltage lineregulation is shown in Figure 3 . Measurements are given for an ambient temperature of 25 °C.
Figure 2. Load Regulation
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LINE REGULATION
vs
INPUT VOLTAGE
-0.30
-0.20
-0.10
0
0.10
0.20
0.30
10 12 14 16 18 20 22 24 26 28 30 32 34 36
V - Input Voltage - A
I
Output Regulation - %
I = 1 A
O
I = 0 A
O
I = 2 A
O
2.4 Load Transients
t - Time = 200 μs/Div
I A/Div
OUT = 500 m
VOUT = 50 mV/Div (AC Coupled)
Test Setup and Results
Figure 3. Line Regulation
The TPS5420EVM-175 response to load transients is shown in Figure 4 . The current step is from 25% to75% of maximum rated load. Total peak-to-peak voltage variation is as shown, including ripple and noiseon the output.
Figure 4. Load Transient Response, TPS5420
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2.5 Loop Characteristics
MEASURED LOOP RESPONSE
-30
-20
-10
0
10
20
30
40
50
60
70
f - Frequency - Hz
Gain - dB
-90
-60
-30
0
30
60
90
120
150
180
210
Phase - Deg
Gain
Phase
10 100 1 k 10 k 100 k 1 M
2.6 Output Voltage Ripple
PH = 10 mV/div
V = 10 mV/div (ac Coupled)
O
Time = 1 s/divm
Test Setup and Results
The TPS5420EVM-175 loop-response characteristics are shown in Figure 5 . Gain and phase plots areshown for VIN voltage of 25 V and a 1-A load current.
Figure 5. Measured Loop Response, TPS5420, VIN = 25 V
The TPS5420EVM-175 output voltage ripple is shown in Figure 6 . The input voltage is VIN = 25 V for theTPS5420. Output current is the rated full load of 2 A. Voltage is measured directly across outputcapacitors.
Figure 6. Measured Output Voltage Ripple, TPS5420
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2.7 Input Voltage Ripple
V = 100 mV/div (ac Coupled)
O
PH = 10 V/div
Time = 1 s/divm
2.8 Powering Up
t - Time = 5 ms/Div
V = 2 V/Div
OUT
V = 10 V/Div
IN
Test Setup and Results
The TPS5420EVM-175 input voltage ripple is shown in Figure 7 . The input voltage is VIN = 10 V for theTPS5420. Output current for each device is at full rated load of 2 A.
Figure 7. Input Voltage Ripple, TPS5420
The TPS5420EVM-175 start-up waveforms are shown in Figure 8 and Figure 9 . In Figure 8 the top traceshows VIN whereas the bottom trace shows VOUT. VIN increases from 0 V toward 25 V. When the inputvoltage reaches the internally set UVLO threshold voltage of 5.3 V, the slow-start sequence begins. Theinternal reference begins to ramp up linearly at the internally set slow-start rate towards 1.221 V, and theoutput ramps up toward the set voltage of 5 V. The output may be inhibited by using a jumper at JP1 to tieENA to GND. When the jumper is removed, ENA is released and the slow-start sequence begins asshown in Figure 9 . The top trace shows the ENA signal and the bottom trace shows VOUT. When theENA voltage reaches the enable-threshold voltage of 1.06 V, the start-up sequence begins as describedabove.
Figure 8. Power Up, VOUT Relative to VIN
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t - Time = 5 ms/Div
V = 2 V/Div
OUT
ENA = 2 V/Div
3 Board Layout
3.1 Layout
Board Layout
Figure 9. Start-Up Waveform, VOUT Relative to ENA
This section provides a description of the TPS5420EVM-175 board layout and layer illustrations.
The board layout for the TPS5420EVM-175 is shown in Figure 10 through Figure 12 . The top-side layer ofthe TPS5420EVM-175 is laid out in a manner typical of a user application. The top and bottom layers are2-oz. copper.
The top layer contains the main power traces for VIN, OUT, and VPHASE. Also on the top layer areconnections for the remaining pins of the TPS5420 and a large area filled with ground. The bottom layercontains ground and some signal routing. The top and bottom and internal ground traces are connectedwith multiple vias placed around the board including four vias directly under the TPS5420 device toprovide a thermal path from the PowerPAD™ land to ground.
The input decoupling capacitors (C1 and C4) and bootstrap capacitor (C3) are all located as close to theIC as possible. In addition, the voltage set-point resistor divider components are also kept close to the IC.The voltage divider network ties to the output voltage at the point of regulation, adjacent to the outputcapacitor C3.
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Board Layout
Figure 10. Top-Side Layout
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Board Layout
Figure 11. Bottom-Side Layout (Looking From Top Side)
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