Texas Instruments TPS7H4010EVM User manual

User’s Guide
TPS7H4010EVM User's Guide
ABSTRACT
The TPS7H4010-SEP (Space Enhanced Plastic) evaluation module (EVM) with orderable part number
TPS7H4010EVM, is designed to help customers evaluate the performance of the TPS7H4010-SEP synchronous
step-down voltage converter. The EVM contains two independent buck converter circuits, each of which contains
the TPS7H4010-SEP which is in the 30-pin wettable flanks QFN (WQFN) package. The two circuits deliver very
accurate output voltages at 1.8 V and 3.3 V with up to 6 A current capacity with exceptional efficiency in a very
small solution size. The EVM provides multiple power connectors and test points, as well as mode setting and
enable input options, allowing for flexibility in testing.
Table of Contents
1 Introduction.............................................................................................................................................................................3
1.1 TPS7H4010 Space Enhanced Plastic Evaluation Module................................................................................................. 3
1.2 TPS7H4010-SEP Synchronous Step-Down Voltage Converter.........................................................................................3
1.3 TPS7H4010-SEP Evaluation Module.................................................................................................................................4
2 Quick Start...............................................................................................................................................................................6
3 Detailed Descriptions............................................................................................................................................................. 7
4 Schematic..............................................................................................................................................................................10
5 Board Layout.........................................................................................................................................................................12
6 Bill of Materials..................................................................................................................................................................... 17
7 TPS7H4010EVM Test Data....................................................................................................................................................19
7.1 TPS7H4010EVM PVIN=5 V, VOUT=1.8 V, FSW=500 kHz..............................................................................................19
7.2 TPS7H4010EVM PVIN=12 V, VOUT=3.3 V, FSW=500 kHz............................................................................................23
List of Figures
Figure 1-1. TPS7H4010EVM....................................................................................................................................................... 3
Figure 1-2. TPS7H4010-SEP Pin Configuration (30-Pin WQFN Package Top View)..................................................................4
Figure 1-3. TPS7H4010-SEP Schematic.....................................................................................................................................4
Figure 1-4. TPS7H4010-SEP Package Marking..........................................................................................................................5
Figure 4-1. TPS7H4010EVM PVIN=5 V, VOUT=1.8 V Schematic............................................................................................ 10
Figure 4-2. TPS7H4010EVM PVIN=12 V, VOUT=3.3 V Schematic.......................................................................................... 11
Figure 5-1. Top Layer and Silkscreen Layer.............................................................................................................................. 12
Figure 5-2. Top Layer Routing................................................................................................................................................... 13
Figure 5-3. Mid-Layer 1 Ground Plane...................................................................................................................................... 14
Figure 5-4. Mid-Layer 2 Routing................................................................................................................................................ 15
Figure 5-5. Bottom Layer Routing..............................................................................................................................................16
Figure 7-1. PVIN=5 V, VOUT=1.8 V, FSW=500 kHz: VOUT vs IOUT....................................................................................... 19
Figure 7-2. PVIN=5 V, VOUT=1.8 V, IOUT=6 A, FSW=500 kHz: Loop Response ................................................................... 20
Figure 7-3. PVIN=5 V, VOUT=1.8 V, FSW=500 kHz: Transient Response to current step from 2 A to 6 A at 1 A/us............... 20
Figure 7-4. PVIN=5 V, VOUT=1.8 V, FSW=500 kHz: Transient Response to current step from 6 A to 2 A at 1 A/us............... 21
Figure 7-5. PVIN=5 V, VOUT=1.8 V, IOUT=6 A, FSW=500 kHz: Output Voltage Ripple.......................................................... 21
Figure 7-6. PVIN=5 V, VOUT=1.8 V, IOUT=6 A, FSW=500 kHz: Soft Start.............................................................................. 22
Figure 7-7. FSW=500 kHz: Efficiency vs IOUT..........................................................................................................................22
Figure 7-8. PVIN=12 V, VOUT=3.3 V, FSW=500 kHz: VOUT vs IOUT..................................................................................... 23
Figure 7-9. PVIN=12 V, VOUT=3.3 V, IOUT=6 A, 3 A, 1 A, FSW=500 kHz: Loop Response .................................................. 24
Figure 7-10. PVIN=12 V, VOUT=3.3 V, FSW=500 kHz: Transient Response to current step from 2 A to 6 A at 1 A/us........... 24
Figure 7-11. PVIN=12 V, VOUT=3.3 V, FSW=500 kHz: Transient Response to current step from 6 A to 2 A at 1 A/us........... 25
Figure 7-12. PVIN=12 V, VOUT=3.3 V, IOUT= 6 A, FSW=500 kHz: Output Voltage Ripple..................................................... 25
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Figure 7-13. PVIN=12 V, VOUT=3.3 V, IOUT= 6 A, FSW=500 kHz: Soft Start......................................................................... 26
Figure 7-14. FSW=500 kHz: Efficiency vs IOUT........................................................................................................................26
List of Tables
Table 1-1. Device and Package Configurations...........................................................................................................................3
Table 1-2. Converter Circuit Variants........................................................................................................................................... 4
Table 6-1. TPS7H4010EVM BOM............................................................................................................................................. 17
Trademarks
All other trademarks are the property of their respective owners.
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1 Introduction
1.1 TPS7H4010 Space Enhanced Plastic Evaluation Module
The TPS7H4010-SEP (Space Enhanced Plastic) evaluation module (EVM), shown in Figure 1-1with orderable
part number TPS7H4010EVM, is designed to help customers evaluate the performance of the TPS7H4010-SEP
synchronous step-down voltage converter. The EVM contains two independent buck converter circuits, each of
which contains the TPS7H4010-SEP which is in the 30-pin wettable flanks QFN (WQFN) package, as described
in Table 1-1. The two circuits deliver very accurate output voltages at 1.8 V and 3.3 V with up to 6 A current
capacity with exceptional efficiency in a very small solution size. The EVM provides multiple power connectors
and test points, as well as mode setting and enable input options, allowing for flexibility in testing.
Figure 1-1. TPS7H4010EVM
Table 1-1. Device and Package Configurations
CONVERTER IC PACKAGE
U1, U2 TPS7H4010-SEP 30-pin wettable flanks QFN (WQFN)
6 mm × 4 mm × 0.8 mm
1.2 TPS7H4010-SEP Synchronous Step-Down Voltage Converter
The TPS7H4010-SEP is an easy-to-use synchronous step-down DC-DC converter capable of driving up to 6 A
of load current from a supply voltage ranging from 3.5 V to 30 V. The TPS7H4010-SEP provides exceptional
efficiency and output accuracy in a very small solution size. Peak-current-mode control is employed. Additional
features such as adjustable switching frequency, synchronization to an external clock, FPWM option, power-
good flag, precision enable, adjustable soft start, and tracking provide both flexible and easy-to-use solutions for
a wide range of applications. Automatic frequency foldback at light load and optional external bias improve
efficiency over the entire load range. The device requires few external components and has a pinout designed
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for simple PCB layout with optimal EMI and thermal performance. Protection features of the device include
thermal shutdown, input undervoltage lockout, cycle-by-cycle current limiting, and hiccup short-circuit protection.
The pin configuration of the TPS7H4010-SEP is shown in Figure 1-2 and the schematic is shown in Figure 1-3
for your quick reference.
VCC
RT
BIAS
SS/TRK
2
3
423
25
24
PVIN
SW
SW
DAP PVIN
PGND
SW
22
26
1
5
CBOOT
SW
PGND
21
6
PGND
PGND
20
7
PGOOD
19
8AGND
9
10
18
17
EN
FB
SYNC/
MODE
16
11
29 28 27
30
13 14 15
12
SW PVIN
NC NC NC NC
NC NC NC NC
Figure 1-2. TPS7H4010-SEP Pin Configuration (30-
Pin WQFN Package Top View)
Copyright © 2017, Texas Instruments Incorporated
CSS
RT
RSYNC
RENT
RENB
SW
PVIN
PGND
CBOOT
VCC
BIAS
EN
AGND
FB
VIN
COUT
CBOOT
CIN
CVCC
VOUT
RFBT
RFBB
L
SYNC/
MODE
RT
SS/TRK PGOOD
Figure 1-3. TPS7H4010-SEP Schematic
1.3 TPS7H4010-SEP Evaluation Module
The TPS7H4010-SEP evaluation module is orderable part number TPS7H4010EVM. The EVM contains two
independent converter circuits targeting two common applications:
• POLA: FSW=500 kHz, PVIN=5 V, VOUT=1.8 V, IOUT=0 A to 6 A
• POLB: FSW=500 kHz, PVIN=12 V, VOUT=3.3 V, IOUT=0 A to 6 A
Although the device operates over a wide PVIN range of 3.5 V to 30 V, the two circuits are optimized for PVIN of
5 V and 12 V. Table 1-2 summarizes the two circuits.
Table 1-2. Converter Circuit Variants
Label U1/U2 IOUT
Switching
Frequency VIN Range VOUT
POLA_VOUT_1.8V TPS7H4010-SEP 6 A 500 kHz 5 to 30 V 1.8 V
POLB_VOUT_3.3V TPS7H4010-SEP 6 A 500 kHz 5 to 30 V 3.3 V
It is worth noting that the package size of the TPS7H4010-SEP at U1 and U2 is not large enough to hold the full
device name. The devices are labeled 'PS7H4010' as shown in graphic below. Despite the device name starting
with "P", these devices are production devices and should not be mistaken for protoypes.
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Figure 1-4. TPS7H4010-SEP Package Marking
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2 Quick Start
The following instructions explain how to quickly setup testing of POLA_VOUT_1.8V circuit. Testing of the
POLB_VOUT_3.3V circuit is analogous to this setup with connections moving to that converter circuit. [NOTE:
Each converter circuit provides two connection options for PVIN and VOUT. PVIN can be supplied to banana
jacks J3/J2 or terminal block J19. VOUT can be connected to banana jacks J1/J2 or terminal block J20. It is
recommended to use terminal blocks instead of banana jacks if currents of 5 A or more are being tested.]
1. Connect the input voltage supply between J3, PVIN_A, and J2, GND_A using short, low gauge wires. [Note:
For very accurate PVIN control across all load conditions, connect sense lines from power supply to
testpoints TP5, PVIN_A, and TP7, GND_A.]
2. Connect the load of the converter between J1, VOUT_A, and J2, GND_A using short, low gauge wires.
3. Set the supply voltage (PVIN) to 5V with a current limit set to 4 A (expect ~2.6 A maximum).
4. Turning on the PVIN power supply, the converter should provide a regulated VOUT = 1.8 V across all current
load conditions from 0 A to 6 A.
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3 Detailed Descriptions
This section describes the connectors and the test points on the EVM and how to properly connect, set up and
use the TPS7H4010EVM. See Figure 1-2 for a top view of the EVM. The "_x" in the table below refers
collectively to the the two converter circuits on the PCB: "POL_A" and "POL_B".
VOUT_A (J1 or
J20+) VOUT_B
(J10 or J22+)
Output voltage of the converter.
VOUT_x banana jack and terminal block connectors connect to the power inductor and the
output capacitors. Connect the loading device between VOUT_x and GND_x connectors to
provide loading to the converter. Connect the loading device to the board with short and
thick wires to handle the large DC output current.
GND_A (J2 or
J20-) GND_B (J11
or J22-)
Ground of the converter.
It is connected to the PGND and AGND of the device, as well as the input and output
capacitors. GND_x is the current return path for both supply voltage and load. Connect to
supply and load grounds with short and thick wires.
PVIN_A (J3 or
J19+) PVIN_B
(J12 or J21+)
Input voltage to the converter.
PVIN_x connectors and test points connect to the input capacitors and the PVIN pins of the
TPS7H4010-SEP. Connect the supply voltage from a power supply or a battery between
PVIN_x and GND_x connectors as power input to the board. The voltage range should be
higher than 3.5 V for the device to be active. PVIN should be no higher than 30 V to avoid
damaging the device. The current limit on the supply should be high enough to provide the
needed supply current, otherwise, the power supply will not maintain the desired voltage.
The supply voltage should be connected to the board with short and thick wires to handle
the pulsing input current. If long cables are used to power up the board, the damping
capacitors C14 and C32, located on the bottom side of board, should be added to avoid
oscillations between the cable parasitic inductance and the low-ESR ceramic capacitors.
PVIN_EMI_A (J4)
PVIN_EMI_B
(J13)
Input voltage to input filter of the converter (not installed by default)
If the input filter is desired between the supply voltage and the TPS7H4010-SEP, connect
the supply voltage between PVIN_EMI_x and GND_x. The supply voltage should be
connected to the board with short and thick wires to handle pulsing input current.
GND_A (J5)
GND_B (J14)
Ground connection near the input filter
This is the current return path for the supply connected to PVIN_EMI_x. It provides a direct
connection to the input filter capacitors to best filter the conducted noises generated from
the PCB. Use PVIN_EMI_x and GND_x connection if input filter is used and conducted EMI
test is desired.
POLA_Input Filter
(C11, C12, C13,
C14, L2)
POLB_Input Filter
(C29, C30, C31,
C32, L4)
Reduces noise from supply voltage
The input filter consists of a C-L-C pi configuration, located on the bottom side of the PCB.
To include the input filter in the power path, connect the supply voltage between the
PVIN_EMI_x and GND_x connectors. The output of the filter is connected to the PVIN net,
which is connected to the PVIN pins of the TPS7H4010-SEP and the input capacitors. Note
that the input filter components are not mounted on the PCB by default.
Conducted EMI arises from the normal operation of switching circuits. The ON and OFF
actions of the power switches generate large discontinuous currents. The discontinuous
currents are present at the input side of buck converters. Voltage ripple generated by
discontinuous currents can be conducted to the voltage supply of the buck converter via
physical contact of the conductors. Without control, excessive input voltage ripple can
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compromise operation of the source. The input filter helps to smooth out the voltage
perturbations leading to the source.
EN_A (TP12)
EN_B (TP26)
Test point to monitor the EN pin of the device
EN_A Jumper
(J6) EN_B
Jumper (J15)
Set EN pin options
As noted on the board, this jumper selects which voltage is used to enable the device
(schematic is shown in Figure 1-3 )
1. PIN-1 to PIN-2: EN_x is connected to EN_EXT_x test point through a resistor divider.
2. PIN-2 to PIN-3 (default): EN_x is connected to PVIN_x through a resistor divider.
The default setting is jumper on PIN-2 and PIN-3. The board will start when PVIN is about
3.5 V with this setting. The EN voltage is calculated by Equation 1.
VEN = PVIN × RENB / (RENT + RENB)(1)
When PIN-1 and PIN-2 are connected, the EN voltage is calculated by Equation 2.
VEN = VEN_EXT × RENB / (RENT + RENB)(2)
If a resistor divider is not desired, the RENB can be removed from the board and the EN pin
voltage will be equal to either EN_EXT_x or PVIN voltage, depending on the jumper
location. It is recommended to keep RENT as a current limiting and noise filtering resistor at
EN pin.
EN_EXT_A (TP14)
EN_EXT_B (TP28)
External voltage input to drive EN
When EN_x jumper has PIN-1 and PIN-2 connected, the enable threshold is driven by the
voltage on the EN_EXT_x test point. The EN_x pin voltage can be found by Equation 2.
Remove RENB from the board if it is desired to have the same voltage on the EN pin as the
EN_EXT_x voltage (schematic is shown in Figure 1-3 ).
PGOOD_A (TP11)
PGOOD_B (TP25)
Test point to monitor the PGOOD_x pin
PGOOD_x test points are used to monitor the power-good flag. This flag indicates whether
the output voltage has reached its regulation level. The PGOOD pin of the device is an
open-drain output that is pulled up to VOUT on this board through 100kohm resistor.
MODE_A Jumper
(J7) MODE_B
Jumper (J16)
Operation mode setting and synchronization clock input
As noted on the PCB, the MODE_x jumper is used to select the desired light-load operation
mode.
1. PIN-1 to PIN-2: FPWM mode;
2. PIN-2 to PIN-3 (default): auto mode;
3. Open, connect external clock input to SYNC_x test points (TP13, TP27) for
synchronization and FPWM mode.
The default is PIN-2 and PIN-3 connected together and the device will operate in auto
mode at light loads. With auto mode, discontinuous conduction mode (DCM) and pulse
frequency modulation (PFM) mode are employed at light loads to provide high efficiency.
PFM mode also provides very low quiescent current at no load. At heavier load, when
inductor current is in DCM or continuous conduction mode (CCM) operation, the switching
frequency is determined by the RT resistors (R6, R16) on the board, which is either 500
kHz.
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When PIN-1 and PIN-2 are connected, the device operates in the force PWM (FPWM)
mode. In FPWM, the inductor current will be in CCM regardless of load. The switching
frequency is the same at light loads as that of heavier loads. The switching frequency will
be programmed by RT resistors (R6, R16) on the board, which is 500 kHz.
If synchronization to an external clock is desired, leave the MODE_x jumper open and
connect the clock input between SYNC_x test points (R13, R27) and a GND test point. The
device will operate in FPWM when it is synchronized to an external clock.
SYNC_A (TP13)
SYNC_B (TP27)
Test point to monitor the SYNC/MODE pin and external clock input
The SYNC_x test point can used to monitor the SYNC/MODE pin voltage on the device. It
is also the external clock input if synchronization is needed. Connect the external clock
input to the SYNC_x test point with the MODE_x jumper open on all pins. The external
clock frequency must be between 350 kHz and 2.2 MHz if used. The device operates in
FPWM when synchronized to a clock.
VCC_A (TP6)
VCC_B (TP20)
Test point to monitor the VCC pin
This test point is to monitor the voltage at the VCC output.
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4 Schematic
The TPS7H4010EVM Schematic is shown in Figure 4-1 below.
Figure 4-1. TPS7H4010EVM PVIN=5 V, VOUT=1.8 V Schematic
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Figure 4-2. TPS7H4010EVM PVIN=12 V, VOUT=3.3 V Schematic
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5 Board Layout
Figure 5-1 through Figure 5-5 show the board layout for the TPS7H4010EVM. The EVM offers resistors,
capacitors, and test points to configure the output voltage, precision enable pin, set frequency, and external
clock synchronization.
The 30-pin WQFN package offers an exposed thermal pad which must be soldered to the copper landing on the
PCB for optimal thermal performance. The PCB consists of a 4-layer design. There are 2-oz copper planes on
the top and bottom and 1-oz copper mid-layer planes to dissipate heat with an array of thermal vias under the
thermal pad to connect to all four layers.
Test points have been provided for ease of use to connect the power supply, required load, and to monitor critical
signals.
Figure 5-1. Top Layer and Silkscreen Layer
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Figure 5-2. Top Layer Routing
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Figure 5-3. Mid-Layer 1 Ground Plane
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Figure 5-4. Mid-Layer 2 Routing
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Figure 5-5. Bottom Layer Routing
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6 Bill of Materials
The bill of materials (BOM) of the TPS7H4010EVM is shown in Table 6-1 below.
Table 6-1. TPS7H4010EVM BOM
Designator Quantity Value Description Package
Reference
Part Number Manufacturer
!PCB1 1 Printed Circuit Board LP044 Any
C1, C8, C26 3 0.47 μF CAP, CERM, 0.47 μF, 50 V, +/– 10%,
X7R, 0805
0805 GRM21BR71H474KA88L MuRata
C2 1 22 μF CAP, CERM, 22 μF, 16 V, +/–10%, X7R,
1210
1210 GCM32ER71C226KE19L MuRata
C3, C19, C20, C21 4 47 μF CAP, CERM, 47 μF, 10 V, +/– 10%,
X7R, 1210
1210 GRM32ER71A476KE15L MuRata
C4 1 330 μF CAP, Tantalum Polymer, 330 μF, 10 V,
+/– 20%, 0.006 ohm, 7343-43 SMD
7343-43 T530X337M010ATE006 Kemet
C7, C25 2 0.47 μF CAP, CERM, 0.47 μF, 25 V, +/– 10%,
X7R, AEC-Q200 Grade 1, 0603
0603 GCM188R71E474KA64D MuRata
C9, C10, C27, C28 4 10 μF CAP, CERM, 10 μF, 50 V, +/– 10%,
X7R, AEC-Q200 Grade 1, 1210
1210 UMK325AB7106KMHT Taiyo Yuden
C15 1 68 pF CAP, CERM, 68 pF, 50 V, +/– 5%, C0G/
NP0, 0603
0603 GRM1885C1H680JA01D MuRata
C16, C34 2 2.2 μF CAP, CERM, 2.2 µF, 10 V,+/– 10%,
X7R, AEC-Q200 Grade 1, 0603
0603 GRM188R71A225KE15J MuRata
C33 1 22 pF CAP, CERM, 22 pF, 50 V, +/– 5%, C0G/
NP0, 0603
0603 GRM1885C1H220JA01D MuRata
H1, H2, H3, H4,
H5, H6
6 Machine Screw, Round, #4-40 x 1/4,
Nylon, Philips panhead
Screw NY PMS 440 0025 PH B&F Fastener
Supply
H7, H8, H9, H10,
H11, H12
6 Standoff, Hex, 0.5"L #4-40 Nylon Standoff 1902C Keystone
J1, J2, J3, J4, J5,
J10, J11, J12, J13,
J14
10 Standard Banana Jack, Uninsulated,
8.9 mm
Keystone575-8 575-8 Keystone
J6, J7, J15, J16 4 Header, 100 mil, 3x1, Gold, TH Header, 100 mil,
3x1, TH
HTSW-103-07-G-S Samtec
J8, J9, J17, J18 4 Compact Probe Tip Circuit Board Test
Points, TH, 25 per
TH Scope Probe 131-5031-00 Tektronix
J19, J20, J21, J22 4 Fixed Terminal Blocks MKDSP 10 HV/
2-10
HDR2 1929517 Phoenix Contact
L1 1 1.8 μH Inductor, Shielded, Composite, 1.8 μH,
21 A, 0.00405 Ω, SMD
7.2x7x7.5 mm XAL7070-182MEB Coilcraft
L3 1 3.3 μH Inductor, Shielded, Composite, 3.3 μH,
15.1 A, 0.01 Ω, SMD
7.2x7x7.5 mm XAL7070-332MEB Coilcraft
R1, R11 2 100 Ω RES, 100, 1%, 0.125 W, AEC-Q200
Grade 0, 0805
0805 CRCW0805100RFKEA Vishay-Dale
R2, R5, R12, R15 4 100 kΩ RES, 100 k, 1%, 0.1 W, AEC-Q200
Grade 0, 0603
0603 CRCW0603100KFKEA Vishay-Dale
R3, R13 2 0 Ω RES, 0, 5%, 0.1 W, AEC-Q200 Grade 0,
0603
0603 CRCW06030000Z0EA Vishay-Dale
R4 1 124 kΩ RES, 124 k, 1%, 0.1 W, AEC-Q200
Grade 0, 0603
0603 CRCW0603124KFKEA Vishay-Dale
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Table 6-1. TPS7H4010EVM BOM (continued)
Designator Quantity Value Description Package
Reference
Part Number Manufacturer
R6, R16 2 78.7 kΩ RES, 78.7 k, 1%, 0.1 W, 0603 0603 RC0603FR-0778K7L Yageo
R8, R18 2 200 kΩ RES, 200 k, 1%, 0.125 W, AEC-Q200
Grade 0, 0805
0805 CRCW0805200KFKEA Vishay-Dale
R9, R19 2 121 kΩ RES, 121 k, 1%, 0.125 W, AEC-Q200
Grade 0, 0805
0805 CRCW0805121KFKEA Vishay-Dale
R10, R20 2 10.0 kΩ RES, 10.0 k, 1%, 0.1 W, AEC-Q200
Grade 0, 0603
0603 CRCW060310K0FKEA Vishay-Dale
R14 1 43.2 kΩ RES, 43.2 k, 1%, 0.1 W, AEC-Q200
Grade 0, 0603
0603 CRCW060343K2FKEA Vishay-Dale
SH-J1, SH-J2, SH-
J3, SH-J4
4 Shunt, 100 mil, Gold plated, Black Shunt 2 pos. 100
mil
881545-2 TE Connectivity
TP1, TP15 2 Test Point, Multipurpose, Orange, TH Orange
Multipurpose
Testpoint
5013 Keystone
TP2, TP3, TP7,
TP8, TP9, TP10,
TP16, TP17, TP21,
TP22, TP23, TP24
12 Test Point, Multipurpose, Black, TH Black Multipurpose
Testpoint
5011 Keystone
TP4, TP5, TP18,
TP19
4 Test Point, Multipurpose, Red, TH Red Multipurpose
Testpoint
5010 Keystone
TP6, TP11, TP12,
TP13, TP20, TP25,
TP26, TP27, TP31,
TP32, TP33, TP34
12 Test Point, Multipurpose, Yellow, TH Yellow
Multipurpose
Testpoint
5014 Keystone
TP14, TP28, TP29,
TP30
4 Test Point, Multipurpose, White, TH White Multipurpose
Testpoint
5012 Keystone
U1, U2 2 3.5-V to 30-V, 6-A Synchronous Step-
Down Voltage Converter
WQFN30 TPS7H4010MRNPTSEP Texas Instruments
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7 TPS7H4010EVM Test Data
7.1 TPS7H4010EVM PVIN=5 V, VOUT=1.8 V, FSW=500 kHz
All data presented is at ambient room temperature (~23C) with device in Auto Mode unless noted otherwise.
Figure 7-1. PVIN=5 V, VOUT=1.8 V, FSW=500 kHz: VOUT vs IOUT
PVIN (V) IOUT (A) Output Voltage (V)
5.000 6.000 1.820
5.000 5.000 1.820
5.000 4.000 1.821
5.000 3.000 1.822
5.000 2.000 1.822
5.000 1.000 1.823
5.000 0.900 1.823
5.000 0.800 1.823
5.000 0.700 1.822
5.000 0.600 1.823
5.000 0.500 1.827
5.000 0.400 1.833
5.000 0.300 1.838
5.000 0.200 1.840
5.000 0.100 1.843
5.000 0.000 1.846
Average 1.828
Max Deviation below Avg -0.431%
Max Deviation above Avg 0.992%
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Figure 7-2. PVIN=5 V, VOUT=1.8 V, IOUT=6 A, FSW=500 kHz: Loop Response
Figure 7-3. PVIN=5 V, VOUT=1.8 V, FSW=500 kHz: Transient Response to current step from 2 A to 6 A at 1
A/us
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20 TPS7H4010EVM User's Guide SNVU744 – OCTOBER 2020
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