Texas Instruments TPS548B28EVM-023 User manual

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TPS548B28EVM-023 20-A, Buck Converter Evaluation Module
User's Guide
SNVU662–June 2020
TPS548B28EVM-023 20-A, Buck Converter Evaluation
Module
This user’s guide contains information for the TPS548B28EVM-023 evaluation module (EVM) as well as
for the TPS548B28 DC/DC converter. Also included are the performance specifications, the schematic,
and the list of materials for the TPS548B28EVM.
Contents
1 Introduction ................................................................................................................... 1
1.1 Background.......................................................................................................... 2
1.2 Performance Specification Summary ............................................................................ 2
1.3 Modifications......................................................................................................... 3
2 Schematic, List of Materials, and Layout ................................................................................. 5
2.1 Schematic............................................................................................................ 6
2.2 List of Materials ..................................................................................................... 7
2.3 Layout ................................................................................................................ 8
List of Figures
1 Safety Warnings ............................................................................................................. 2
2 TPS548B28EVM Top-Side Layout ........................................................................................ 9
3 TPS548B28EVM Internal Layer-1 Layout ................................................................................ 9
4 TPS548B28EVM Internal Layer-2 Layout............................................................................... 10
5 TPS548B28EVM Bottom-Side Layout................................................................................... 10
List of Tables
1 Input Voltage and Output Current Summary............................................................................. 2
2 TPS548B28EVM Performance Specification Summary ................................................................ 2
3 TPS548B28EVM Mode Pin Selection..................................................................................... 4
4 Enable Pin Selection ........................................................................................................ 4
5 TPS548B28EVM List of Materials......................................................................................... 7
Trademarks
D-CAP3 is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
1 Introduction
The TPS548B28 is a D-CAP3™ synchronous buck converter designed for 20 A output current, and the
evaluation module is designed to demonstrate the small printed-circuit-board areas that may be achieved
when designing with the device. The high-side and low-side switching MOSFETs are integrated in the
device package along with their gate drive circuitry. Rated input voltage and output current ranges for the
evaluation module are given in Table 1.

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1.1 Background
The EVM is setup to allow the user to evaluate the performance of the TPS548B28 IC, and easily make
changes to multiple settings. The low drain-to-source on resistance of the MOSFETs allows the device to
achieve high efficiencies and keep the junction temperature low at high output currents. There is no need
for external compensation components since this device is designed with D-CAP3™ control topology. On
the EVM the switching frequency and the operation mode are externally selectable using a jumper to set
the resistor from the MODE pin to AGND. An external resistor divider allows for an adjustable output
voltage. Additionally, the device provides adjustable soft start, adjustable OC limit threshold, external
reference input, and an open-drain power good indicator. Lastly the TPS548B28 device has a fixed
internal VIN under voltage lockout and externally adjustable UVLO using a resistor divider at the EN pin.
Table 1. Input Voltage and Output Current Summary
EVM INPUT VOLTAGE RANGE OUTPUT CURRENT
RANGE
TPS548B28 VIN = 8 V to 14 V 0 A to 20 A
Figure 1. Safety Warnings
1.2 Performance Specification Summary
A summary of the TPS548B28EVM performance specifications is provided in Table 2. Specifications are
given for an input voltage of VIN = 12 V and an output voltage of 1.0 V, unless otherwise specified. The
TPS548B28EVM is designed and tested for VIN = 8 V to 14 V. The ambient temperature is 25°C for all
measurements, unless otherwise noted. The design can be modified to perform over 4 V to 16 V.
Table 2. TPS548B28EVM Performance Specification Summary
SPECIFICATION TEST CONDITIONS MIN TYP MAX Unit
VIN voltage range (without internal
Bias) 8 12 14 V
Output voltage setpoint 1.0 V
Output current range VIN = 8 V to 14 V 0 20 20 A
Internal LDO Voltage 3.0 V
Operating frequency 800 kHz

O INTREF
FB HS FB LS
INTREF
V V
R R
V
_ _

u
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TPS548B28EVM-023 20-A, Buck Converter Evaluation Module
1.3 Modifications
These evaluation modules are designed to provide access to the features of the TPS548B28. Some
modifications can be made to this module.
1.3.1 Output Voltage Setpoint
To change the output voltage of the EVM, it is necessary to change the value of resistor R6 and R7. R9 is
fixed at 10 kΩ. Changing the total value of R6 plus R7 can change the output voltage above the 0.6V
reference voltage VINTREF. A two resistor configuration of R6+R7 is implemented to give the exact desired
output voltage setting. The value of R6 and R7 for a specific output voltage can be calculated using
Equation 1.
(1)
VINTREF= 0.6V
RFB_HS = R6+ R7
RFB_LS = R9= 10kΩ

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1.3.2 Frequency and Operation Mode Setting
To change the frequency and operation mode of the part, the MODE pin is used. J6 and the surrounding
circuitry allows for an easy change to the frequency and operation mode setting. All 6 options offered by
J6 are shown in Table 3
Table 3. TPS548B28EVM Mode Pin Selection
Switching Frequency (FSW)Operation Mode Under
Light Load Mode Pin Connections
Connection Jumper Setting
600 kHz Skip Mode Short to VCC Short Pins 1 and 2
800 kHz Skip Mode 243kΩ±10% to AGND Short Pins 3 and 4
1000 kHz Skip Mode 121kΩ±10% to AGND Short Pins 5 and 6
1000 kHz Forced CCM 60.4kΩ±10% to AGND Short Pins 7 and 8
800 kHz Forced CCM 30.1kΩ±10% to AGND Short Pins 9 and 10
600 kHz Forced CCM Short to AGND Short Pins 11 and 12
1.3.3 Enable Pin Selection
The converter can be enabled and disabled by J5.
Default setting: EN pin connected to VIN.
Table 4. Enable Pin Selection
Set On Connection Enable Selection
Pins 2-3 Shorted EN pin connected to VIN pins through resistor divider
J3 Open EN pin is left floating
Pins 1-2 Shorted EN pin connected to PGND
1.3.4 Remote Sensing
The EVM is not set-up for remote sensing by default. To set up remote sensing follow these steps:
1. Replace R8 and R11 with 100Ωresistors
2. Connect your sense points to the Vsns+ and Vsns- test points
1.3.5 Adjustable UVLO
The undervoltage lockout (UVLO) can be adjusted externally using R2 and R9. See the TPS548B28 Data
Sheet to get detailed instructions for setting the external UVLO.

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2 Schematic, List of Materials, and Layout
This section provides a schematic, a description of the TPS548B28EVM board layout, and layer
illustrations.

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2.1 Schematic
The following image illustrates the schematic for the TPS548B28EVM.

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2.2 List of Materials
Table 5 presents the list of materials for the TPS548B28EVM.
Table 5. TPS548B28EVM List of Materials
DES QTY DESCRIPTION PART NUMBER MANUFACTURER
C2 1 CAP, AL, 330 uF, 25 V, ±20%, 0.15 ohm, SMD, 330uF EEE-FC1E331P Panasonic
C3, C4, C5,
C6, C21,
C22
6 CAP, CERM, 22 uF, 25 V, ±20%, X6S, 1206_190 GRM31CC81E226ME11L MuRata
C7, C8,
C32, C33 4 CAP CER 1UF 25V X6S 0402 GRM155C81E105KE11D Murata
C9 1 CAP, CERM, 0.1 uF, 50 V, ±10%, X7R, AEC-Q200 Grade 1, 0603 CGA3E2X7R1H104K080A
ATDK
C10 1 CAP, CERM, 2.2 uF, 10 V, ±10%, X7R, 0603 GRM188R71A225KE15D MuRata
C13, C14,
C15, C16,
C26, C27,
C28, C29
8 CAP, CERM, 47 uF, 6.3 V, ±10%, X6S, 1206 GRM31CC80J476KE18L MuRata
C19 1 CAP, CERM, 0.22 uF, 16 V, ±10%, X7R, 0603 C1608X7R1C224K080AC TDK
L1 1 Inductor, Shielded, Composite, 300 nH, 33.4 A, 0.00106 ohm, SMD XAL7070-301MEB Coilcraft
R1, R17 2 RES, 0, 1%, 0.5 W, 1206 5108 Keystone
R2, R7, R11 3 RES, 0, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 RMCF0603ZT0R00 Stackpole Electronics Inc
R3, R12 2 RES, 30.1 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 CRCW060330K1FKEA Vishay-Dale
R4 1 RES, 20.0 k, 0.1%, 0.1 W, 0603 RT0603BRD0720KL Yageo America
R5 1 RES, 6.04 k, 1%, 0.1 W, 0603 CRCW06036K04FKEA Vishay-Dale
R6 1 RES, 6.65 k, 1%, 0.1 W, 0603 'RC0603FR-076K65L Yageo
R8 1 RES, 10.0, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 CRCW060310R0FKEA Vishay-Dale
R9, R10 2 RES, 10.0 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 CRCW060310K0FKEA Vishay-Dale
R13 1 RES, 60.4 k, 1%, 0.1 W, 0603 RC0603FR-0760K4L Yageo
R14 1 RES, 121 k, 1%, 0.1 W, 0603 RC0603FR-07121KL Yageo
R15 1 RES, 243 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 CRCW0603243KFKEA Vishay-Dale
U1 1 4-V to 16-V Input, 20-A Single Synchronous Step-Down Converter,
RWW0021A (VQFN-HR-21) TPS548B28RWWT Texas Instruments

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2.3 Layout
The board layout for the TPS548B28EVM is shown in Figure 2 through Figure 5. The top-side layer of the
EVM is laid out in a manner typical of a user application. The top, bottom, and internal layers are 2-oz.
copper.
The top layer contains the main power traces for VIN, VOUT, and SW. Also on the top layer are connections
for the remaining pins of the TPS548B28 and the majority of the signal traces. The top layer has a
dedicated ground plane for quiet analog ground that is connected to the main power ground plane at a
single point. The internal layer-1 is a large ground plane. The internal layer-2 contains an additional large
ground copper area as well as an additional VOUT copper fill. The bottom layer is another ground plane
with two additional traces for the output voltage feedback and various signals routed to test points and
headers. There are also additional VIN and VOUT planes on the bottom layer. The top-side ground traces
are connected to the bottom and internal ground planes with multiple via groupings placed around the
board.
The input decoupling capacitors and bootstrap capacitor are all located as close to the IC as possible.
Additionally, the voltage set point resistor divider components are kept close to the IC. The voltage divider
network ties to the output voltage at the point of regulation, the copper VOUT trace at the TP4 test point. An
additional input bulk capacitor is used to limit the noise entering the converter from the input supply.
Critical analog circuits that are noise sensitive are terminated to the quiet analog ground island on the top
layer.

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Figure 2. TPS548B28EVM Top-Side Layout
Figure 3. TPS548B28EVM Internal Layer-1 Layout

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Figure 4. TPS548B28EVM Internal Layer-2 Layout
Figure 5. TPS548B28EVM Bottom-Side Layout