Texas Instruments LMK5B33216EVM User manual

User’s Guide
LMK5B33216EVM User's Guide
ABSTRACT
The LMK5B33216EVM is an evaluation module for the LMK5B33216 Network Clock Generator and
Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping.
Table of Contents
1 Introduction.............................................................................................................................................................................2
2 EVM Quick Start......................................................................................................................................................................4
3 EVM Configuration..................................................................................................................................................................6
3.1 Power Supply..................................................................................................................................................................... 8
3.2 Logic Inputs and Outputs................................................................................................................................................... 9
3.3 Switching Between I2C and SPI...................................................................................................................................... 10
3.4 Generating SYSREF Request..........................................................................................................................................11
3.5 XO Input........................................................................................................................................................................... 11
3.6 Reference Clock Inputs....................................................................................................................................................13
3.7 Clock Outputs...................................................................................................................................................................13
3.8 Status Outputs and LEDS................................................................................................................................................ 13
3.9 Requirements for Making Measurements........................................................................................................................ 13
3.10 Typical Phase Noise Characteristics..............................................................................................................................14
4 EVM Schematics................................................................................................................................................................... 15
4.1 Power Supply Schematic................................................................................................................................................. 15
4.2 Alternative Power Supply Schematic............................................................................................................................... 15
4.3 Power Distribution Schematic.......................................................................................................................................... 16
4.4 LMK5B33216 and Input Reference Inputs IN0 to IN1 Schematic.................................................................................... 17
4.5 Clock Outputs OUT0 to OUT3 Schematic........................................................................................................................18
4.6 Clock Outputs OUT4 to OUT9 Schematic........................................................................................................................19
4.7 Clock Outputs OUT10 to OUT15 Schematic....................................................................................................................20
4.8 XO Schematic.................................................................................................................................................................. 21
4.9 Logic I/O Interfaces Schematic........................................................................................................................................ 22
4.10 USB2ANY Schematic.....................................................................................................................................................23
5 EVM Bill of Materials.............................................................................................................................................................24
5.1 Loop Filter and Vibration Nonsensitive Capacitors.......................................................................................................... 31
6 Appendix A - TICS Pro LMK5B33216 Software..................................................................................................................32
6.1 Using the Start Page........................................................................................................................................................ 32
6.2 Using the Status Page..................................................................................................................................................... 35
6.3 Using the Input Page........................................................................................................................................................36
6.4 Using APLL1, APLL2, and APLL3 Pages........................................................................................................................ 38
6.5 Using the DPLL1, DPLL2, and DPLL3 Pages..................................................................................................................40
6.6 Using the Validation Page................................................................................................................................................ 43
6.7 Using the GPIO Page.......................................................................................................................................................43
6.8 Using the Outputs Page................................................................................................................................................... 44
6.9 EEPROM Page................................................................................................................................................................ 46
6.10 Design Report Page.......................................................................................................................................................47
7 Revision History................................................................................................................................................................... 47
Trademarks
All trademarks are the property of their respective owners.
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1 Introduction
Overview
The LMK5B33216EVM is an evaluation module for the LMK5B33216 Network Clock Generator and
Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping. The
LMK5B33216 integrates three Analog PLLs (APLL) and three Digital PLLs (DPLL) with programmable loop
bandwidth. The EVM includes SMA connectors for clock inputs, optional off-board APLL reference input, and
clock outputs to interface the device with 50-Ω test equipment. The onboard TCXO allows the LMK5B33216 to
be evaluated in free-running, locked, or holdover mode of operation. The EVM can be configured through the
onboard USB microcontroller (MCU) interface using a PC with TI's TICS Pro software graphical user interface
(GUI). TICS Pro can be used to program the LMK5B33216 registers.
Features
• LMK5B33216
What is Included
• LMK5B33216EVM
• 3-ft. mini-USB cable (MPN 3021003-03)
What is Needed
• Windows PC with TICS Pro Software GUI
• Test Equipment
– DC power supply (12 V, 1A)
What is Recommended
• Test equipment:
– Source signal analyzer
– Signal generator / reference clock
– Real-time oscilloscope
– Precision frequency counter
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Figure 1-1 shows the jumper position with red markings. Figure 1-1 shows the DIP switch positions in either
green boxes (for ON) or red boxes (for OFF) in the appropriate location.
OUT9_P OUT9_N OUT8_N OUT8_P OUT15_N OUT15_P OUT14_N OUT14_P
IN1_N IN1_P IN0_N IN0_P
OUT10_P
OUT10_N
OUT11_N
OUT11_P
OUT12_P
OUT12_N
OUT13_N
OUT13_P
OUT0_P
OUT0_N
OUT1_N
OUT1_P
OUT7_P
OUT7_N
OUT6_N
OUT6_P
OUT4_P
OUT4_N
OUT5_N
OUT5_P
OUT3_P
OUT3_N
OUT2_N
OUT2_P
VIN1
VIN2
Figure 1-1. LMK5B33216EVM Default Setting of Jumpers and DIP Switches
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2 EVM Quick Start
Table 2-1 describes the default jumper positions for the EVM to power the device from a single 12-V supply
provided to VIN4. In positional information about jumpers, “adjacent designator” means the jumper is placed
adjacent to the designator. “Opposite designator” means the jumper is placed opposite of the designator.
Table 2-1. Default Jumper and DIP Switch Settings
CATEGORY REFERENCE
DESIGNATOR POSITION DESCRIPTION
Power
JP1 1-2 (opposite designator) LMK5B33216 VDD = 3.3 V from DCDC1 provided by
U500 on top of the PCB.
JP2 1-2 (opposite designator) LMK5B33216 VDDO = 3.3 V from DCDC1 by U500 on
top of the PCB.
JP4 1-2 (opposite designator) XO VCC = 3.3 V from DCDC1 provided by U500 on
top of PCB.
Communication JP5 1-2, 3-4 Connect I2C from onboard USB2ANY to LMK5B33216
LMK5B33216 Control Pins
S3 S3[1:2] = OFF SCS_ADD = no pullup or pulldown.
S1, S2, S4 Sx[1,2] = OFF
Sx[3,4] = ON Enable 3.9k pulldown on GPIO0, GPIO1, and GPIO2
To begin using the LMK5B33216, follow the steps below.
Hardware Setup
1. Verify the EVM default jumper and DIP switch settings shown in Figure 1-1.
2. Connect the 12-V external power DC power supply (1-A limit) to:
a. VIN4 and GND terminals on header J500 (pins 4and 5, see Figure 3-2.)
3. Connect references:
a. 25-MHz reference clock to IN0_P/N and/or,
b. 25-MHz reference clock to IN1_P/N
4. Connect the USB cable to the USB port at J41.
Software Setup
1. If not already installed, install TICS Pro software from TI website: TICS Pro Software
2. If the MATLAB R2015b (9.0)* 64-bit runtime is not already installed, download and install from MathWorks
website. While optional for programming and evaluating the default profile settings, the Matlab Runtime is
necessary for any application that needs to modify the DPLL loop filter settings. See Matlab Runtime.
3. Start TICS Pro software.
4. Select the LMK5B33216 profile from Select Device → Network Synchronizer Clock (Digital PLLs) →
LMK5B33216.
5. Confirm communications with the board by:
a. Click USB communications from the menu bar.
b. Click Interface to launch the Communication Setup pop-up window.
c. Check these fields in the Communication Setup pop-up window:
i. Ensure USB2ANY is selected as the interface.
ii. In case of multiple USB2ANY, select desired interface. If a USB2ANY is currently in use in another
TICS Pro, you must release that interface by changing its interface setting to DemoMode.
iii. Click Identify to blink LED shown in Figure 2-1. This confirms you are connected to the board you
expect. Be aware that USB2ANY devices connected to the PC but not attached to by a TICS Pro
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instance may blink at a slow rate of 1 second on, 1 second off continuously. After clicking the Identify
button, the LED will flash quickly at about 0.5 second on, 0.5 second off for about 5 seconds.
Figure 2-1. USB LED
Program the LMK5B33216
1. Toggle the switch S5 (PDN/RESET).
2. Program all the registers:
a. Press the Write All Regs button in toolbar,
b. Select USB Communications in the menu bar, then select Write All Registers, or
c. Press Ctrl + L.
3. Check the current consumption (maximum 1.3 A).
4. Check LMK5B33216 Status as shown in Figure 2-2.
a. Go to the Status page of the GUI.
b. Click Read Status Bits.
c. Make sure to clear the latched bits. To clear latched bits:
i. Press the Clear Latched Bits button.
ii. Select Read Status Bits.
d. Wait to confirm the change. It may take some time for the DPLL status bits to reflect lock.
Figure 2-2. Read Status Bits
Measure
Measurements can now be made at the clock outputs.
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3 EVM Configuration
The LMK5B33216 is a highly-configurable clock chip with multiple power domains, PLL domains, and clock input
and output domains. To support a wide range of LMK5B33216 use cases, the EVM was designed with more
flexibility and functionality than needed to implement the chip in a customer system application.
This section describes the power, logic, and clock input and output interfaces on the EVM, as well as how to
connect, set up, and operate the EVM. Refer to Figure 4-1.
Table 3-1. Key Components Reference Designators and Descriptions
ITEM NO. REFERENCE
DESIGNATORS DESCRIPTION
1 U1 LMK5B33216
2 J500 (VIN4 terminal block header) External Supply, +12-V DC using default
configuration.
3
A Y1
Onboard TCXO. Y1 will provide improved
holdover stability and allow narrower DPLL
loop bandwidths to be used in comparison to
the external XO input.
B J8 SMA connector for external XO. To use the
external XO, remove the jumper from JP4.
4 J4/5, J6/7
SMA Ports for Clock Inputs (IN0_P/N and
IN1_P/N).
IN0_N is not populated and IN0_P is
configured for single ended input. IN1 is
configured for differential input.
5
J9/11, J10/12, J13/15, J14/16, J17/19,
J18/20, J21/J23, J22/24, J25/27, J26/28,
J29/31, J30/32, J33/35, J34/36, J37/39,
J38/40
SMA Ports for Clock Outputs
6 S5
Normally open. Push button for device power
down (PDN pin). R76 enables control of the
PDN pin through the GUI.
R76 is installed by default.
7 JP5 Jumper header for I2C/SPI interface (MCU to
LMK5B33216)
8 D6 SCL or SCK busy indication LED.
9 J41 USB Port for MCU
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OUT9_P
OUT9_N OUT8_N
OUT8_P
OUT15_N
OUT15_P
OUT14_N
OUT14_P
IN1_N
IN1_P
IN0_N
IN0_P
OUT10_P
OUT10_N
OUT11_N
OUT11_P
OUT12_P
OUT12_N
OUT13_N
OUT13_P
OUT0_P
OUT0_N
OUT1_N
OUT1_P
OUT7_P
OUT7_N
OUT6_N
OUT6_P
OUT4_P
OUT4_N
OUT5_N
OUT5_P
OUT3_P
OUT3_N
OUT2_N
OUT2_P
VIN1
VIN2
5
5
5
4
2
9
1
6
8
3B
7
3A
Figure 3-1. Key Components - EVM Top Side
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3.1 Power Supply
The LMK5B33216 has VDD and VDDO supply pins that operate from 3.3 V ± 5%.
J500 is the main power terminal to the external power supply. Power SMA port VIN1 (J2) provides an alternative
connector style to apply power through coax cable. By default this SMA connector is not populated.
On the EVM, there are three methods for supplying power.
1. The default power configuration uses the onboard DC/DC supply (U500) to power all VDD and VDDO pins
as well as the onboard XO from an external 12-V supply input to VIN4 on J500.
2. The LDO power configuration uses three separate LDO regulators (U9, U10, and U11) to power the VDD,
VDDO, and XO from an external 5-V supply input to VIN1 on J500 (or J2).
3. The direct power configuration allows for separate voltage supplies for the VDD, VDDO, and XO. In the
direct power configuration mode, an external 3.3-V supply is provided to VIN1 to power the VDD pins, an
external 3.3-V supply is provided to VIN2 to power the VDDO pins, and an external 3.3-V supply is provided
to VIN3 to power the onboard XO.
Note
Not every power connection is used or required to operate the EVM. Other power configurations are
possible. See the power schematics in Figure 4-1 and Figure 4-3.
VIN1
VIN2
OUT2_P
VIN1
VIN2
VIN3
VIN4
Input Supply:
12 V to VIN4 on
J500 to power
DCDC
XO Supply:
Select
DCDC1 to
power XO
VDDO Supply:
Select DCDC1
to power VDDO
VDD Supply:
Select DCDC1
to power VDD
GND
Figure 3-2. Default Power Jumper Configuration
Figure 3-2 shows the default power jumper locations and settings. Table 3-2 shows the suggested power
configurations for the LMK5B33216.
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Table 3-2. Suggested Power Configurations
CONNECTION NAME
ONBOARD DC/DC SUPPLY
(DEFAULT) ONBOARD LDO REGULATORS DIRECT EXTERNAL SUPPLIES
VDD = 3.3 V (DCDC1)
VDDO = 3.3 V (DCDC1)
XO = 3.3 V (DCDC1)
VDD = 3.3 V (LDO1)
VDDO = 3.3 V (LDO2)
XO = 3.3 V (LDO3)
VDD = 3.3 V (EXT. VIN1)
VDDO = 3.3 V (EXT. VIN2)
XO = 3.3 V (EXT. VIN3)
J500 PWR • Pin 1 (VIN1): n/a
• Pin 2 (VIN2): n/a
• Pin 3 (VIN3): n/a
• Pin 4 (VIN4): Connect to
external 12-V supply
• Pin 5 (GND): Connect to
supply ground
• Pin 1 (VIN1): Connect to
external 5-V supply
• Pin 2 (VIN2): n/a
• Pin 3 (VIN3): n/a
• Pin 4 (VIN4): n/a
• Pin 5 (GND): Connect to
supply ground
• Pin 1 (VIN1): Connect to
external 3.3-V supply
• Pin 2 (VIN2): Connect to
external 3.3-V supply
• Pin 3 (VIN3): Connect to
external 3.3-V supply
• Pin 4 (VIN4): n/a
• Pin 5 (GND): Connect to
supply ground
JP1 VDD • Tie pins 1-2 (opposite to
designator) to select 3.3 V
from DCDC1 to VDD Plane
• Tie pins 3-4 (middle pins) to
select 3.3 V from LDO1 to
VDD Plane
• Tie pins 5-6 (adjacent to
designator) to select external
VIN1 to VDD Plane
JP2 VDDO • Tie pins 1-2 (opposite to
designator) to select 3.3 V
from DCDC1 to VDDO Plane
• Tie pins 3-4 (middle pins) to
select 3.3 V from LDO2 to
VDDO Plane
• Tie pins 5-6 (adjacent to
designator) to select external
VIN2 to VDDO Plane
JP4 XO • Tie pins 1-2 (opposite to
designator) to select 3.3 V
from DCDC1 to XO supply
• Tie pins 3-4 (middle pins) to
select 3.3 V from LDO3 to
XO supply
• Tie pins 5-6 (adjacent to
designator) to select external
VIN3 to XO supply
3.2 Logic Inputs and Outputs
The logic I/O pins of the LMK5B33216 support different functions depending on the device start-up mode chosen
by the GPIO1 input level upon POR.
The default logic input pin states are determined by onboard pullup or pulldown resistors, but some input pins
can be driven to high or low state by the MCU output or DIP switch control. The MCU can be controlled
from a PC running TICS Pro software to program the device registers through I2C or SPI and also drive the
LMK5B33216 logic inputs. To allow the MCU to control the pin input, SW[2] of the DIP switch correlating with
controlled GPIO must be set to on.
See Table 3-3 for the logic pin mapping tables for the device start-up modes.
Table 3-3. Device Start-Up Modes
GPIO1 INPUT LEVEL(1) START-UP MODE
Low I2C Mode
High SPI Mode
(1) The input levels on these pins are sampled only during POR.
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3.3 Switching Between I2C and SPI
To switch the EVM between I2C and SPI modes, the switches and jumpers must be configured as follows:
I2C
GPIO Switches:
S1: 10 kΩ pull-up
S2: MSP430
S3: 3.9 kΩ pull-down
S4: LED (lit = high)
I2C ADD:
S1: pull-up
S2:pull-down
Figure 3-3. I2C Mode Jumper Configuration
SPI
GPIO Switches:
S1: 10 kΩ pull-up
S2: MSP430
S3: 3.9 kΩ pull-down
S4: LED (lit = high)
I2C ADD:
S1: pull-up
S2:pull-down
Figure 3-4. SPI Mode Jumper Configuration
In SPI mode, GPIO2 must also be configured as STATUS or INT, SPI Readback Data (SDO), Active High, and
CMOS to support SPI readback.
Figure 3-5. GPIO2 Setting for SPI Mode
Communication protocols must be set in TICS Pro. From the menu bar, select USB communications → Interface
to get the Communication Setup window and change the protocol.
Figure 3-6. Communication Setup Window (Changing from I2C to SPI)
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3.4 Generating SYSREF Request
A software request, GPIO0, or GPIO1 can be used to generate a SYSREF request. The TICS Pro software and
EVM is designed to use GPIO2 for SPI readback (SDO). Accordingly, GPIO2 is not listed in the pins as it is
dedicated for SPI readback. In user application, any GPIO pin may be used.
Connect the desired GPIO pin to the MCU by setting S2 as ON on the switch block for the desired GPIO. Then,
make sure the GPIO pin is configured for SYSREF_REQ on the GPIO tab of the GUI. A SYSREF Request can
now be issued by toggling the GPIO buttons in the Pins section of the User Controls tab.
Figure 3-7. GPIO Setting for SYSREF Request
Figure 3-8. GPIO Pin Selection for SYSREF
3.5 XO Input
The LMK5B33216 has an XO input (XO pin) to accept a reference clock for the Fractional-N APLLs. The XO
input determines the output frequency accuracy and stability in free-run or holdover modes. For synchronization
applications like SyncE or IEEE 1588, the XO input would typically be driven by a low-frequency TCXO or OCXO
that conforms to the frequency accuracy and holdover stability requirements of the application. For proper DPLL
operation, the XO frequency must have a non-integer frequency relationship with the VCO output frequency
of any APLLs that uses the XO input as its reference. The non-integer relationship should be greater than
0.05 away from an integer boundary (meaning > 0.05 and < 0.95). When configuring the LMK5B33216 as a
clock generator (DPLL not used), then the XO frequency can have an integer relationship with the APLL output
frequency.
The XO input of the LMK5B33216 has programmable on-chip input termination and AC-coupled input biasing
options to support any clock interface type.
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Jumpers to power onboard TCXO:
The onboard TCXO can be powered in
three manners:
1. Direct 3.3-V supply provided to VIN3.
Tie pins 5-6 (adjacent to JP4 designator).
2. 3.3-V supply provided from output of
LDO3 (U9). Tie pins 3-4.
3. 3.3-V supply provided from output of
DCDC1 (U500). Tie pins 1-2 (opposite to
JP4 designator).
Remove jumper from JP4 when
providing external XO input.
External XO Input
Onboard 48 MHz
TCXO
Figure 3-9. XO Input
3.5.1 48-MHz TCXO (Default)
By default, the EVM is populated with a 48-MHz, 3.3-V LVCMOS, low-jitter TCXO, designated as Y1 (3.2 mm
x 2.5 mm), which drives the XO input of the LMK5B33216 with the onboard termination and AC coupling. See
Figure 3-9. All LMK5B33216 EVMs have a TXC 7N48071001 48-MHz TCXO populated on Y1. Y1 can be used
to evaluate various frequency configurations.
3.5.2 External Clock Input
Another option is to feed an external clock to the SMA port (J8) to drive the XO input. See Figure 3-9. This path
can be connected to the XO input pins. Y1 should be powered down when using the external XO input path. To
power down Y1 and use an external XO input, the jumper on JP4 must be removed. Suggested XO frequencies
for best device performance are frequencies of 38.88 and 48 MHz.
3.5.3 Additional XO Input Options
For flexibility, the EVM provides additional XO input options (use one at a time). C70 allows an external
reference to be provided at SMA connector XO (J8). C71 allows one of the onboard XO/TCXO/OCXO footprints
to be used.
By default, Y1 is populated with a 48-MHz TCXO and selected with the populated R43 and R206. R43 provides
the output clock of Y1 to the XO pin of the LMK5B33414 and R206 provides power to Y1.
Additional PCB footprints are available to install alternate components for performance evaluation of specific
oscillators. These additional footprints are Y2 (2.5 x 2.0 mm), Y3 (3.2 mm x 2.5 mm), Y4 (9.7 mm x 7.5 mm), Y5
(25 mm x 22 mm), and U4 (2.5 mm x 2 mm).
When using Y2, Y3, Y4, Y5, or U4, R43 and R206 must be removed to power down and isolate the output of
Y1. When populating Y2, R46 must be populated to provide Y2's output to the XO pin. When populating Y3,
R47 must be populated to provide Y3's output to the XO pin. When populating Y4, R48 must be populated to
provide Y4's output to the XO pin. When populating Y5, R49 must be populated to provide Y5's output to the XO
pin. When populating U4, R50 must be populated to provide U4's output to the XO pin. Section 4.8 shows the
components described above.
Take care if more than one device is installed to remove resistors to power down unused oscillators and isolate
their outputs as described above.
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3.5.4 APLL Reference Options
The LMK5B33216 APLLs may accept any other APLL output as a reference instead of the XO. The BAW
on APLL3 provides a good option for a high-frequency cascaded APLL reference. Figure 6-2 shows how to
configure the APLL reference to be cascaded from another APLL.
3.6 Reference Clock Inputs
The LMK5B33216 has two DPLL reference clock input pairs (IN0_P/N and IN1_P/N) with configurable input
priority and input selection modes. The inputs have programmable input type, termination, and biasing options to
support any clock interface type.
External LVCMOS or Differential reference clock inputs can be applied to the SMA ports, labeled IN0_P/N and
IN1_P/N. All SMA inputs are routed through 50-Ω single-ended traces and DC-coupled to the corresponding
IN0_P/N and IN1_P/N pins of the LMK5B33216. Single-ended signals should be connected to the noninverting
input, IN0_P or IN1_P. EVM default intends IN0 for single-ended input as the IN0_N SMA connector is not
populated.
3.7 Clock Outputs
The LMK5B33216 has 16 clock output pairs (OUT[0:15]_P/N).
OUT0 is configured as DC-coupled for LVCMOS evaluation purposes. OUT1, OUT2, and OUT3 have 50 Ω to
GND followed by an AC-coupling capacitor for HCSL evaluation purposes.OUT4 to OUT15 are AC-coupled to
the SMA ports for LVDS and HSDS evaluation purposes.
WARNING
DC-coupled clocks should not be directly connected to RF equipment which cannot accept DC
voltage greater than 0 V. For example, spectrum analyzers and phase noise analyzers.
3.8 Status Outputs and LEDS
Status outputs signals can be configured on the GPIO0, GPIO1, and GPIO2 pins. The status output types are
3.3-V LVCMOS or NMOS open-drain.
3.9 Requirements for Making Measurements
When performing measurements with the LMK5B33216EVM, the following procedures must be completed:
1. Ensure all required outputs have proper termination components installed to match the desired output types.
Figure 3-10 shows the recommended output terminations for each output format.
LMK5B33216
Output Driver
Oscilloscope
Internal input biasing
RB RB
Driver
LVDS
HSDS
HCSL
RB (Ω)
open
open
50
Figure 3-10. Output Termination Recommendations
1. Ensure all enabled outputs that are not connected to any test equipment have a 50-Ω SMA termination.
Figure 3-11 shows an example of a 50 Ω SMA termination.
Figure 3-11. 50-Ω SMA Termination
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3.10 Typical Phase Noise Characteristics
These plots show the typical phase noise performance for common frequencies outputted from the BAW
(VCO3).
The EVM configuration used to obtain these measurements is as follows:
1. XO frequency = 48 MHz (Onboard TCXO)
2. Outputs were configured as HSDS outputs following the methods described in Section 3.9.
Figure 3-12. APLL3 312.5-MHz Phase Noise
Performance
Figure 3-13. APLL3 156.25-MHz Phase Noise
Performance
Figure 3-14. APLL3 125-MHz Phase Noise
Performance
Figure 3-15. APLL3 100-MHz Phase Noise
Performance
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4 EVM Schematics
4.1 Power Supply Schematic
SELECT TPS62913 or BYPASS
TPS62913 for VDD and VDDO rails
VDDO_PLANE
TP5
VDDO
1uF
C21
TP1
VDD_DCDC
DNP
TP7
VIN2
DNP
47µF
C27
VIN2
DUT VDDO OUTPUT POWER (3.3V)
TPS62913 OUT: 3.3 V
TPS62913 OUT: 3.3 V
VDD_PLANE
TP2
VDD
1uF
C6
DUT VDD CORE POWER (3.3V)
20V
D2
DIODE_SCHOTTKY
VDDO
TP4
VDDO_DCDC
DNP
VIN3
1
2
3 4 5
J3
VIN2
DNP
POWER INPUT
SH2
SNT-100-BK-G
SH1
SNT-100-BK-G
VDD
EN/SYNC
1
SW 2
VO 3
PGND
4PG 5
VIN
6
PSNS
7NR/SS 8
FB 9 S-CONF
10
TPS62913RPUT
U500
470nF
25V
C512
VIO_3P3V
S-CONF top resistor = 0 for 2.2MHz no sync no discharge, open if bottom resistor is chosen
S-CONF bottom resistor = 18.2k for 2.2MHz, no sync, with output discharge
18.2k
R502
S-CONF bottom resistor = 27.4k for 2.2MHz +/-20% sync with discharge
0
R500
0805
10V
22uF
C501
0402
25V
2200pF
C507
0805
10V
22uF
C502
0805
10V
22uF
C503
GND
GND
0805
10uF
25V
C505
0805
10uF
25V
C506
XGL4030-222MEC
L501
+12V
270pF
50V
C511
GND
5.60k
R501
1.80k
R504
DNP
0805
10V
22uF
C508
0805
10V
22uF
C509
1 2
L500
BLE18PS080SN1 0805
10V
22uF
C510
10V
10uF
C513
GND GND
1 2
L502
BLE18PS080SN1
0402
25V
2200pF
C514
GND
0402
25V
2200pF
C504
TP501
VDD_XO_DCDC
DNP
10V
10uF
C515
GND GND
1 2
L503
BLE18PS080SN1
0402
25V
2200pF
C516
35V
47uF
C500
10uF
C23
23.2k
R8
13.3k
R9
1-A LDO REG (LDO3) for XO rail
10uF
C22
LDO3 OUT 3.3V
IN
1
IN
2
IN[CP]
3
CP
4
EN
5
GND[CP]
6GND 7
FB 8
SET 9
OUT[FB] 10
OUT 11
OUT 12
DAP 13
LP38798SD-ADJ/NOPB
U9
10nF
C24
LDO3_IN
LDO3
47k
R203
0.01uF
C156
GND
1
2
3
4
5
J500
393570005
1 2
3 4
5 6
JP1
61000621121
LDO1
1 2
3 4
5 6
JP2
61000621121
LDO2
VIN4
SH4
SNT-100-BK-G
1 2
3 4
5 6
JP4
61000621121
VCC_XO
VIN1
1
2
3 4 5
J2
VIN1
DNP
47µF
C10
20V
D1
DIODE_SCHOTTKY
GND
Figure 4-1. Power Supplies
4.2 Alternative Power Supply Schematic
1-A LDO REG (LDO1, LDO2) for DUT VDD & VDDO rails
IN
1
IN
2
IN[CP]
3
CP
4
EN
5
GND[CP]
6GND 7
FB 8
SET 9
OUT[FB] 10
OUT 11
OUT 12
DAP 13
LP38798SD-ADJ/NOPB
U10
IN
1
IN
2
IN[CP]
3
CP
4
EN
5
GND[CP]
6GND 7
FB 8
SET 9
OUT[FB] 10
OUT 11
OUT 12
DAP 13
LP38798SD-ADJ/NOPB
U11
10uF
C1
10nF
C7
10uF
C8
10nF
C13
10uF
C2
23.2k
R1
13.3k
R2
10uF
C9
23.2k
R3
13.3k
R5
LDO1
LDO2
47k
R201
0.01uF
C154
GND
47k
R202
0.01uF
C155
GND
VIN1
Figure 4-2. Alternative Power Supply
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4.3 Power Distribution Schematic
VDD CORE SUPPLY DIST & FILTERING
FB2
FB4
FB6
FB8
FB1
FB7
10uF
C32
10uF
C38
10uF
C44
10uF
C50
VDDO OUTPUT SUPPLY DIST & FILTERING
VDD_PLANE VDDO_PLANE
10uF
C29
DNP
10uF
C47
0.1uF
C28
0.1uF
C46
0.1uF
C31
0.1uF
C37
0.1uF
C43
0.1uF
C49
VDDO_23
VDDO_4TO7
VDDO_8TO13
FB5
1uF
10V
C41
0.1uF
C40
FB3
10uF
C35
DNP
0.1uF
C34
FB9
10uF
C53
0.1uF
C52
TP19
GND
TP21
GND
TP23
GND
TP25
GND
Green
12
D3
VDD PWR
470
R13
Green
12
D4
VDDO PWR
470
R14
POWER LED INDICATORS (DUT, XO, TCXO)
Green
12
D5
XO PWR
470
R15
GND TEST POINTS
TP20
GND
TP22
GND
TP24
GND
TP26
GND
VDDGPIO
FB11
10uF
C59
0.1uF
C58
0.1uF
C55
10uF
C56
FB10
TP8
VDD_IN0
DNP
TP10
VDD_IN1
DNP
TP12
VDD_DIG
DNP
TP14
VDD_APLL1_XO
DNP
TP16
VDD_APLL2
DNP
TP18
VDD_APLL3
DNP
VDD_PLANE VDDO_PLANE VCC_XO
TP9
VDDO_01
DNP
TP11
VDDO_23
DNP
TP13
VDDO_4TO7
DNP
TP15
VDDO_8TO13
DNP
VDDO_1415
0.1uF
C42
0.1uF
C48
0.1uF
C54
0.1uF
C60
0.1uF
C30
0.1uF
C36
0.1uF
C33
0.1uF
C39
0.1uF
C57
0.1uF
C45
0.1uF
C51
NT1
NT_0603
0
R11
0
R16
0
R18
0
R20
0
R22
0
R25
0
R23
0
R21
0
R19
0
R17
0
R12
VDD_IN0
VDD_IN1
VDD_DIG
VDD_APLL1_XO
VDD_APLL2
VDD_APLL3
VDDO_01
TP17
VDDO_1415
0
R24
DNP
VDDO_1415 for LMK5B33216; VDD_IN23 for LMK5B33414
Figure 4-3. Power Distribution
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4.4 LMK5B33216 and Input Reference Inputs IN0 to IN1 Schematic
OUT1_P
OUT1_N
LF2
LF1
OUT0_P
OUT0_N
OUT2_P
OUT2_N
OUT3_P
OUT3_N
OUT4_P
OUT4_N
OUT5_P
OUT5_N
OUT6_P
OUT6_N
OUT7_P
OUT7_N
XO_P
LMKSDIO
LMKSCK
LMKGPIO0
LMKGPIO1
LMKGPIO2
LMKPDN
VDDO_23
VDD_APLL3
VDDO_01
VDDO_4TO7
VDDO_8TO13
VDD_APLL1_XO
VDD_IN1
VDD_DIG
DUT
DUT LDO BYP CAPS
LOOP FILTER C2 SELECTION
IN0_P
IN0_N
25V
100nF
C72
VDD_APLL2
25V
0.047µF
C76
DNP
470nF
10V
C75
25V
0.047µF
C73
DNP
OUT8_P
OUT8_N
OUT9_P
OUT9_N
OUT10_P
OUT10_N
OUT11_P
OUT11_N
OUT12_P
OUT12_N
OUT13_P
OUT13_N
IN1_P
IN1_N
OUT14_P
OUT14_N
OUT15_P
OUT15_N
LF3
LMKSCS_ADD
VDD_IN0
LMK5B33216RGCR
VDD_APLL1_XO
8
VDD_APLL2
23
VDD_APLL3
47
VDD_DIG
41
VDD_IN0
33
VDD_IN1
37
VDDO_01
1
VDDO_23
11
VDDO_1415
44
VDDO_4567
28
VDDO_8910111213
55
OUT0_N 3
OUT0_P 2
OUT1_N 4
OUT1_P 5
OUT2_N 13
OUT2_P 12
OUT3_N 14
OUT3_P 15
OUT4_N 26
OUT4_P 27
OUT5_N 25
OUT5_P 24
OUT6_N 30
OUT6_P 29
OUT7_N 31
OUT7_P 32
OUT8_N 52
OUT8_P 51
OUT9_N 53
OUT9_P 54
OUT10_N 57
OUT10_P 56
OUT11_N 58
OUT11_P 59
OUT12_N 61
OUT12_P 60
OUT13_N 62
OUT13_P 63
OUT14_N 43
OUT14_P 42
OUT15_N 45
OUT15_P 46
PD
36
SCK
17
SCS_ADD_TOD
18 SDIO
16
Thermal_Pad 65
XO_P
9
LF1 6
LF2 19
LF3 49
CAP_APLL1
7
CAP_APLL3
48
GPIO0
50
GPIO1
64
GPIO2
10
CAP1_APLL2
22
CAP2_APLL2
21
CAP3_APLL2
20
CAP_DIG
40
IN0_N
35 IN0_P
34
IN1_N
38 IN1_P
39
U1
EXT. SMA XO CLK
SMA_XO_P XO2_P
0
R41
1
2
3 4 5
J8
142-0701-201
49.9
R42
DNP
XO1_P
0.1uF
R40
0.1uF
C70
0.1uF
C71
25V
100nF
C67
25V
0.047µF
C68
DNP
SMA_IN0_P
SMA_IN0_N
0
R30
0
R26
0
R31
0
R27
51
R32
51
R28
DNP
R_IN0_P
R_IN0_N
100
R29
DNP
IN0_N
IN0_P
SMA_IN1_P
SMA_IN1_N
0
R37
0
R33
0
R38
0
R34
51
R39
DNP
51
R35
DNP
R_IN1_P
R_IN1_N
100
R36
DNP
IN1_P
IN1_N
VDDO_1415
100nF
50V
C61
10uF
C62
10uF
C6410uF
C63
10uF
C65
10uF
C66
1
2
3 4 5
J4
IN0_P
1
2
3 4 5
J5
IN0_N
DNP
1
2
3 4 5
J6
IN1_P
1
2
3 4 5
J7
IN1_N
XO3
DPLL INPUT 1
DPLL INPUT 0
C1PLL2
CPLL1
CDIG
C2PLL2
C3PLL2
CPLL3
50V
0.1µF
C69
DNP
50V
0.1µF
C74
DNP
50V
0.1µF
C77
DNP
TP27
LF1
TP28
LF2
TP29
LF3
ClassName: XO_trace ClassName: XO_trace
ClassName: XO_trace
ClassName: XO_trace
ClassName: XO_trace
ClassName: IN_trace
ClassName: IN_trace
ClassName: IN_trace
ClassName: IN_trace ClassName: IN_trace
ClassName: IN_trace
ClassName: IN_trace
ClassName: IN_traceClassName: IN_trace
ClassName: IN_trace
ClassName: IN_trace
ClassName: IN_trace
Requires capacitor at R27 if external
50 ohms to ground is used.
Figure 4-4. LMK5B33216 and Input Reference Inputs IN0 to IN1
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4.5 Clock Outputs OUT0 to OUT3 Schematic
OUT0-OUT3 CLOCK OUTPUTS
49.9
R78
DNP
49.9
R82
DNP
SMA_O0_P
SMA_O0_N
OUT0_P
OUT0_N
0
R132
0
R128
49.9
R79
DNP
49.9
R85
DNP
SMA_O1_P
SMA_O1_N
OUT1_P
OUT1_N
0.1uF
C98
0.1uF
C100
49.9
R86
DNP
49.9
R90
DNP
SMA_O2_P
SMA_O2_N
OUT2_P
OUT2_N
0.1uF
C101
0.1uF
C103
49.9
R88
DNP
49.9
R92
DNP
SMA_O3_P
SMA_O3_N
OUT3_P
OUT3_N
0.1uF
C102
0.1uF
C104
1
2
3 4 5
J9
OUT0_P
1
2
3 4 5
J11
OUT0_N
1
2
3 4 5
J10
OUT1_P
1
2
3 4 5
J12
OUT1_N
1
2
3 4 5
J14
OUT3_P
1
2
3 4 5
J16
OUT3_N
1
2
3 4 5
J13
OUT2_P
1
2
3 4 5
J15
OUT2_N
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1aClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1b
0
R6
0
R10
0
R81
0
R84
0
R7
0
R80
0
R83
0
R87
49.9
R167
DNP
49.9
R169
DNP
49.9
R171
49.9
R173
GND
GND
GND
GND
OUT0_A_P
OUT0_A_N
OUT2_A_P
OUT2_A_N
49.9
R168
49.9
R170
49.9
R172
49.9
R174
GND
GND
GND
GND
OUT1_A_P
OUT1_A_N
OUT3_A_P
OUT3_A_N
Figure 4-5. Clock Outputs OUT0 to OUT3
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4.6 Clock Outputs OUT4 to OUT9 Schematic
OUT4 to OUT9 CLOCK OUTPUTS
OUT4_P
OUT4_N
0.1uF
C105
0.1uF
C107
49.9
R96
DNP
49.9
R101
DNP
SMA_O5_P
SMA_O5_N
OUT5_P
OUT5_N
0.1uF
C106
0.1uF
C108
49.9
R103
DNP
49.9
R109
DNP
SMA_O6_P
SMA_O6_N
OUT6_P
OUT6_N
0.1uF
C109
0.1uF
C111
1
2
3 4 5
J17
OUT4_P
1
2
3 4 5
J19
OUT4_N
1
2
3 4 5
J18
OUT5_P
1
2
3 4 5
J20
OUT5_N
1
2
3 4 5
J21
OUT6_P
1
2
3 4 5
J23
OUT6_N
49.9
R105
DNP
49.9
R111
DNP
SMA_O7_P
SMA_O7_N
OUT7_P
OUT7_N
0.1uF
C110
0.1uF
C112
1
2
3 4 5
J22
OUT7_P
1
2
3 4 5
J24
OUT7_N
49.9
R113
DNP
49.9
R117
DNP
SMA_O8_P
SMA_O8_N
OUT8_P
OUT8_N
0.1uF
C113
0.1uF
C115
49.9
R115
DNP
49.9
R119
DNP
SMA_O9_P
SMA_O9_N
OUT9_P
OUT9_N
0.1uF
C114
0.1uF
C116
1
2
3 4 5
J25
OUT8_P
1
2
3 4 5
J27
OUT8_N
1
2
3 4 5
J26
OUT9_P
1
2
3 4 5
J28
OUT9_N
49.9
R94
DNP
49.9
R99
DNP
OUT4, Supported formats: LVDS, HSDS, and HCSL Source may be VCO2 or VCO3
OUT6, Supported formats: LVDS, HSDS, and HCSL Source may be VCO2 or VCO3
OUT8, Supported formats: LVDS, HSDS, and HCSL; Source may be VCO2 or VCO3
OUT5, Supported formats: LVDS, HSDS, and HCSL; Source may be VCO2 or VCO3
OUT7, Supported formats: LVDS, HSDS, and HCSL; Source may be VCO2 or VCO3
OUT9, Supported formats: LVDS, HSDS, and HCSL; Source may be VCO2 or VCO3
SMA_O4_P
SMA_O4_N
ClassName: OUT_LenMatch2a
ClassName: OUT_LenMatch2a
ClassName: OUT_LenMatch2a
ClassName: OUT_LenMatch2a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch2b ClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch2a ClassName: OUT_LenMatch2b ClassName: OUT_LenMatch2a ClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch2a ClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch2a ClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch2a ClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch2a ClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1bClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch2b
0
R91
0
R95
0
R98
0
R102
0
R106
0
R108
0
R107
0
R104
0
R100
0
R97
0
R93
0
R89
49.9
R176
DNP 49.9
R175
DNP
49.9
R177
DNP
49.9
R179
DNP 49.9
R178
DNP
49.9
R180
DNP
49.9
R182
DNP
49.9
R184
DNP
49.9
R181
DNP
49.9
R183
DNP
GND
GND
GND
GND
GND
GND
GND
GNDGND
GND
OUT4_A_P
OUT4_A_N
OUT6_A_P
OUT6_A_N
OUT8_A_P
OUT8_A_N
OUT5_A_P
OUT5_A_N
OUT7_A_P
OUT7_A_N
OUT9_A_P
OUT9_A_N
49.9
R204
DNP
GND
49.9
R205
DNP
GND
Figure 4-6. Clock Outputs OUT4 to OUT9
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4.7 Clock Outputs OUT10 to OUT15 Schematic
OUT10-OUT15 CLOCK OUTPUTS
49.9
R121
DNP
49.9
R125
DNP
SMA_O10_P
SMA_O10_N
OUT10_P
OUT10_N
0.1uF
C117
0.1uF
C119
1
2
3 4 5
J29
OUT10_P
1
2
3 4 5
J31
OUT10_N
49.9
R122
DNP
49.9
R127
DNP
SMA_O11_P
SMA_O11_N
OUT11_P
OUT11_N
0.1uF
C118
0.1uF
C120
1
2
3 4 5
J30
OUT11_P
1
2
3 4 5
J32
OUT11_N
49.9
R129
DNP
49.9
R133
DNP
SMA_O12_P
SMA_O12_N
OUT12_P
OUT12_N
0.1uF
C121
0.1uF
C123
49.9
R131
DNP
49.9
R135
DNP
SMA_O13_P
SMA_O13_N
OUT13_P
OUT13_N
0.1uF
C122
0.1uF
C124
1
2
3
4 5
J33
OUT12_P
1
2
3 4 5
J35
OUT12_N
1
2
3 4 5
J34
OUT13_P
1
2
3 4 5
J36
OUT13_N
49.9
R137
DNP
49.9
R140
DNP
0.1uF
C125
0.1uF
C127
49.9
R139
DNP
49.9
R142
DNP
SMA_OUT15_P
SMA_OUT15_N
0.1uF
C126
0.1uF
C128
FOR LMK5B33414, OUT15 is IN3
1
2
3 4 5
J37
IN2_P/OUT14_P
1
2
3 4 5
J39
IN2_N/OUT14_N
1
2
3 4 5
J38
IN3_P/OUT15_P
1
2
3 4 5
J40
IN3_N/OUT15_N
FOR LMK5B33414, OUT14 is IN2
OUT14_P
OUT14_N
OUT15_P
OUT15_N
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1aClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch2a ClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch2a ClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch2a ClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch2a ClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch1bClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1b ClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1bClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1b
SMA_OUT14_P
SMA_OUT14_N
0
R120
0
R116
0
R124
0
R110
0
R114
0
R118
0
R123
0
R126
0
R130
0
R112
49.9
R185
DNP
49.9
R187
DNP
49.9
R186
DNP
49.9
R188
DNP
49.9
R189
DNP
49.9
R191
DNP
49.9
R190
DNP
49.9
R134
DNP
49.9
R136
DNP
49.9
R141
DNP
49.9
R138
DNP
49.9
R143
DNP
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
OUT10_A_P
OUT10_A_N
OUT12_A_P
OUT12_A_N
OUT14_A_P
OUT14_A_N
OUT11_A_P
OUT11_A_N
OUT13_A_P
OUT13_A_N
100
R192
DNP
100
R193
DNP
Figure 4-7. Clock Outputs OUT10 to OUT15
EVM Schematics www.ti.com
20 LMK5B33216EVM User's Guide SNAU263A – FEBRUARY 2022 – REVISED JULY 2022
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