Texas Instruments TPS65033-Q1 Series User manual

User’s Guide
TPS650330-Q1 EVM User's Guide
ABSTRACT
The TPS650330-Q1 EVM is an evaluation board for the TPS65033x-Q1 Power Management Integrated Circuits
(PMICs). The EVM includes an onboard USB-to-I2C adapter, power terminals and jumpers for all DC regulator
inputs and outputs, and test points for common measurements.
Table of Contents
1 Introduction.............................................................................................................................................................................3
2 Requirements..........................................................................................................................................................................3
3 Operation Instructions........................................................................................................................................................... 3
4 EVM Configurations................................................................................................................................................................6
5 Test Points...............................................................................................................................................................................7
6 Graphical User Interface........................................................................................................................................................ 8
7 Typical Performance Plots................................................................................................................................................... 18
8 TPS650330-Q1 EVM Schematic........................................................................................................................................... 21
9 TPS650330-Q1 EVM PCB Layers.........................................................................................................................................23
10 TPS650330-Q1 EVM Bill of Materials................................................................................................................................ 29
11 TPS650330-Q1 Silicon Revision Changes........................................................................................................................ 32
12 Revision History................................................................................................................................................................. 33
List of Figures
Figure 4-1. TPS650330-Q1 EVM Top View................................................................................................................................. 6
Figure 5-1. TPS650330-Q1 EVM Test Point Locations............................................................................................................... 8
Figure 6-1. TPS650330-Q1 EVM Debugging Flow Chart............................................................................................................9
Figure 6-2. Opening Serial Port Options....................................................................................................................................10
Figure 6-3. Selecting an Alternate Port......................................................................................................................................10
Figure 6-4. TPS6503xx-Q1 GUI Home Screen..........................................................................................................................11
Figure 6-5. TPS6503xx-Q1 GUI Block Diagram Page...............................................................................................................12
Figure 6-6. Register Page Interfaces.........................................................................................................................................12
Figure 6-7. TPS6503xx-Q1 GUI Device Configuration Page.....................................................................................................13
Figure 6-8. Device Selection for Generating NVM Settings.......................................................................................................14
Figure 6-9. Example Settings Output.........................................................................................................................................14
Figure 6-10. Sequencing Overview Tab.....................................................................................................................................15
Figure 6-11. Sequencing Overview Including GPIO.................................................................................................................. 15
Figure 6-12. GUI Generated Timing Diagram............................................................................................................................16
Figure 6-13. TPS6503xx-Q1 GUI Re-Program PMIC Page...................................................................................................... 16
Figure 6-14. GUI Configuration CRC Script...............................................................................................................................17
Figure 7-1. TPS650330-Q1 Default Power Up Sequence......................................................................................................... 18
Figure 7-2. TPS650330-Q1 Default Power Down Sequence.................................................................................................... 18
Figure 8-1. TPS650330-Q1 Schematic......................................................................................................................................21
Figure 8-2. MSP432E401Y Schematic...................................................................................................................................... 22
Figure 9-1. Top Layer.................................................................................................................................................................23
Figure 9-2. Mid-Layer 1............................................................................................................................................................. 24
Figure 9-3. Mid-Layer 2............................................................................................................................................................. 25
Figure 9-4. Mid-Layer 3............................................................................................................................................................. 26
Figure 9-5. Mid-Layer 4............................................................................................................................................................. 27
Figure 9-6. Bottom Layer (Mirrored).......................................................................................................................................... 28
List of Tables
Table 3-1. Adapter Power Source (J18).......................................................................................................................................3
Table 3-2. Dedicated LDO Supply for Adapter (J19)................................................................................................................... 3
Table 3-3. Adapter PMIC Connections........................................................................................................................................ 4
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Table 3-4. Buck 1 Power Source (J33)........................................................................................................................................ 4
Table 3-5. Mid-Vin (Buck1) Features........................................................................................................................................... 4
Table 3-6. Mid-Vin (Buck1) Configurable Settings....................................................................................................................... 4
Table 3-7. Buck 2 Power Source (J15)........................................................................................................................................ 4
Table 3-8. Buck 3 Power Source (J16)........................................................................................................................................ 4
Table 3-9. Low-Vin (Buck2 and Buck3) Features.........................................................................................................................5
Table 3-10. Low-Vin (Buck2 and Buck3) Configurable Settings.................................................................................................. 5
Table 3-11. PMIC LDO Power Source (J8).................................................................................................................................. 5
Table 3-12. Low Noise LDO Features..........................................................................................................................................5
Table 3-13. Low Noise LDO Configurable Settings..................................................................................................................... 5
Table 3-14. VIO Power Source (J8)............................................................................................................................................. 6
Table 5-1. TPS650330-Q1 EVM Test Points................................................................................................................................7
Table 10-1. TPS650330-Q1 EVM Bill of Materials.....................................................................................................................29
Table 11-1. TPS65033x-Q1 Silicon Revision B0 Feature Changes........................................................................................... 32
Trademarks
Google Chrome™ is a trademark of Google, LLC.
Mozilla Firefox™ is a trademark of Mozilla Foundation.
Windows® is a registered trademark of Microsoft Corporation.
macOS® is a registered trademark of Apple Inc.
Linux® is a registered trademark of The Linux Foundation.
All other trademarks are the property of their respective owners.
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1 Introduction
The TPS650330-Q1 device is a highly integrated PMIC for automotive camera modules. This device combines
three step down converters and one low-dropout (LDO) regulator. The BUCK1 step-down converter has an input
voltage range up to 18.3 V for connections to power over coax. All converters operate in a forced fixed-
frequency PWM mode. The LDO can supply 300 mA and operate with an input voltage range from 2.2 V to 5.5
V. The step-down converters and the LDO have separate voltage inputs that enable maximum design and
sequencing flexibility.
2 Requirements
• Computer with Windows, MacOS, or Linux operating system
• Camera PMIC GUI (Link Here)
• Micro-USB Cable
• TPS650330-Q1 EVM
• DC Power Supply (4.5 V to 19 V)
– Banana Cables for Power and GND
3 Operation Instructions
1. Ensure USB to I2C Adapter is configured properly using the jumpers mentioned in Configuring the USB to I2C
Adapter. For most applications, this will be the default configurations defined in the tables.
2. Configure regulator input supply rails for the expected application using the jumpers mentioned in Regulator
Input Supplies and Features. Take extra care not to exceed absolute maximum ratings when VSYS supplies
BUCK2, BUCK3, or the LDO.
3. Connect Micro-USB to a PC capable of loading the Camera PMIC GUI.
4. Connect VSYS to a power supply capable of supporting the application and enable the supply. Typical supply
voltage is 12 V. The PMIC will boot automatically as VSYS is applied.
5. Set the SEQ switch (S1) to ON to enable the Buck 1 and Buck 2 regulators.
6. Set GPIO switch (S4) to ON to enable the Buck 3 and LDO regulators.
7. Load the Camera PMIC GUI and ensure the adapter has been recognized by the PC. If the GUI says
Hardware not connected, refer to TPS650330-Q1 EVM Debugging.
8. Step 6: Once the adapter is connected, the GUI will attempt to read all registers and update the register map.
3.1 Configuring the USB to I2C Adapter
An onboard MCU acts as a USB adapter to the PMIC. This adapter allows I2C communication to the host PC as
well as GPIO assertion and monitoring. By default, the onboard adapter is powered by the USB cable through an
onboard dedicated 3.3 V LDO (U4). Additional configurations are allowed by reconfiguring jumpers J18 and J19,
shown in Table 3-1 and Table 3-2. The onboard adapter must have power applied through a valid configuration.
Table 3-1. Adapter Power Source (J18)
Selection Jumper Pin Adapter Supply Bus
Pin 1 (PMIC Buck 1 Output) Pin 2 (Adapter Input Supply Rail)
Pin 3 (PMIC LDO Output) Pin 4 (Adapter Input Supply Rail)
Pin 5 (Dedicated 3.3 V LDO Output - Default) Pin 6 (Adapter Input Supply Rail)
Table 3-2. Dedicated LDO Supply for Adapter (J19)
Selection Jumper Pin Dedicated 3.3V LDO Supply Bus
Pin 1 (PMIC Buck 1 Output) Pin 2 (Dedicated 3.3 V LDO Input Rail)
Pin 3 (PMIC Buck 1 Input - Default) Pin 4 (Dedicated 3.3 V LDO Input Rail)
Pin 5 (VBUS Rail) Pin 6 (Dedicated 3.3 V LDO Input Rail)
The following Jumpers in Table 3-3 connect the USB adapter to PMIC functional pins. These can be
disconnected for flexibility.
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Table 3-3. Adapter PMIC Connections
Jumper PMIC Pin
J21 nRST
J22 SEQ
3.2 Regulator Input Supplies and Features
The four regulators on the TPS650330-Q1 EVM can be supplied with multiple supplies. The following tables
show the possible supply configurations in addition to key specifications and programmable features for each
regulator.
3.2.1 Buck 1 Input Supply
Table 3-4. Buck 1 Power Source (J33)
Selection Jumper Pin Buck1 Supply Bus
Pin 1 (VSYS - Default) Pin 2 (Buck 1 Input Supply Rail)
3.2.2 Mid-Vin Buck1 Features
Table 3-5. Mid-Vin (Buck1) Features
Feature Specification
Input Voltage Range 4 V to 18.3 V
Operating Current Maximum of 1.5 A
Current Limiting 1.8 A to 3.6 A
Status Monitoring UVLO, UV, HOT, OVP, SCG, OCP
Over-Voltage Protection (OVP) VOUT = 109% to 115%
Short-Circuit Threshold (SCG) VOUT = 250 mV to 350 mV
Table 3-6. Mid-Vin (Buck1) Configurable Settings
Feature Configurable Range
Output Voltage 2.5 V to 4.0 V
PVIN_B1 UVLO Rising 3.64 V to 9.36 V
PVIN_B1 UVLO Falling 3.5 V to 9 V
Output Discharge Disabled, 125 Ω, 250 Ω, and 500 Ω
Sequencing Enable, Dependencies, and Fault RST
Sequence Delay (Off and On) 0 ms to 20 ms
Note: Over-voltage monitor settings are available for the TPS650331-Q1, TPS650332-Q1, and TPS650333-Q1.
3.2.3 Buck 2 Input Supply
Table 3-7. Buck 2 Power Source (J15)
Selection Jumper Pin Buck2 Supply Bus
Pin 1 (VSYS) Pin 2 (Buck 2 Input Supply Rail)
Pin 3 (Buck1 Output Rail - Default) Pin 4 (Buck 2 Input Supply Rail)
3.2.4 Buck 3 Input Supply
Table 3-8. Buck 3 Power Source (J16)
Selection Jumper Pin Buck3 Supply Bus
Pin 1 (VSYS) Pin 2 (Buck 3 Input Supply Rail)
Pin 3 (Buck1 Output Rail - Default) Pin 4 (Buck 3 Input Supply Rail)
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3.2.5 Low-Vin Buck2 and Buck3 Features
Table 3-9. Low-Vin (Buck2 and Buck3) Features
Feature Specification
Input Voltage Range 2.5 V to 5.5 V
Operating Current Maximum of 1.2 A
Current Limiting 1.6 A to 2.8 A
Status Monitoring UV, HOT, OVP, SCG, OCP
Over-Voltage Protection (OVP) VOUT = 109% to 115%
Short-Circuit Threshold (SCG) VOUT = 250 mV to 350 mV
Table 3-10. Low-Vin (Buck2 and Buck3) Configurable Settings
Feature Configurable Range
Output Voltage 0.9 V to 1.9 V
Under-Voltage Flags (UV) VOUT = 94.5%, 95%, 95.5%, and 96%
Spread Spectrum Enable or Disable
Sequencing Enable, Dependencies, and Fault RST
Sequence Delay (Off and On) 0 ms to 20 ms
Note: Over-voltage monitor settings are available for the TPS650331-Q1, TPS650332-Q1, and TPS650333-Q1.
3.2.6 LDO Input Supply
Table 3-11. PMIC LDO Power Source (J8)
Selection Jumper Pin PMIC LDO Supply Bus
Pin 1 (VSYS) Pin 2 (PMIC LDO Input Supply Rail)
Pin 3 (Buck1 Output Rail - Default) Pin 4 (PMIC LDO Input Supply Rail)
Pin 5 (Buck2 Output Rail) Pin 6 (PMIC LDO Input Supply Rail)
Pin 7 (Buck3 Output Rail) Pin 8 (PMIC LDO Input Supply Rail)
3.2.7 Low Noise LDO Features
Table 3-12. Low Noise LDO Features
Feature Specification
Input Voltage Range 2.5 V to 5.5 V
Operating Current Maximum of 150 mA or 300 mA
Current Limiting Minimum of 200 mA or 400 mA
Status Monitoring UV, HOT, OVP, SCG, OCP
Over-Voltage Protection (OVP) VOUT = 109% to 115%
Short-Circuit Threshold (SCG) VOUT = 250 mV to 350 mV
Table 3-13. Low Noise LDO Configurable Settings
Feature Configurable Range
Output Voltage 1.8 V, or 2.7 V to 3.3 V
Under-Voltage Flags (UV) VOUT = 94.5%, 95%, 95.5%, and 96%
Load Switch Mode Enable or Disable
Current Limit 200 mA, 400 mA
Sequencing Enable, Dependencies, and Fault RST
Sequence Delay (Off and On) 0 ms to 20 ms
Note: Over-voltage flag settings are available for the TPS650331-Q1, TPS650332-Q1, and TPS650333-Q1.
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3.3 Selecting the Logic Supply Voltage
Table 3-14. VIO Power Source (J8)
Selection Jumper Pin VIO Supply Bus
Pin 1 (Buck1 Output Rail - Default) Pin 2 (VIO Input Supply Rail)
Pin 3 (Buck2 Output Rail) Pin 4 (VIO Input Supply Rail)
Pin 5 (Buck3 Output Rail) Pin 6 (VIO Input Supply Rail)
Pin 7 (PMIC LDO Output Rail) Pin 8 (VIO Input Supply Rail)
Pin 9 (Dedicated 3.3 V LDO) Pin 10 (VIO Input Supply Rail)
4 EVM Configurations
The following sections outline how to configure the TPS650330-Q1 EVM for general experimentation.
Figure 4-1. TPS650330-Q1 EVM Top View
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5 Test Points
5.1 Voltage Test Points
The TPS650330-Q1 EVM contains 30 test points for various measurements. Trace assignments to the test
points are shown in Table 5-1. For reference, Figure 5-1 demonstrates the test point locations on the EVM.
Table 5-1. TPS650330-Q1 EVM Test Points
Test Point Number Associated Trace
TP1 SCL
TP2 VREG
TP3 GPIO
TP4 Buck 1 Output
TP5 VBUS
TP6 SDA
TP7 V1P8_INT
TP8 nINT
TP9 PMIC LDO Input
TP10 SEQ
TP11 nRSTOUT
TP12 Buck 2 Output
TP13 Buck 2 Input
TP14 VIO
TP15 Buck 3 Output
TP16 Buck 3 Input
TP17 PMIC LDO Output
TP18 Buck 1 Input
TP19 GND
TP20 GND
TP21 USBD_N
TP22 GND
TP23 GND
TP24 VSYS
TP25 GND
TP26 GND
TP27 GND
TP28 GND
TP29 USBD_P
TP30 GND
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Figure 5-1. TPS650330-Q1 EVM Test Point Locations
6 Graphical User Interface
The Graphical User Interface (GUI) for the EVM can be found in the Gallery at TI DevTools. The GUI can be
operated through Google Chrome™ or Mozilla Firefox™ web browsers. To run the GUI in the browser, click the
thumbnail and follow the prompted instructions for first time installation. The GUI requires both a browser plugin
and the TI Cloud Agent software for access to the local USB ports. The GUI can also be downloaded for offline
operation by hovering over the downward arrow in the GUI thumbnail and selecting the desired platform –
Windows®, macOS®, or Linux®.
6.1 TPS650330-Q1 EVM Debugging
Refer to Figure 6-1 to debug potential issues while using the TPS650330-Q1 EVM.
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Figure 6-1. TPS650330-Q1 EVM Debugging Flow Chart
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6.1.1 I2C Communication Port and Adapter Debugging
By default, the GUI will recognize two serial ports from the EVM adapter, but may not select the I2C bridge
automatically. Once the EVM is powered and the USB cable is connected to the computer, click the connect icon
at the bottom left of the GUI. If the bottom notification updates to Hardware Not Selected:
1. Click the Options menu at the top of the GUI, select Serial Port.
Figure 6-2. Opening Serial Port Options
2. Use the Ports dropdown to select the alternative interface.
Figure 6-3. Selecting an Alternate Port
After clicking OK, the GUI should connect to the device properly. If communication to the EVM is lost, most
issues can be resolved by pressing the nRST_MCU button (S3) on the EVM. Afterwards, further issues can be
diagnosed by confirming that MCU_IN (J18) is still present, and that the I2C pull-up domain is still active.
6.1.2 Updating MCU Firmware
If the EVM on-board MCU is showing up under the Device Manager with a Stellaris... title, the MCU firmware
needs to be updated to communicate with the GUI. One way to do this is with TI's free LM Flash Programmer
tool. Once the firmware is updated, the MCU should show up as ACCtrl... COM ports in the Device Manager.
1. Download the GUI source files from the Gallery. The EVM firmware is the .bin file located in the
install_image_TPS6503xx-Q1_GUI/TPS6503xx-Q1_GUI/app/firmware folder.
2. Open LM Flash Programmer with the EVM connected through USB.
3. Select USB DFU in the Configuration tab. The Stellaris device should show in the device list box after
refreshing.
4. Select the Program tab.
5. Browse to the .bin file downloaded from the GUI.
6. Leave all other settings as default.
7. Click Program.
6.2 Navigating the GUI
The GUI contains the following five sections, selectable on the left side of the GUI or by clicking the Menu tab in
the top left corner.
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• Home
• Block Diagram
• Registers
• Device Configuration
• Re-Program PMIC
6.2.1 Home
The Home section is the landing page of the GUI. Here the GUI presents an overview of the EVM and
Programming BoosterPack (BOOSTXL-TPS65033), and emphasize navigation to the remaining four sections
through the tiles on the bottom of the page.
Figure 6-4. TPS6503xx-Q1 GUI Home Screen
6.2.2 Block Diagram
The Block Diagram section displays the typical components and functional blocks of the PMIC. A block diagram
for the Programming BoosterPack is also shown.
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Figure 6-5. TPS6503xx-Q1 GUI Block Diagram Page
6.2.3 Registers
The Registers section provides an overview of the internal register map, and includes basic interfaces for each
PMIC register. Figure 6-6 illustrates the register page and the primary interactive regions.
Manually
enter hex
value
(Optional)
Select
autoread
interval
Read
selected
register
Read all
registers
Select I2C
Write
Behavior
Register
Field
Information
Register
Information
Select
register field
value
Figure 6-6. Register Page Interfaces
The register table displays each register name, address, last known value from the PMIC, and corresponding bit
values. Selecting a title or bit fields in the table will update the Field View column on the right side of the GUI.
The Field View displays the individual fields contained within the associated register address. Within the register
page, clicking a blue icon containing a question mark (?) will expand additional descriptions if available. The
expanded description views can then be closed by clicking the red (x) icon.
This register page can poll the device periodically using the Auto Read feature in the top right corner, or allow
manual read instructions using the Read Register and Read All Registers buttons.
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A drop-down menu selection at the top right of the register map indicates how the registers are written as the
user interacts with the register page. With Immediate selected, any update to the register page is automatically
sent to the PMIC, whereas Deferred will wait for the Write Register or Write All Registers instructions before
communicating with the device. After each write, the register page will automatically read the affected register
address to confirm the latest value in the device.
6.2.4 Device Configuration
The Device Configuration section is organized into selectable tabs at the top of the page, where only the
contents of the blue tab is actively displayed. Each tab contains categorized visual instruments relating to
individual bit fields within the register map. Each instrument is linked to the latest bit values in the register map
table, and can be used to alter settings within the PMIC through the dropdown menus or check box features. If
the Auto Read function in the register map is inactive, the Read All Registers button in the top right area of the
Device Configuration page can be used to manually refresh the register page, which will then update the
instruments with the latest device values.
The PMIC incorporates Control Lock and Configuration Lock features that can prevent I2C writes to various
registers within the device. The status of these locks will always be displayed in the top right hand corner of the
Device Configurations page, and can be toggled by clicking their associated checkbox. When the GUI is properly
connected to the EVM and write instructions appear to be ignored by the PMIC, confirm the status of these
indicators to verify the device is able to accept new write instructions.
Figure 6-7. TPS6503xx-Q1 GUI Device Configuration Page
6.2.4.1 Using Device Configuration to Define Spin Settings
In some circumstances, TI may provide customized, pre-programmed devices for the camera application.
Contact a local TI sales representative for more information.
The Device Configuration tabs in the GUI can be used to define custom settings for TI to pre-program into the
device Non-Volatile Memory (NVM). Before beginning the spin definition, see the Camera PMIC Spin Selection
Guide to determine if there is an exisiting spin that is already compatible with the target application and the
image sensor or both.
Since the visual instruments in the Device Configuration page link directly to the corresponding bits and registers
in the Register Map page, the Device Configuration page can be used to quickly define desired OTP register
settings.
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1. Select the desired camera PMIC from the drop-down menu above the tab indicators to start. The GUI will
automatically show, hide, or disable features corresponding to the selected PMIC. This drop down box will not
be adjustable if a device is connected to the GUI.
Figure 6-8. Device Selection for Generating NVM Settings
2. Select the desired regulator, sequencing, and additional feature settings in each of the tabs. These changes
will be reflected in the Register Map page. For determining the power sequence settings, see Section 6.2.4.2.
3. Click File > Save Settings in the top left corner of the GUI. This exports the register settings in a JSON file
that is provided to generate the NVM spin.
Figure 6-9. Example Settings Output
6.2.4.2 Configuring the Power Sequence
The Sequencing Overview tab includes instruments to customize the power sequence of the PMIC. Note that the
check boxes are power sequence masks. If a particular logic signal needs to be included as part of the regulator
or logic power up sequence, leave the box next to the logic signal unchecked. TI recommends to set Power On
Bit unmasked for each rail that is required in the application.
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Figure 6-10. Sequencing Overview Tab
When using a TPS65033x-Q1 device, the GPIO pin can also be used for power sequencing of an external
regulator or other device. In the Special Features tab, configure GPIO as an output to include its sequencing in
the Sequencing Overview tab. Note that when using GPIO for sequencing, the GPIO Function must be Enabled.
Figure 6-11. Sequencing Overview Including GPIO
For reference, the GUI can generate example power-up and power-down timing diagrams based on the
sequence settings present when the UPDATE TIMING DIAGRAM button is clicked. As noted, rise and fall times
are approximate, and the maximum sequence length is 200 ms. Changes to regulator enable and output
discharge settings are reflected in the timing diagram. If the sequence settings are not valid, the GUI will provide
a notifying message and the timing diagram will not be updated. For example, if a regulator is enabled but fails
to power-up within 200 ms, the sequence settings are not valid.
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Figure 6-12. GUI Generated Timing Diagram
6.2.5 Re-Program PMIC
The Re-Program PMIC section contains a button for sending the EEPROM Program Command to the device.
After the EEPROM Program Command is sent, the device will store the existing register configurations
permanently and the PMIC will automatically restart with the latest settings. The device can be re-programmed
multiple times to evaluate various configurations.
Figure 6-13. TPS6503xx-Q1 GUI Re-Program PMIC Page
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6.3 In-Circuit Programming
The TPS650330-Q1 EVM demonstrates the in-circuit programming capabilities of the TPS650330-Q1 PMIC in a
typical application. This section provides an example in-circuit programming procedure with application
considerations.
1. Verify the desired power and sequence settings using the GUI's Sequencing Overview tools. See Configuring
the Power Sequence.
2. Validate the settings with the BOOSTXL-TPS65033. This socketed board provides a quicker way to evaluate
device settings.
3. Once settings are verified and validated, configure the TPS650330-Q1 EVM for a typical camera application:
a. Ensure the I2C pull-up jumpers (J24 and J34) are populated.
b. Supply the PMIC VIO with either the Buck 1 or Buck 2 output. See Selecting the Logic Supply Voltage.
c. Tie the PMIC Buck 1 input to VSYS. See Buck 1 Input Supply.
d. Supply the PMIC Buck 2, Buck 3, and LDO with the Buck 1 output. See Selecting Regulator Input
Supplies.
4. Assert SEQ (S1) before applying power.
5. Apply a Buck 1 input voltage (typical is 12 V) to power up the device. By default, the Buck 1 and Buck 2
regulators are enabled, allowing the 3.3 V and 1.8 V rails to power up.
a. In a typical camera application, this may be sufficient to power up the serializer and enable PMIC
programming over the Serializer-Deserializer (SerDes) back-channel.
b. If additional rails are required, assert GPIO (S4) to enable the Buck 3 and LDO regulators.
6. Unlock the configuration and control registers.
7. Re-program the PMIC settings. If changing a regulator output voltage, TI recommends disabling the regulator
first. If doing this in an application setting shuts down a critical component, change the output voltage in small
steps to prevent triggering under or over-voltage fault handling.
8. If the device configuration Cyclic Redundancy Check (CRC) is enabled, calculate and write the new
configuration CRC by running the GUI's built-in script. For more information on the GUI's capabilities for
programming automation, see the BOOSTXL-TPS65033 User's Guide.
Figure 6-14. GUI Configuration CRC Script
9. Burn the final PMIC register settings to EEPROM.
10.Validate the settings on subsequent startups.
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7 Typical Performance Plots
7.1 Power Sequence Plots
Figure 7-1. TPS650330-Q1 Default Power Up Sequence Figure 7-2. TPS650330-Q1 Default Power Down Sequence
7.2 Load Transient Plots
VIN = 12 V VOUT = 3.3 V IOUT = 1 mA to 750 mA in 1 µs
Figure 7-3. Buck 1 Load Transient
VIN = 3.3 V VOUT = 1.8 V IOUT = 1 mA to 300 mA in 1 µs
Figure 7-4. Buck 2 Load Transient
VIN = 3.3 V VOUT = 1.2 V IOUT = 1 mA to 300 mA in 1 µs
Figure 7-5. Buck 3 Load Transient
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18 TPS650330-Q1 EVM User's Guide SLVUBI2A – JULY 2018 – REVISED OCTOBER 2020
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7.3 Output Voltage Ripple Plots
VIN = 12 V VOUT = 3.3 V IOUT = 750 mA
Figure 7-6. Buck 1 Output Voltage Ripple
VIN =3.3 V VOUT = 1.8 V IOUT = 600 mA
Figure 7-7. Buck 2 Output Voltage Ripple
VIN = 3.3 V VOUT = 1.2 V IOUT = 600 mA
Figure 7-8. Buck 3 Output Voltage Ripple
7.4 Efficiency Plots
VIN = 9 V VOUT = 3.3 V Ta = 25°C
Figure 7-9. Buck 1 Efficiency Curve
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TPS650330-Q1 EVM User's Guide 19
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7.4 Efficiency Plots
VIN = 3.3 V VOUT = 1.8 V Ta = 25°C
Figure 7-10. Buck 2 Efficiency Curve
VIN = 3.3 V VOUT = 1.2 V Ta = 25°C
Figure 7-11. Buck 3 Efficiency Curve
7.5 LDO Output Noise
VIN = 3.3 V VOUT = 2.8 V IOUT = 300 mA
Figure 7-12. LDO Output Noise Density
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20 TPS650330-Q1 EVM User's Guide SLVUBI2A – JULY 2018 – REVISED OCTOBER 2020
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