Texas Instruments TPS65053EVM-389 User manual

1 Introduction
User's GuideSLVU262 – February 2009
TPS65053EVM-389
Contents1 Introduction ................................................................................................................... 12 Setup .......................................................................................................................... 23 Board Layout ................................................................................................................. 64 Schematic and Bill of Materials ............................................................................................ 8
List of Figures
1................................................................................................................................. 52 Assembly Layer .............................................................................................................. 63 Top Layer Routing ........................................................................................................... 74 Bottom Layer Routing ....................................................................................................... 85 TPS65053EVM-389 Schematic ............................................................................................ 9
List of Tables
1 EVM Preset Output Voltage ................................................................................................ 42 Maximum Load Current ..................................................................................................... 43 Factory EVM Jumper Settings ............................................................................................. 54 TPS65053EVM-389 Bill of Materials ..................................................................................... 10
The Texas Instruments TPS65053EVM-389 evaluation module (EVM) enables designers to evaluate theoperation and performance of the TPS65053 Power Management Integrate Circuit (PMIC) for applicationsthat require multiple power rails and are powered from a single Lithium Ion or Lithium Polymer cell. TheTPS65053 contains two efficient step-down switching converters, three low dropout (LDO) linearregulators and a voltage monitor RESET output.
The TPS65053EVM-389 is setup according to the power requirements of the Freescale™ i.MX27processor.
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2 Setup
2.1 Input/Output Connector Descriptions
Setup www.ti.com
This chapter describes the jumpers and connectors on the EVM, as well as how to properly connect,setup, and use the TPS65053EVM-389.
J1 - VLDO1
This header is the positive output of LDO1 linear regulator. This output is externally adjustable for theTPS65053 and is programmed to a value of 1.8 V on the EVM. The VLDO1 output is capable of supplyingup to 400-mA. A load can be connected between J1 and J2 (GND). Applications using Freescale™i.MX27 can utilize J1-VLDO1 to power the NVDD_DDR, analog, and FUSEVDD rails of the i.MX27processor.
J2 - GND
J2 is the return connection of VLDO1 output rail. A load can be connected between J2 and J1 (VLDO1).
J3 - VLDO2
This header is the positive output of LDO2 linear regulator. This output is externally adjustable for theTPS65053 and is programmed to a value of 1.4 V on the EVM. The VLDO2 output is capable of supplyingup to 200 mA. A load can be connected between J3 and J4 (GND). Applications using Freescale™ i.MX27can utilize J3-VLDO2 to power the RTCVDD and OSC32VDD rails of the i.MX27 processor.
J4 - GND
J4 is the return connection of VLDO2 output rail. A load can be connected between J4 and J3 (VLDO2).
J5 - VLDO3
This header is the positive output of LDO3 linear regulator. This output is fixed at 1.3 V for the TPS65053.The VLDO3 output is capable of supplying up to 200-mA. A load can be connected between J5 and J6(GND).
J6 - GND
J6 is the return connection of VLDO3 output rail. A load can be connected between J6 and J5 (VLDO3).
J7 - RESET
This header allows the user to monitor the RESET output. The RESET output goes high 100-ms after theTHRESHOLD input exceeds 1.0-V. RESET goes low when the THRESHOLD input falls below 1.0-V. Onthe EVM, the RESET circuitry monitors the outputs VOUT DCDC1 and VOUT DCDC2.
J8 - VOUT DCDC1
This header is the positive output of VDCDC1 step-down converter. This output is externally adjustable forthe TPS65053 and is programmed to a value of 2.7-V on the EVM. VDCDC1 is capable of sourcing up to1.0-A. A load can be connected between J8 and J9 (GND). Applications using Freescale™ i.MX27 canutilize J8-VOUT DCDC1 to power NVDD_FAST, NVDD_SLOW, and OSC26VDD of the i.MX27 processor.
J9 - GND
J9 is the return connection of VOUT VDCDC1 output rail. A load can be connected between J9 and J8(VOUT DCDC1).
J10 - VIN
This header is the positive connection to the input power supply. The power supply must be connectedbetween J10 and J11 (GND). The leads to the input supply should be twisted and kept as short aspossible. The input voltage has to be between 2.5-V and 6-V.
J11 - GND
This header is the return connection to the input power supply. Connect the power supply between J11and J10 (VIN). The leads to the input supply should be twisted and kept as short as possible. The inputvoltage has to be between 2.5-V and 6-V.
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www.ti.com J12 - VOUT DCDC2
J12 - VOUT DCDC2
This header is the positive output of VDCDC2 step-down converter. This output is externally adjustable forthe TPS65053 and is programmed to a value of 1.8-V on the EVM. VDCDC2 is capable of sourcing up to600-mA. A load can be connected between J12 and J13 (GND). Applications using Freescale™ i.MX27can can utilize J12-VOUT DCDC2 to power the QVDD rail of the i.MX27 processor.
J13 - GND
J13 is the return connection of VOUT VDCDC2 output rail. A load can be connected between J13 and J12(VOUT DCDC2).
JP1 - VIN_LDO1
JP1 selects the input voltage source for LDO1.
Place a shorting bar in the VOUT_DCDC1 position to select the output of VDCDC1 converter as inputvoltage source for LDO1.
Place a shorting bar in the VIN position to select the input voltage as input source for LDO1.
JP2 - VIN_LDO2/3
JP2 selects the input voltage source for LDO2 and LDO3.
Place a shorting bar in the VOUT_DCDC1 position to select the output of VDCDC1 converter as inputvoltage source for LDO2 and LDO3.
Place a shorting bar in the VIN position to select the input voltage as input source for LDO2 and LDO3.
JP3 - EN_LDO1
Placing a shorting bar between EN LDO1 and ON ties the EN pin of LDO1 to VIN, thereby enabling LDO1.Placing a shorting bar between EN LDO1 and OFF ties the EN pin of LDO1 to GND, thereby disablingLDO1.
JP4 - EN_DCDC2
Placing a shorting bar between EN_DCDC2 and ON ties the EN pin of DCDC2 to VIN, thereby enablingDCDC2. Placing a shorting bar between EN_DCDC2 and OFF ties the EN pin of DCDC2 to GND, therebydisabling DCDC2.
JP5 - EN_DCDC1
Placing a shorting bar between EN_DCDC1 and ON ties the EN pin of DCDC1 to VIN, thereby enablingDCDC1. Placing a shorting bar between EN_DCDC1 and OFF ties the EN pin of DCDC1 to GND, therebydisabling DCDC1.
JP6 - MODE InputJP6 selects the forced PWM or Power Save Mode (PSM) operation for the switching converters DCDC1and DCDC2.
Placing a shorting bar between MODE and PWM ties the MODE pin of TPS65053 to VIN, therebyselecting forced PWM operating mode for the DCDC converters. Placing a shorting bar between MODEand PSM (Power Save Mode) ties the MODE pin of TPS65053 to GND, thereby selecting Power SaveMode operating mode for the DCDC converters at light-load conditions. If Power Save Mode is selectedthe DCDC converters will automatically switch to PWM mode at havier load conditions.
JP7 - EN_LDO2
Placing a shorting bar between EN LDO2 and ON ties the EN pin of LDO2 to VIN, thereby enabling LDO2.Placing a shorting bar between EN LDO2 and OFF ties the EN pin of LDO2 to GND, thereby disablingLDO2.
JP8 - EN_LDO3
Placing a shorting bar between EN LDO3 and ON ties the EN pin of LDO3 to VIN, thereby enabling LDO3.Placing a shorting bar between EN LDO3 and OFF ties the EN pin of LDO3 to GND, thereby disablingLDO3.
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2.2 EVM Setup
2.2.1 EVM Factory Configuration
2.3 Power Up Sequence
JP8 - EN_LDO3 www.ti.com
The EVM is configured to provide the following nominal operating conditions:•Input Voltage: 2.5-V to 6.0-V•Output Voltage: See Table 1•Maximum Load Current: See Table 2
Table 1. EVM Preset Output Voltage
Preset Output
TPS65053EVMVoltage
VDCDC1 2.7 VVDCDC2 1.4 VVLD01 1.8 VVLD02 1.4 VVLD03 1.3 V
Table 2. Maximum Load Current
Maximum Load
TPS65053EVMCurrent
VDCDC1 1 AVDCDC2 600 mAVLD01 400 mAVLD02 200 mAVLD03 200 mA
The TPS65053EVM-389 is set up to meet the Power Up requirements of the Freescale™ i.MX27processor.
The step down converters DCDC1 and DCDC2 start up first, followed by the low drop out (LDO)regulators LDO1, LDO2 and LDO3 as shown in Figure 1 .
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DCDC1 2V/div
DCDC2 1V/div
LDO1 1V/div
LDO2 1V/div
200 s/divμ
2.4 Operation
www.ti.com JP8 - EN_LDO3
Figure 1.
1. Configure all EVM jumpers to factory settings shown in Table 3 .2. Connect the input voltage return to J11.3. Connect the positive input voltage to J10.4. Connect all loads to the outputs.5. Turn on input voltage.
Table 3. Factory EVM Jumper Settings
Shunt LocationJumper
TPS65053EVM
JP1 Between VOUT_DCDC1 and VIN_LDO1JP2 Between VOUT_DCDC1 and VIN_LDO2JP3 Between ON and EN_LDO1JP4 Between ON and EN_DCDC2JP5 Between ON and EN_DCDC1JP6 Between PWM and MODEJP7 Between ON and EN_LDO2JP8 Between ON and EN_LDO3
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3 Board Layout
3.1 Layout
EXAS
T
INSTRUMENTS
Board Layout www.ti.com
This chapter provides the TPS65053EVM-389 board layout and illustrations.
Figure 2 and Figure 3 show the board layout for the TPS65053EVM-389 PWB.
Figure 2. Assembly Layer
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www.ti.com Board Layout
Figure 3. Top Layer Routing
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4 Schematic and Bill of Materials
Schematic and Bill of Materials www.ti.com
Figure 4. Bottom Layer Routing
This chapter provides the TPS65053EVM-389 schematic and bill of materials.
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4.1 Schematic
www.ti.com Schematic and Bill of Materials
Figure 5. TPS65053EVM-389 Schematic
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4.2 Bill of MaterialsRelated Documentation From Texas Instruments
www.ti.com
Table 4. TPS65053EVM-389 Bill of Materials
Count RefDes Value Description Size Part Number MFR
C1, C2, C3, C4, C5, Capacitor, Ceramic, 10V, X5R,6 10uF 0805 GRM21BR61A106KE19L muRataC6 10%2 C11, C14 33pF Capacitor, Ceramic, 50V, C0G, 5% 0603 C1608C0G1H330J TDKCapacitor, Ceramic, 6.3V, X5R,1 C15 3.3nF 0805 Std Std10%
Capacitor, Ceramic, 6.3V, X5R,1 C7 4.7uF 0603 GRM188R60J475ME19D muRata20%
Capacitor, Ceramic, 10V, X5R,4 C8, C10, C12, C13 2.2uF 0603 GRM188R61A225KE34D muRata10%
Capacitor, Ceramic, 16V, X7R,1 C9 1uF 0603 C1608X7R1C105K TDK10%J1, J2, J3, J4, J5,
Header, Male 2-pin, 100mil 0.100 inch12 J6, J8, J9, J10, J11, Anyspacing x 2J12, J13
0.100 inch1 J7 Header, 2-pin, 100mil spacing Anyx 2JP1, JP2, JP3, JP4, 0.100 inch8 Header, 3-pin, 100mil spacing AnyJP5, JP6, JP7, JP8 x 30.118 x2 L1**, L2** 2.2uH Inductor, SMT,1.5A, 110milliohm LPS3015-222ML Coilcraft0.118 inch1 R1 562k ΩResistor, Chip, 1/10W, 1% 0805 Std Std1 R11 510k ΩResistor, Chip, 1/10W, 1% 0805 Std Std0 R13 open Resistor, Chip, 1/10W, 1% 0805 Std Std1 R14 1R Resistor, Chip, 1/10W, 1% 0805 Std Std2 R2, R3 160k ΩResistor, Chip, 1/10W, 1% 0805 Std Std2 R4, R7 120k ΩResistor, Chip, 1/10W, 1% 0805 Std Std1 R5 240k ΩResistor, Chip, 1/10W, 1% 0805 Std Std3 R6, R8, R10 300k ΩResistor, Chip, 1/10W, 1% 0805 Std Std3 R9, R12, R15 100k ΩResistor, Chip, 1/10W, 1% 0805 Std StdIC, 2.25 MHz Dual Step-downTPS6501 U1** Converter With 3 Low Input QFN24 TPS65053RGE TI53RGE
Voltage LDOs1 -- PCB, 3.4 In x 2.8 In x 0.062 In HPA389 Any8 -- Shunt, 100-mil, Black 0.100 Any
Related Documentation From Texas InstrumentsTPS65053 data sheet (SLVS754)
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