Texas Instruments TPS71401DRVEVM-426 User manual

1 Overview
1.1 Related Documentation from Texas Instruments
User's GuideSBVU013 – January 2009
TPS71401DRVEVM-426
This user's guide describes the characteristics, operation, and use of the TPS71401DRVEVM-426evaluation module. This document includes setup instructions, a schematic diagram, thermal guidelines, abill of materials (BOM), and printed circuit board (PCB) layout drawings.
Contents1 Overview ...................................................................................................................... 12 Setup .......................................................................................................................... 23 Operation ..................................................................................................................... 34 Thermal Guidelines .......................................................................................................... 35 Board Layout, Schematic, and Parts List ................................................................................. 4
List of Figures
1 Assembly Layer .............................................................................................................. 52 Top Layer Routing ........................................................................................................... 63 Bottom Layer Assembly ..................................................................................................... 74 Bottom Layer Routing ....................................................................................................... 85 TPS71401DRVEVM-426 Schematic ...................................................................................... 9
This document describes the characteristics, operation, and use of the TPS71401DRVEVM-426evaluation module (EVM). This EVM demonstrates the capabilities and features of Texas Instruments'TPS71401 , a low-dropout (LDO) linear regulator, an 80-mA, low quiescent current linear regulator in a2-mm x 2-mm SON package. The TPS71401DRVEVM-426 EVM helps designers evaluate the operationand performance of the TPS71401 LDO in a variety of configurations.
The following related documents are available through the Texas Instruments web site athttp://www.ti.com .
Table 1. Related Documentation
Part Number Literature Number
TPS71401 SBVS116
All trademarks are the property of their respective owners.
SBVU013 – January 2009 TPS71401DRVEVM-426 1Submit Documentation Feedback

2 Setup
2.1 Electrostatic Discharge Notice
2.2 Input/Output Connector Descriptions
2.2.1 J1: VIN
2.2.2 J2: VOUT
2.2.3 J3: GND
2.2.4 J4: GND
2.2.5 J5: Output Voltage Selection
Setup www.ti.com
This section describes the jumpers and connectors on the EVM as well as how to properly connect, setup, and use the TPS71401EVM.
CAUTION
Many of the components on the TPS71401EVM are susceptible to damage byelectrostatic discharge (ESD). Customers are advised to observe proper ESDhandling precautions when unpacking and handling the EVM, including the useof a grounded wrist strap at an approved ESD workstation.
Failure to observe proper ESD handling procedures may result in damage toEVM components.
This connector is the positive input supply voltage. The leads to the input supply should be twisted andkept as short as possible to minimize electromagnetic interference (EMI) transmission. Additional bulkcapacitance should be added between J1 and J2 if the supply leads are longer than 6 in (15,24 cm). Anadditional 47uF or greater capacitor improves the transient response of the TPS71401 and helps toreduce ringing on the input when long supply wires are used.
This point is the positive connection from the output. Connect this pin to the positive input of the load.
This is the return connection for the input power supply of the regulator.
This point is the return connection for the output.
This jumper is used to select the output voltage of the TPS71401. The jumper selects different feedbackresistors to change the output voltage setting. The output voltage is set by inserting a shorting jumperacross two pins of J5. The preprogrammed output voltages are configured as shown in Table 2 .
Table 2. Output Voltage Setting
Output Voltage (V) Jumper Between Pins
5.0 1 and 23.3 3 and 42.7 5 and 62.5 7 and 8
TPS71401DRVEVM-426 2 SBVU013 – January 2009Submit Documentation Feedback

3 Operation
3.1 Power On
3.2 Fixed Output TPS714xx Device Configuration
4 Thermal Guidelines
4.1 Thermal Considerations
T = T + P
J A D JA
´ q
(1)
www.ti.com Operation
Other output voltages can be configured by changing the feedback resistors on the board. The feedbacknetwork is high impedance and sensitive to noise or resistance value changes. The pins of J5 should notbe touched while the device is powered on because the impedance of a human is enough to alter theoutput voltage set point. The output voltage may increase or decrease if J5 is touched, which maydamage any load connected to the EVM.
This section discusses the operation of the TPS71401EVM.
Connect the positive input power supply to J1. Connect the input power return (ground) to J3. TheTPS71401EVM has an absolute maximum input voltage of 11.0 V. The recommended maximum operatingvoltage is 10 V. The actual highest input voltage may be less than 10 V as a result of thermal conditions.See the Thermal Considerations section of this manual to determine the highest input voltage.
Connect the desired load between J2 (positive lead) and J4 (negative or return lead). Configure jumper J5for the desired output voltage. The function of J5 is described in the Setup section of this manual.
The TPS71401 EVM can also be used to evaluate fixed-output voltage versions of the TPS714 LDO. Theboard layout and device footprints are the same for both the adjustable and the fixed-output voltageversions of the TPS714. To evaluate a fixed-output voltage version, the IC on the board must be changedto the desired fixed output voltage (TPS714xx). Note that R
1
must be removed from the EVM board if afixed output voltage version is mounted to the EVM board.
This section presents guidelines for the thermal management of the TPS71401DRVEVM-426 PCB.
Thermal management is a key design component of any power converter application and is especiallyimportant when the power dissipation in the LDO is high. To better help users design the TPS71401 familyinto an application, the following formula should be used to approximate the maximum power dissipationat a particular ambient temperature:
Where:
•T
J
is the junction temperature•T
A
is the ambient temperature•P
D
is the power dissipation in the IC• θ
JA
is the thermal resistance from junction to ambient
All temperatures are in degrees Celsius.
The thermal resistance from junction to ambient for the TPS71401EVM has a typical value of 65 °C/W. Therecommended maximum operating junction temperature specified in the data sheet for the TPS71401family is +125 °C. With these two pieces of information, the maximum power dissipation can be found byusing Equation 1 .
SBVU013 – January 2009 TPS71401DRVEVM-426 3Submit Documentation Feedback

+125 C = +85 C + P (65 C/W)
D
° ° °
(2)
P = (V V ) I = (-OUTD IN OUT V 3.3 V) 0.08 A = 0.615 W
IN -´ ´
(3)
5 Board Layout, Schematic, and Parts List
5.1 PCB Layouts
Board Layout, Schematic, and Parts List www.ti.com
Example 1. Maximum Power Dissipation Calculation
What is the maximum input voltage that can be applied to a TPS71401 with the output voltageconfigured to 3.3 V if the ambient temperature is +85 °C and the full 80 mA of load current is required?
Given:
T
J
= +125 °C, T
A
= +85 °C, θ
JA
= 65 °C/W
Using Equation 1 , we substitute in the given values above and find that the maximum power dissipationfor the part is P
D
= 0.615 W.
This result means that the total power dissipation of the TPS71401 must be less than 0.615 W. Now theinput voltage can be calculated:
Therefore, the maximum input voltage should be 10.98 V or less in order to maintain a safe junctiontemperature. However, the recommended maximum input voltage is 10.0 V, so the device can be usedover the entire recommended input voltage range.
Similar analyses can be performed to determine the maximum ambient temperature allowed and stillprovide the full output current while maintaining the junction temperature at or below +125 °C. Themaximum ambient temperature depends on the output voltage. Table 3 lists the maximum ambienttemperature allowed for the pre-programmed output voltages.
Table 3. Output Voltage and Maximum AmbientTemperature
Maximum AmbientOutput Voltage (V) Temperature ( °C)
5.0 993.3 902.7 872.5 86
This section provides the TPS71401DRVEVM-426 board layout and illustrations. It also includes theschematic and bill of materials for the EVM.
Figure 1 through Figure 3 show the layout for the TPS71401DRVEVM-426 PCB.
Note: Board layouts are not to scale. These figures are intended to show how the board is laid out;they are not intended to be used for manufacturing TPS71401DRVEVM-426 PCBs.
4TPS71401DRVEVM-426 SBVU013 – January 2009Submit Documentation Feedback

www.ti.com Board Layout, Schematic, and Parts List
Figure 1. Assembly Layer
SBVU013 – January 2009 TPS71401DRVEVM-426 5Submit Documentation Feedback

Board Layout, Schematic, and Parts List www.ti.com
Figure 2. Top Layer Routing
TPS71401DRVEVM-426 6 SBVU013 – January 2009Submit Documentation Feedback

www.ti.com Board Layout, Schematic, and Parts List
Figure 3. Bottom Layer Assembly
SBVU013 – January 2009 TPS71401DRVEVM-426 7Submit Documentation Feedback

Board Layout, Schematic, and Parts List www.ti.com
Figure 4. Bottom Layer Routing
TPS71401DRVEVM-426 8 SBVU013 – January 2009Submit Documentation Feedback

5.2 Schematic and BOM
www.ti.com Board Layout, Schematic, and Parts List
Figure 5 illustrates the TPS71401DRVEVM-426 schematic. Table 4 lists the bill of materials for this EVM.
Figure 5. TPS71401DRVEVM-426 Schematic
SBVU013 – January 2009 TPS71401DRVEVM-426 9Submit Documentation Feedback

Board Layout, Schematic, and Parts List www.ti.com
Table 4. TPS71401DRVEVM-426 Bill of Materials
(1) (2) (3)
Count RefDes
(4)
Value Description Size Part Number Mfr
1 C1 0.1 µF Capacitor, Ceramic, 0.1- µF, 603 STD Any16-V, X7R, 10%1 C2 2.2 µF Capacitor, Ceramic, 2.2- µF, 603 STD Any10-V, X7R, 10%4 J1, J2, PTC36SAAN Header, Two-pin, 100-mil 0.100 x 2 PTC36SAAN SullinsJ3, J4 spacing1 J5 PTC36DAAN Header, Male 2x4-pin, 0.20 x 0.40 in PTC36DAAN Sullins100-mil spacing1 N/A N/A PCB, 1.5 In x 1.2 In x 0.062 — HPA425 AnyIn1 R1 487 k Resistor, Chip, 1.00M Ω, 603 STD Any1/16-W, 1%1 R2 154 k Resistor, Chip, 1/16W, 5% 603 STD Any1 R3 280 k Resistor, Chip, 1/16W, 5% 603 STD Any1 R4 392 k Resistor, Chip, 1/16W, 5% 603 STD Any1 R5 453 k Resistor, Chip, 1/16W, 5% 603 STD Any1 U1 TPS71401DRV IC, 80-mA, 10-V Quiescent 2mm x 2mm TPS71401DRV TICurrent 3.2- µA LDO LinearRegulator1 — — 100-mm Two-Pin Shunt 0.100 x 2 929957-08 3M
(1)
These assemblies are ESD sensitive. ESD precautions shall be observed.(2)
These assemblies must be clean and free from flux and all contaminants. Use of no-clean flux is not acceptable.(3)
These assemblies must comply with workmanship standards IPC-A-610 Class 2.(4)
Components can be substituted with equivalent manufacturer components.
10 TPS71401DRVEVM-426 SBVU013 – January 2009Submit Documentation Feedback