Texas Instruments TPS543620 User manual

User’s Guide
TPS543620 SWIFT™ Step-Down Converter Evaluation
Module User's Guide
ABSTRACT
This user’s guide contains information for the TPS543620EVM evaluation module (BSR101) and the
TPS543620 dc/dc converter. Also included are the performance characteristics, schematic, and bill of materials
for the TPS543620EVM.
Table of Contents
1 Introduction.............................................................................................................................................................................3
1.1 Background........................................................................................................................................................................ 3
1.2 Before You Begin............................................................................................................................................................... 3
1.3 Performance Characteristics Summary............................................................................................................................. 4
2 Configurations and Modifications.........................................................................................................................................6
2.1 Output Voltage................................................................................................................................................................... 6
2.2 Switching Frequency (FSEL Pin)....................................................................................................................................... 7
2.3 Current Limit, Soft-Start Time, and Internal Compensation (MODE Pin)........................................................................... 7
2.4 Adjustable UVLO................................................................................................................................................................7
3 Test Setup and Results.......................................................................................................................................................... 8
3.1 Input/Output Connections.................................................................................................................................................. 8
3.2 Efficiency.......................................................................................................................................................................... 11
3.3 Output Voltage Regulation............................................................................................................................................... 14
3.4 Load Transient and Loop Response................................................................................................................................ 15
3.5 Output Voltage Ripple...................................................................................................................................................... 17
3.6 Input Voltage Ripple......................................................................................................................................................... 18
3.7 Synchronizing to a Clock..................................................................................................................................................19
3.8 Start-up and Shutdown with EN....................................................................................................................................... 20
3.9 Start-up and Shutdown with VIN...................................................................................................................................... 21
3.10 Start-up Into Pre-Bias.....................................................................................................................................................22
3.11 Hiccup Current Limit....................................................................................................................................................... 23
3.12 Overvoltage Protection...................................................................................................................................................24
3.13 Thermal Performance.................................................................................................................................................... 25
4 Board Layout.........................................................................................................................................................................26
4.1 Layout.............................................................................................................................................................................. 26
5 Schematic and Bill of Materials...........................................................................................................................................27
5.1 Schematic........................................................................................................................................................................ 28
5.2 Bill of Materials.................................................................................................................................................................30
6 Revision History................................................................................................................................................................... 31
List of Figures
Figure 3-6. U1 Load Regulation.................................................................................................................................................14
Figure 3-7. U1 Line Regulation..................................................................................................................................................14
Figure 3-8. U2 Load Regulation.................................................................................................................................................14
Figure 3-9. U2 Line Regulation..................................................................................................................................................14
Figure 3-10. U1 Transient Response.........................................................................................................................................15
Figure 3-11. U2 Transient Response......................................................................................................................................... 15
Figure 3-12. U1 Bode Plot......................................................................................................................................................... 15
Figure 3-13. U2 Bode Plot......................................................................................................................................................... 15
Figure 3-14. U2 Loop Gain with Different Ramp Settings..........................................................................................................16
Figure 3-15. U2 Loop Phase with Different Ramp Settings....................................................................................................... 16
Figure 3-16. U1 Output Ripple – No Load................................................................................................................................. 17
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Figure 3-17. U1 Output Ripple – 6-A Load................................................................................................................................ 17
Figure 3-18. U2 Output Ripple – No Load................................................................................................................................. 17
Figure 3-19. U2 Output Ripple – 6-A Load................................................................................................................................ 17
Figure 3-20. U1 Input Ripple – No Load.................................................................................................................................... 18
Figure 3-21. U1 Input Ripple – 6-A Load................................................................................................................................... 18
Figure 3-22. U2 Input Ripple – No Load.................................................................................................................................... 18
Figure 3-23. U2 Input Ripple – 6-A Load................................................................................................................................... 18
Figure 3-24. U1 and U2 Synchronized to a Clock..................................................................................................................... 19
Figure 3-25. U2 Clock Synchronization Transitions...................................................................................................................19
Figure 3-26. U2 Start-up with EN – No Load............................................................................................................................. 20
Figure 3-27. U2 Shutdown with EN – No Load..........................................................................................................................20
Figure 3-28. U2 Start-up with EN – 0.2-Ω Load.........................................................................................................................20
Figure 3-29. U2 Startup with EN – No Load and Measuring BP5..............................................................................................20
Figure 3-30. U2 Start-up with VIN – 0.3-Ω Load........................................................................................................................21
Figure 3-31. U2 Shutdown with VIN – 0.3-Ω Load.....................................................................................................................21
Figure 3-32. U2 Start-up Into 0.5-V Pre-Bias.............................................................................................................................22
Figure 3-33. U2 Output Overcurrent Protection – Overload with High Limit .............................................................................23
Figure 3-34. U2 Output Overcurrent Protection – Overload with Low Limit...............................................................................23
Figure 3-35. U2 Output Overcurrent Protection – Short with Low Limit.....................................................................................23
Figure 3-36. U2 OCP Hiccup and Recover – High Limit ...........................................................................................................23
Figure 3-37. U2 Overvoltage Protection.................................................................................................................................... 24
Figure 3-38. U2 OVP and Recover............................................................................................................................................24
Figure 3-39. U1 Thermal Performance – 6-A Load and U2 off..................................................................................................25
Figure 3-40. U2 Thermal Performance – 6-A Load and U1 off..................................................................................................25
Figure 3-41. U1 Thermal Performance – Both 6-A Load........................................................................................................... 25
Figure 3-42. U2 Thermal Performance – Both 6-A Load........................................................................................................... 25
Figure 4-1. Top-Side Composite View....................................................................................................................................... 26
Figure 4-2. Bottom-Side Composite View (Viewed From Bottom).............................................................................................26
Figure 4-3. Top Layer Layout.....................................................................................................................................................27
Figure 4-4. Mid Layer 1 Layout..................................................................................................................................................27
Figure 4-5. Mid Layer 2 Layout..................................................................................................................................................27
Figure 4-6. Bottom Layer Layout............................................................................................................................................... 27
Figure 5-1. U1 Schematic.......................................................................................................................................................... 28
Figure 5-2. U2 Schematic.......................................................................................................................................................... 29
List of Tables
Table 1-1. Input Voltage and Output Current Summary...............................................................................................................3
Table 1-2. TPS543620EVM Small Size (U1) Performance Characteristics Summary................................................................ 4
Table 1-3. TPS543620EVM High Efficiency (U2) Performance Characteristics Summary..........................................................5
Table 2-1. VOUT Selection.......................................................................................................................................................... 6
Table 2-2. FSEL Selection........................................................................................................................................................... 7
Table 2-3. MODE Selection......................................................................................................................................................... 7
Table 3-1. Connectors and Jumpers............................................................................................................................................9
Table 3-2. Test Points................................................................................................................................................................ 10
Table 3-3. Efficiency Measurement Test Points......................................................................................................................... 11
Table 5-1. TPS543620EVM Bill of Materials..............................................................................................................................30
Trademarks
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1 Introduction
1.1 Background
The TPS543620 dc/dc converter is a synchronous buck converter designed to provide up to a 6-A output. The
input (VIN) is rated for 4 V to 18 V. Rated input voltage and output current range for the evaluation module are
given in Table 1-1.
The high-side and low-side MOSFETs are incorporated inside the TPS543620 package along with the gate-
drive circuitry. The low drain-to-source on-resistance of the MOSFET allows the TPS543620 to achieve high
efficiencies and helps keep the junction temperature low at the rated output current. Fixed frequency advanced
current mode control allows you to synchronize the regulators to an external clock source. An external divider
allows for an adjustable output voltage. The TPS543620 FSEL and MODE pins provide selectable switching
frequency, soft start time, current limit, and internal compensation. Lastly, the TPS543620 includes an enable pin
and a power good output which can be used for sequencing multiple regulators.
This evaluation module includes two designs with the TPS543620. The first design is designed to demonstrate
the small printed-circuit-board areas that may be achieved when designing with the TPS543620 regulator. The
small area design fits within 100 mm2. The second design is designed to demonstrate the high efficiency that
can be achieved when designing with the TPS543620 regulator. The second design also includes jumpers that
can be used to easily evaluate the features of the TPS543620.
Table 1-1. Input Voltage and Output Current Summary
EVM INPUT VOLTAGE RANGE OUTPUT CURRENT RANGE
TPS543620EVM VIN = 4 V to 18 V 0 A to 6 A
1.2 Before You Begin
The following warnings and cautions are noted for the safety of anyone using or working close to the
TPS543620EVM. Observe all safety precautions.
Warning
The TPS543620EVM may become hot during operation due to dissipation of power
in some operating conditions. Avoid contact with the board. Follow all applicable
safety procedures applicable to your laboratory.
WARNING
The circuit module has signal traces, components, and component leads on the bottom of the board.
This may result in exposed voltages, hot surfaces or sharp edges. Do not reach under the board
during operation.
CAUTION
Some power supplies can be damaged by application of external voltages. If using more than
1 power supply, check your equipment requirements and use blocking diodes or other isolation
techniques, as needed, to prevent damage to your equipment.
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1.3 Performance Characteristics Summary
A summary of the TPS543620EVM performance characteristics is provided in Table 1-2 and Table 1-3. The
TPS543620EVM is designed and tested for VIN = 4 V to 18 V. Characteristics are given for an input voltage of
VIN = 12 V and , unless otherwise specified. The ambient temperature is room temperature (20°C to 25°C) for all
measurements, unless otherwise noted.
Table 1-2. TPS543620EVM Small Size (U1) Performance Characteristics Summary
SPECIFICATION TEST CONDITIONS MIN TYP MAX UNIT
VIN voltage range 4 12 13.2(1) V
Input current VIN = 12 V, IO = 0 A 14 mA
VIN = 5 V, IO = 6 A 1.39 A
VIN start voltage Set by internal UVLO 3.95 V
VIN stop voltage Set by internal UVLO 3.8 V
Output voltage setpoint 1.005 V
Output current range VIN = 4 V to 13.2 V 0 6 A
Line and load regulation VIN = 4 V to 13.2 V, IO = 0 A to 6 A ±0.1%
Load transient response
IO = 1.5 A to 4.5 A
Voltage change –25 mV
Recovery time to
within ±0.5% 70 µs
IO = 4.5 A to 1.5 A
Voltage change 25 mV
Recovery time to
within ±0.5% 70 µs
Loop bandwidth RO = 0.2 Ω 201 kHz
Phase margin 50 degrees
Input ripple voltage IO = 6 A 70 mVPP
Output ripple voltage IO = 6 A 9 mVPP
Output rise time Set by MODE pin resistor 1 ms
Current limit Set by MODE pin resistor High
Switching frequency (fSW) Set by FSEL pin resistor 1500 kHz
Peak efficiency VIN = 5 V, IO = 2.5 A 91.2%
VIN = 12 V, IO = 3.5 A 87.0%
IC case temperature VIN = 12 V, IO = 6 A, 15-minute soak 45.9 °C
(1) Max VIN limited by minimum on-time
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Table 1-3. TPS543620EVM High Efficiency (U2) Performance Characteristics Summary
SPECIFICATION TEST CONDITIONS MIN TYP MAX UNIT
VIN voltage range 4 12 18 V
Input current VIN = 12 V, IO = 0 A 11 mA
VIN = 5 V, IO = 6 A 1.37 A
VIN start voltage Set by EN pin resistor divider 4.53 V
VIN stop voltage Set by EN pin resistor divider 3.98 V
Output voltage setpoint J14 short pins 1 and 2 1.003 V
Output current range VIN = 4 V to 18 V 0 6 A
Line and load regulation VIN = 4 V to 18 V, IO = 0 A to 6 A ±0.1%
Load transient response
IO = 1.5 A to 4.5 A
Voltage change –28 mV
Recovery time to
within ±0.5% 60 µs
IO = 4.5 A to 1.5 A
Voltage change 25 mV
Recovery time to
within ±0.5% 60 µs
Loop bandwidth RO = 0.2 Ω, J18 short pins 3 and 4 140 kHz
Phase margin 56 degrees
Input ripple voltage IO = 6 A 90 mVPP
Output ripple voltage IO = 6 A 6 mVPP
Output rise time Set by MODE pin resistor, All default J18 options 1 ms
Current limit Set by MODE pin resistor, J18 short pins 1 and 2,
3 and 4, or 5 and 6 High
Switching frequency (fSW) Set by FSEL pin resistor, J17 short pins 3 and 4 1000 kHz
Peak efficiency VIN = 5 V, IO = 2 A 92.4%
VIN = 12 V, IO = 3 A 89.3%
IC case temperature VIN = 12 V, IO = 6 A, 15-minute soak 40.4 °C
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2 Configurations and Modifications
These evaluation modules are designed to provide access to the features of the TPS543620. The U2 design
provides jumpers for testing different configurations. Jumper selections must be made prior to enabling the
TPS543620.
If a desired configuration is not available, some modifications can be made to this module. When modifications
are made to the components on the EVM, the internal compensation option selected with the MODE pin resistor
can need to be changed. Changes to the fSW, output voltage, output inductor, and output capacitors can require
a change in the compensation. TPS543620 data sheet equations or WEBENCH can be used to calculate the
output capacitor value, compensation, fSW, and inductance. Ensure all components have sufficient voltage and
current ratings.
2.1 Output Voltage
In the U1 design, the output voltage is set by the resistor divider network of R7 (RFBT) and R8 (RFBB). R8 is
fixed at 1.00 kΩ to set the FB divider current at approximately 500 µA. To change the output voltage of the EVM,
the value of resistor R7 must change. Changing the value of R7 can change the output voltage above the 0.5-V
reference voltage (VREF). The value of R7 for a specific output voltage can be calculated using Equation 1. After
changing R7, the feedfoward capacitor (C8) can also need to be changed.
OUT
FBT FBB
REF
V
R R 1
V
§ ·
u 
¨ ¸
© ¹
(1)
In the U2 design, there are a few ways to set the output voltage. First, jumper J14 can be used to select between
the options shown in Table 2-1. If the desired output voltage is not available, a resistor must be changed. For
output voltages less than 0.8 V, TI recommends leaving J14 open and increasing R21. R21 becomes RFBB and
the required value for can be calculated with Equation 2, where RFBT is R15. For output voltages greater than
0.8 V, the jumper output voltage options can be changed by changing one of the resistors R23-R26. The RFBJ
resistor value to get a desired equivalent RFBB resistance can be calculated with Equation 3. To use J14 for
output voltages 3.3 V or larger, R20 should be reduced to 499 Ω.
REF
FBB FBT
OUT REF
V
R R
V V
u

(2)
 
FBB
FBJ
FBB
R R20 R21 R20 R21
R
R21 R
u   u

(3)
Table 2-1. VOUT Selection
JUMPER SETTING EQUIVALENT BOTTOM FB RESISTOR (RFBB) NOMINAL OUTPUT VOLTAGE
Open R21 = 8.25 kΩ 0.803 V
1 to 2 pin shorted(1) (R23+R20)||R21 = 4.97 kΩ 1.003 V
3 to 4 pin shorted (R24+R20)||R21 = 3.55 kΩ 1.204 V
5 to 6 pin shorted (R25+R20)||R21 = 2.48 kΩ 1.507 V
7 to 8 pin shorted (R26+R20)||R21 = 1.92 kΩ 1.803 V
(1) Default Setting
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2.2 Switching Frequency (FSEL Pin)
In the U2 design, jumper J17 can be used to select between the switching frequency options shown in Table 2-2.
If the desired option is not available, change one of the resistors to the value which sets the desired option.
In the U1 design, change the FSEL resistor to the value which sets the desired option.
Table 2-2. FSEL Selection
JUMPER SETTING FSEL RESISTOR SWITCHING FREQUENCY
1 to 2 pin shorted 17.4 kΩ 750 kHz
3 to 4 pin shorted(1) 11.8 kΩ 1000 kHz
5 to 6 pin shorted 8.06 kΩ 1500 kHz
7 to 8 pin shorted 4.99 kΩ 2200 kHz
(1) Default Setting
2.3 Current Limit, Soft-Start Time, and Internal Compensation (MODE Pin)
In the U2 design, jumper J18 can be used to select between the current limit, soft-start time, and internal
compensation options shown in Table 2-3. If the desired option is not available, change one of the resistors to
the value which sets the desired option.
In the U1 design, change the MODE resistor to the value which sets the desired option.
Table 2-3. MODE Selection
JUMPER SETTING MODE RESISTOR CURRENT LIMIT SOFT-START TIME RAMP
1 to 2 pin shorted 2.21 kΩ High 1 ms 1 pF
3 to 4 pin shorted(1) 4.87 kΩ High 1 ms 2 pF
5 to 6 pin shorted 11.3 kΩ High 1 ms 4 pF
7 to 8 pin shorted 60.4 kΩ Low 1 ms 2 pF
(1) Default Setting
2.4 Adjustable UVLO
The undervoltage lockout (UVLO) for U2 can be adjusted externally using R14 (RENT) and R17 (RENB). See the
TPS543620 data sheet for detailed instructions for setting the external UVLO.
In the U1 design, the EN pin is floating, so only the internal UVLO of the device is used.
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3 Test Setup and Results
This section describes how to properly connect, set up, and use the TPS543620EVM evaluation module.
The section also includes test results typical for the evaluation module and covers efficiency, output voltage
regulation, load transients, loop response, output ripple, input ripple, start-up, and current limit modes.
Measurements are taken with the following conditions unless otherwise noted.
• 12-V input
• Room temperature (20°C to 25°C)
• U2 with the default setting output voltage of 1 V, switching frequency of 1000 kHz, and maximum current limit
setting
• With the other converter disabled
3.1 Input/Output Connections
The TPS543620EVM is provided with input connectors, output connectors, and test points as shown in Table 3-1
and Table 3-2.
To support the minimum input voltage with the full rated load on both outputs with the default EVM, a power
supply capable of supplying greater than 5 A must be connected to J8 through a pair of 20-AWG wires or better.
Banana jacks J5 and J9 provide an alternative connection to input power supply.
For U1, the load must be connected to J2 and for U2, the load must be connected to J7. A pair of 20-AWG wires
or better must be used for each connection. With the maximum current limit setting, the maximum load current
capability is near 8 A before the TPS543620 goes into current limit. Wire lengths must be minimized to reduce
losses in the wires.
Test point TP11 provides a place to monitor the VIN input voltage with TP19 providing a convenient ground
reference. TP2 is used to monitor the output voltage of U1 with TP5 as the ground reference. TP15 is used to
monitor the output voltage of U2 with TP17 as the ground reference.
If modifications are made to the TPS543620EVM, the input current may change. The input power supply and
wires connecting the EVM to the power supply must be rated for the input current.
Note
For the FSEL pin of the TPS543620 to correctly detect the resistor value connected to ground, the
buffers on the EVM need to be provided a VCC voltage of 2 V to 5.5 V to go high impedance.
Populating the shunt on J15 will power both buffers from the BP5 of U2. If testing the U1 circuit with
the U2 disabled, connect an external power supply to pin 1 of J15 to power the buffers.
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Table 3-1. Connectors and Jumpers
REFERENCE
DESIGNATOR NAME RELATED IC FUNCTION
J2 VOUT U1 VOUT screw terminal to connect load to output
J4 EN_OFF U1 2-pin header for enable. Add shunt to connect EN to ground and disable device.
J5, J9 VIN Both Banana jack for positive terminal and negative terminal of input power supply
J7 VOUT U2 VOUT screw terminal to connect load to output
J8 VIN Both VIN screw terminal to connect input voltage (see Table 1-1 for VIN range)
J11 RDIV_VIN U2
2-pin header for enable divider. Remove shunt to disconnect EN pin divider for U2 from
VIN. If J11 shunt is removed and J13 shunt is populated, U2 EN pin is pulled to ground
through bottom resistor in divider disabling U2.
J13 EN_RDIV U2 2-pin header to connect enable divider to U2. Remove shunt to float EN pin of U2 to use
internal UVLO to enable U2.
J14 VOUT Select U2 VOUT selection header. Use shunt to set output voltage. See Table 2-1.
J15 ENSYNC_U1 U1 2-pin header to connect U1 buffer output enable to ground. Populate shunt to enable
output of buffer. Remove shunt to make buffer output high impedance.
J16 ENSYNC_U2 U2 2-pin header to connect U2 buffer output enable to ground. Populate shunt to enable
output of buffer. Remove shunt to make buffer output high impedance.
J17 FSEL Select U2 FSEL selection header. Use shunt to select FSEL resistor. See Table 2-2.
J18 MODE Select U2 MODE selection header. Use shunt to select MODE resistor. See Table 2-3.
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Table 3-2. Test Points
REFERENCE
DESIGNATOR NAME RELATED IC FUNCTION
TP1 VIN_U1 U1 VIN test point. Use this for efficiency measurements.
TP2 VOUT_U1 U1 VOUT test point. Use this for efficiency, output regulation, and bode plot measurements.
TP3 SW_U1 U1 SW node solder mask opening
TP4 PGND_U1 U1 PGND test point
TP5 PGND_EFF_U1 U1 PGND test point. Use this for efficiency measurements.
TP6 PGOOD_U1 U1 PGOOD test point
TP7 EN_U1 U1 EN test point. If applying an external voltage, it must be kept below the absolute maximum
voltage of the EN pin of 6 V.
TP8 AGND_U1 U1 AGND test point
TP9 BODE_U1 U1 Test point between voltage divider network and output voltage. Used for Bode plot
measurements.
TP10 VOUT_U1 U1 SMB connector to measure output voltage. When using this test point, the scope should
be set for 1-MΩ termination. When using 50-Ω termination, a 2:1 divider is created.
TP11 VIN Both VIN test point near input terminals
TP12 VIN_U2 U2 VIN test point. Use this for efficiency measurements.
TP13 SW_U2 U2 SW node solder mask opening
TP14 SW_U2 U2 SW node test point
TP15 VOUT_U2 U2 VOUT test point. Use this for efficiency, output regulation, and bode plot measurements.
TP16 PGND_U2 U2 PGND test point
TP17 PGND_EFF_U2 U2 PGND test point. Use this for efficiency measurements.
TP18 PGOOD_U2 U2 PGOOD test point
TP19 PGND Both PGND test point near input terminals
TP20 AGND_U2 U2 AGND test point
TP21 BP5_U2 U2 BP5 test point
TP22 BODE_U2 U2 Test point between voltage divider network and output voltage. Used for Bode plot
measurements.
TP23 EN_U2 U2 EN test point. If you are applying an external voltage, it must be kept below the absolute
maximum voltage of the EN pin of 6 V.
TP24 VO_ADJ U2 Test point for injecting current into the FB divider to adjust the DC output voltage or inject a
step to FB to test OVP
TP25 VO_2NDSTG U2 Test point to measure output voltage after second stage filter if added to EVM.
TP26 SYNC Both SYNC test point. Supply an external clock to this test point to synchronize both regulators
to it.
TP27 FSEL U2 FSEL test point
TP28 SW_U2 U2
SMB connector to measure SW node. When using this test point, the scope should be
set for 50-Ω termination. The combination of 50-Ω termination and 450-Ω series resistance
creates a 10:1 attenuation.
TP29 VOUT_U2 U2 SMB connector to measure output voltage. When using this test point, the scope should
be set for 1-MΩ termination. When using 50-Ω termination, a 2:1 divider is created.
TP30 VO_2NDSTG U2
SMB connector to measure output voltage after second stage filter if added to EVM. When
using this test point, the scope should be set for 1-MΩ termination. When using 50-Ω
termination, a 2:1 divider is created.
TP31 FGEN Both Test point to connect function generator to load transient circuit. Slowly increase amplitude
and vary slew rate of function generator for desired load step.
TP32 ISNS Both Test point to measure current in load transient circuit. Gain is 20 A/V.
TP33 PGND Both PGND test point for load transient circuit
TP34 MODE U2 MODE test point
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3.2 Efficiency
Figure 3-1 through Figure 3-5 show the efficiency for both designs on the TPS543620EVM. Using the selection
jumpers for U2, the results for different output voltage and switching frequency combinations are included. The
test points listed in Table 3-3 are used for the efficiency measurement. Use these test points to minimize the
contribution of PCB parasitic power loss to the measured power loss.
The following are some additional test setup considerations to minimize external sources of power dissipation.
• Disable the other regulator to avoid including the switching quiescent current of the other regulator in the
efficiency measurement. When testing U1 with U2 disabled, an external power supply should be used to
power the buffer connected to the FSEL pin as described in this note.
• Do not measure the SW pin of U2 with TP28 while measuring the efficiency of U2. Measuring the SW pin with
this test point loads this node with 500 Ω and the efficiency measurement will include the power lost in this
external resistance.
• Remove the shunts from J11 and J13 as a small amount of power is dissipated in the EN resistor divider
connected to U2.
Table 3-3. Efficiency Measurement Test Points
RELATED IC TEST POINT NAME REFERENCE
DESIGNATOR FUNCTION
U1
VIN_U1 TP1 Input voltage test point connected near pins of U1
VOUT_U1 TP2 Output voltage test point near output inductor of U1
PGND_EFF_U1 TP5 PGND reference test point for both input and output
voltages Kelvin connected near U1
U2
VIN_U2 TP12 Input voltage test point connected near pins of U2
VOUT_U2 TP15 Output voltage test point near output inductor of U2
PGND_EFF_U2 TP17 PGND reference test point for both input and output
voltages Kelvin connected near U2
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Output Current (A)
Efficiency (%)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
60
65
70
75
80
85
90
95
100
VIN = 5 V
VIN = 12 V
VIN = 15 V
VOUT = 1 V fSW = 1500 kHz
Figure 3-1. U1 Efficiency
Output Current (A)
Efficiency (%)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
60
65
70
75
80
85
90
95
100
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 18 V
VOUT = 1 V fSW = 1000 kHz
Figure 3-2. U2 Efficiency – Default Configuration
Output Current (A)
Efficiency (%)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
60
65
70
75
80
85
90
95
100
VOUT = 0.8 V
VOUT = 1 V
VOUT = 1.2 V
VOUT = 1.5 V
VOUT = 1.8 V
VIN = 12 V fSW = 1000 kHz
Figure 3-3. U2 Efficiency – 1000-kHz Switching
Frequency with Different Output Voltages
Output Current (A)
Efficiency (%)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
60
65
70
75
80
85
90
95
100
fSW = 750 kHz
fSW = 1000 kHz
fSW = 1500 kHz
fSW = 2200 kHz
VIN = 9 V VOUT = 1 V
Figure 3-4. U2 Efficiency – 1-V Output with
Different Switching Frequencies
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Output Current (A)
Efficiency (%)
0 0.4 0.8 1.2 1.6 2 2.4 2.8
60
65
70
75
80
85
90
95
100
fSW = 1000 kHz
fSW = 1500 kHz
fSW = 2200 kHz
VIN = 9 V VOUT = 1 V RMODE = 60.4 kΩ
Figure 3-5. U2 Efficiency – 1-V Output and Low Current Limit with Different Switching Frequencies
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3.3 Output Voltage Regulation
Figure 3-6 and Figure 3-7 show the load and line regulation for U1. Figure 3-8 and Figure 3-9 show the load and
line regulation for U2.
Output Current (A)
Output Voltage (V)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
1
1.001
1.002
1.003
1.004
1.005
1.006
1.007
1.008
1.009
1.01
VIN = 5 V
VIN = 12 V
VIN = 15 V
Figure 3-6. U1 Load Regulation
Input Voltage (V)
Output Voltage (V)
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
1
1.001
1.002
1.003
1.004
1.005
1.006
1.007
1.008
1.009
1.01
IOUT = 0 A
IOUT = 3 A
IOUT = 6 A
Figure 3-7. U1 Line Regulation
Output Current (A)
Output Voltage (V)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
0.998
0.999
1
1.001
1.002
1.003
1.004
1.005
1.006
1.007
1.008
VIN = 5 V
VIN = 12 V
VIN = 18 V
Figure 3-8. U2 Load Regulation
Input Voltage (V)
Output Voltage (V)
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
0.998
0.999
1
1.001
1.002
1.003
1.004
1.005
1.006
1.007
1.008
IOUT = 0 A
IOUT = 3 A
IOUT = 6 A
Figure 3-9. U2 Line Regulation
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3.4 Load Transient and Loop Response
Figure 3-10 and Figure 3-11 show the response to load transients for both designs. The current step is from 1.5
A to 4.5 A and the current step slew rate is 1 A/µs. An electronic load is used to provide a DC 1.5-A load and the
load transient circuit on the EVM is used to provide a 3-A step. The VOUT voltage is measured using TP10 for
U1 and TP29 for U2.
When using the load transient circuit included on the TPS543620EVM, slowly increase amplitude of function
generator for desired load step amplitude then vary the rise and fall times for the desired slew rate. The current
for the load step can be sensed with the ISNS test point. The default resistors on the EVM provide a gain of 20
A/V. With this gain, a 3-A step will result in 150-mV at the ISNS test point.
Note
To use the load transient circuit with U1, move R27 to R28.
Figure 3-12 and Figure 3-13 show the loop characteristics for both designs. Gain and phase plots are shown for
VIN voltage of 12 V and a 0.2-Ω resistive load.
Time (40 µs/div)
IOUT (1 A/div)
VOUT AC (20 mV/div)
Figure 3-10. U1 Transient Response
Time (100 µs/div)
VOUT AC (20 mV/div)
IOUT (1 A/div)
Figure 3-11. U2 Transient Response
Frequency (Hz)
Gain (dB)
Phase (°)
100 200 5001000 10000 100000 1000000
-40 -120
-20 -60
0 0
20 60
40 120
60 180
Gain
Phase
Figure 3-12. U1 Bode Plot
Frequency (Hz)
Gain (dB)
Phase (°)
100 200 5001000 10000 100000 1000000
-40 -120
-20 -60
0 0
20 60
40 120
60 180
Gain
Phase
Figure 3-13. U2 Bode Plot
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Figure 3-14 and Figure 3-15 shows the loop characteristics for U2 with the 3 different ramp settings.
Frequency (Hz)
Gain (dB)
100 200 5001000 10000 100000 1000000
-40
-20
0
20
40
60
Ramp = 4 pF
Ramp = 2 pF
Ramp = 1 pF
Figure 3-14. U2 Loop Gain with Different Ramp
Settings
Frequency (Hz)
Phase (°)
100 200 5001000 10000 100000 1000000
-120
-90
-60
-30
0
30
60
90
120
150
180
Ramp = 4 pF
Ramp = 2 pF
Ramp = 1 pF
Figure 3-15. U2 Loop Phase with Different Ramp
Settings
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3.5 Output Voltage Ripple
Figure 3-16 through Figure 3-19 show the TPS543620EVM output voltage ripple. The load currents are no load
and 6 A. VIN = 12 V. The VOUT voltage is measured using TP10 for U1 and TP29 for U2.
Time (1 µs/div)
VOUT AC (10 mV/div)
SW (5 V/div)
Figure 3-16. U1 Output Ripple – No Load
Time (1 µs/div)
VOUT AC (10 mV/div)
SW (5 V/div)
Figure 3-17. U1 Output Ripple – 6-A Load
Time (1 µs/div)
VOUT AC (10 mV/div)
SW (5 V/div)
Figure 3-18. U2 Output Ripple – No Load
Time (1 µs/div)
VOUT AC (10 mV/div)
SW (5 V/div)
Figure 3-19. U2 Output Ripple – 6-A Load
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3.6 Input Voltage Ripple
Figure 3-20 through Figure 3-23 show the TPS543620EVM input voltage ripple. The load currents are no load
and 6 A. VIN = 12 V. The ripple voltage is measured across C1 for U1 and measured across C13 for U2.
Time (1 µs/div)
VIN AC (10 mV/div)
SW (5 V/div)
Figure 3-20. U1 Input Ripple – No Load
Time (1 µs/div)
VIN AC (50 mV/div)
SW (5 V/div)
Figure 3-21. U1 Input Ripple – 6-A Load
Time (1 µs/div)
VIN AC (10 mV/div)
SW (5 V/div)
Figure 3-22. U2 Input Ripple – No Load
Time (1 µs/div)
VIN AC (50 mV/div)
SW (5 V/div)
Figure 3-23. U2 Input Ripple – 6-A Load
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3.7 Synchronizing to a Clock
Figure 3-24 shows U1 and U2 synchronized to an external clock of 1.25 MHz at the SYNC test point. To
synchronize to the clock at the SYNC test point, place a shunt on the ENSYNC_U1 or ENSYNC_U2 jumper or
jumpers to enable the output of the buffers.
Figure 3-25 shows the transitions to and from synchronizing to an external clock with 6-A load. 16 pulses with
a frequency of 1-MHz were sent to the SYNC testpoint on the EVM. In this waveform, after four pulses, the
TPS543620 begins synchronizing to the clock. After the clock goes away, the TPS543620 switches at 70% of
the internal clock frequency for four pulses then transitions back to the normal internal clock frequency. There is
only a small variation in the output voltage during these transitions.
Time (1 µs/div)
SW_U1 (5 V/div)
SW_U2 (5 V/div)
SYNC (2 V/div)
Figure 3-24. U1 and U2 Synchronized to a Clock
Time (4 µs/div)
VOUT AC (10 mV/div)
SW (5 V/div)
SYNC (5 V/div)
Figure 3-25. U2 Clock Synchronization Transitions
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3.8 Start-up and Shutdown with EN
Figure 3-26 and Figure 3-27 show the start-up and shutdown waveforms for U2 with EN. In Figure 3-26, the
input voltage is initially applied and the output is inhibited by pulling EN to GND using an external function
generator. When the EN voltage is increased above the enable-threshold voltage, the start-up sequence begins
and the output voltage ramps up to the externally set value. In Figure 3-27, the external function generator pulls
EN to ground and the TPS543620 shuts down.
Figure 3-28 shows EN start-up with a 0.2-Ω resistor load. Figure 3-29 shows the BP5 internal LDO start-up
relative to the EN pin.
A shunt on the ENOFF_U1 jumper or RDIV_VIN can be used to test the EN start-up of U1 and U2, respectively.
When the shunt is removed from ENOFF_U1, EN is released and the start-up sequence begins for U1. When
the shunt is placed on RDIV_VIN, EN is pulled to the input voltage through the resistor divider and the start-up
sequence begins for U2.
Time (400 µs/div)
VOUT (500 mV/div)
SW (10 V/div)
EN (2 V/div)
PGOOD (5 V/div)
Figure 3-26. U2 Start-up with EN – No Load
Time (400 µs/div)
VOUT (500 mV/div)
SW (10 V/div)
EN (2 V/div)
PGOOD (5 V/div)
Figure 3-27. U2 Shutdown with EN – No Load
Time (400 µs/div)
VOUT (500 mV/div)
IOUT (5 A/div)
EN (2 V/div)
PGOOD (5 V/div)
Figure 3-28. U2 Start-up with EN – 0.2-Ω Load
Time (400 µs/div)
VOUT (500 mV/div)
BP5 (5 V/div)
EN (2 V/div)
PGOOD (5 V/div)
Figure 3-29. U2 Startup with EN – No Load and
Measuring BP5
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