Texas Instruments TPS7H500-SP Series User manual

User’s Guide
TPS7H500x-SP Evaluation Module User's Guide
ABSTRACT
This user's guide describes the characteristics, operation, and use of the TPS7H5001EVM-CVAL,
TPS7H5002EVM-CVAL, TPS7H5003EVM-CVAL, TPS7H5004EVM-CVAL evaluation module (EVM). Setup to
ensure proper operation of the device as well as a complete schematic diagram, printed-circuit board layouts,
and bill of materials are included in this document. Basic waveforms of operation are also shown.
Table of Contents
1 Introduction.............................................................................................................................................................................3
1.1 Features............................................................................................................................................................................. 3
1.2 Applications........................................................................................................................................................................3
2 EVM Setup and Quick Start Guide........................................................................................................................................ 4
3 EVM Connectors and Test Points..........................................................................................................................................7
4 PCB Layouts..........................................................................................................................................................................10
5 Schematics............................................................................................................................................................................12
6 Bill of Materials..................................................................................................................................................................... 24
List of Figures
Figure 2-1. Positive and Negative Terminal for J11..................................................................................................................... 4
Figure 2-2. TPS7H5001/2/3/4-SP Output.................................................................................................................................... 5
Figure 2-3. Duty Cycle Generation.............................................................................................................................................. 6
Figure 4-1. Top Overlay............................................................................................................................................................. 10
Figure 4-2. Top Solder............................................................................................................................................................... 10
Figure 4-3. Top Layer.................................................................................................................................................................10
Figure 4-4. Bottom Layer........................................................................................................................................................... 10
Figure 4-5. Bottom Solder..........................................................................................................................................................11
Figure 4-6. Bottom Overlay........................................................................................................................................................11
Figure 4-7. Drill Drawing............................................................................................................................................................ 11
Figure 4-8. Board Dimensions................................................................................................................................................... 11
Figure 5-1. TPS7H5001EVM-CVAL Schematic (Page 1).......................................................................................................... 12
Figure 5-2. TPS7H5001EVM-CVAL Schematic (Page 2).......................................................................................................... 13
Figure 5-3. TPS7H5001EVM-CVAL Schematic (Page 3).......................................................................................................... 14
Figure 5-4. TPS7H5002EVM-CVAL Schematic (Page 1).......................................................................................................... 15
Figure 5-5. TPS7H5002EVM-CVAL Scheamtic (Page 2).......................................................................................................... 16
Figure 5-6. TPS7H5002EVM-CVAL Schematic (Page 3).......................................................................................................... 17
Figure 5-7. TPS7H5003EVM-CVAL Schematic (Page 1).......................................................................................................... 18
Figure 5-8. TPS7H5003EVM-CVAL Schematic (Page 2).......................................................................................................... 19
Figure 5-9. TPS7H5003EVM-CVAL Schematic (Page 3).......................................................................................................... 20
Figure 5-10. TPS7H5004EVM-CVAL Schematic (Page 1)........................................................................................................ 21
Figure 5-11. TPS7H5004EVM-CVAL Schematic (Page 2)........................................................................................................ 22
Figure 5-12. TPS7H5004EVM-CVAL Schematic (Page 3)........................................................................................................ 23
List of Tables
Table 2-1. Default EVM Configuration......................................................................................................................................... 4
Table 2-2. TPS7H5001/2/3/4EVM-CVAL Connections................................................................................................................ 4
Table 3-1. EVM Board Connections.............................................................................................................................................7
Table 3-2. J6 Connections and Configuration..............................................................................................................................9
Table 6-1. TPS7H5001EVM-CVAL Bill of Materials...................................................................................................................24
Table 6-2. TPS7H5002EVM-CVAL Bill of Materials...................................................................................................................27
Table 6-3. TPS7H5003EVM-CVAL Bill of Materials...................................................................................................................30
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Table 6-4. TPS7H5004EVM-CVAL Bill of Materials...................................................................................................................33
Trademarks
All trademarks are the property of their respective owners.
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1 Introduction
This board enables the TPS7H5001/2/3/4EVM-CVAL to be connected to other components needed to quickly
prototype and evaluate a complete power converter design. The TPS7H5001EVM-CVAL is placed on an open
test board similar to the board used in the TPS7H5001-SP Lookahead Total Ionizing Dose (TID) radiation report.
Adding test points and voltage terminals is the only major change to the design that was needed to facilitate
probing the TPS7H5001/2/3/4EVM-CVAL without additional hardware. Minor changes were made to the BOM for
manufacturability purposes.
1.1 Features
This EVM has the following features:
• Synchronous rectification outputs with adjustable dead time
• 0.613-V ±1% Voltage reference overtemperature, radiation, and line and load
• Adjustable slope compensation and soft start
• Configurable duty cycle limit
1.2 Applications
• Space satellite isolated power supplies
• Radiation hardened applications
• Space satellite payloads
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2 EVM Setup and Quick Start Guide
Default EVM Configuration lists the default configuration.
Table 2-1. Default EVM Configuration
Parameter Specification
Input Power Supply 4 V to 14 V
Operating Temperature 25°C
Switching Frequency 500 kHz
The TPS7H5001/2/3/4EVM-CVAL can be quickly turned on and run using the connections shown in
TPS7H5001EVM-CVAL Connections.
Table 2-2. TPS7H5001/2/3/4EVM-CVAL Connections
Terminal or Test Point Voltage Source
J11 (VIN) 4 to 14-V input at 10 mA. See Positive and Negative Terminal for J11 for
connections.
TP9 (COMP) 1 V at < 10 mA (input range can be –0.3 V to 3.3 V based on the
TPS7H5001-SP Radiation-Hardness-Assured Si and GaN Dual Output
Controller data sheet)
Positive and Negative Terminal for J11 shows which terminal is the positive and negative on J11. Connect the
positive input voltage to the positive terminal and GND to negative terminal.
Figure 2-1. Positive and Negative Terminal for J11
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The device then turns on and operates in open loop mode as shown in TPS7H5001-SP Output. TPS7H5001-SP
Output shows the output of TPS7H5001-SP measured on J1–J4 with the quick start method.
Figure 2-2. TPS7H5001/2/3/4-SP Output
The operation of this mode is such that forcing the voltage on COMP creates an output on the
TPS7H5001/2/3/4EVM-CVAL. The duty cycle varies based on the input voltage on COMP as well as the triangle
waveform created by the CS_LIM circuit or any other waveform that the user decides to add to the CS_LIM
pin. See Duty Cycle Generation for signal generation waveforms. Note that OUTB and SRB is not present for
TPS7H5002EVM-CVAL and TPS7H5003EVM-CVAL. SRA and SRB are not present for TPS7H5004EVM-CVAL.
Duty Cycle Generation shows waveforms for input and output signal generations for the TPS7H5001/2/3/4EVM-
CVAL based on COMP voltage and CS_LIM pin voltage.
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Figure 2-3. Duty Cycle Generation
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3 EVM Connectors and Test Points
Table 3-1 is a list of major connections on the board. For further information, see the relevant section in the
TPS7H5001-SP Radiation-Hardness-Assured Si and GaN Dual Output Controller data sheet. A ✓ means that
the test point is included in the EVM.
Table 3-1. EVM Board Connections
Test Point 5001 5002 5003 5004 Connection Description
TP1, J1 ✓✓✓✓OUTA
Connected to the gate driver in the design.
Components R5, C5 can be used to test
different R/C loads.
TP2, J2 ✓ ✓ OUTB
Connected to the gate driver in the design.
Components R6, C6 can be used to test
different R/C loads.
TP3, J3 ✓✓✓ SRA
Connected to the gate driver in the design.
Components R7, C7 can be used to test
different R/C loads.
TP4, J4 ✓SRB
Connected to the gate driver in the design.
Components R8, C8 can be used to test
different R/C loads.
TP5, TP6 ✓✓✓✓CS_LIM
Input for current sense in the design.
The CS_LIM circuit provides small triangle
waveform from OUTA, OUTB. Note that
this can load OUTA, OUTB causing a
slow in the slew rate. If R9 and R10 are
unpopulated, CS_LIM can be force from
TP5.
TP7 ✓✓✓✓VIN Voltage input for the
TPS7H5001/2/3/4EVM-CVAL device
TP8 ✓✓✓✓EN Enable pin for the TPS7H5001/2/3/4EVM-
CVAL device, currently pulled high to VLDO
TP9 ✓✓✓✓COMP
Error amplifier output for the
TPS7H5001/2/3/4EVM-CVAL, forcing this
voltage runs the TPS7H5001/2/3/4EVM-
CVAL in open loop.
TP10 ✓✓✓✓REFCAP Internal reference for
TPS7H5001/2/3/4EVM-CVAL
TP11, TP12 ✓✓✓✓SS
In a closed loop design, this slowly
increases converter output voltage during
start-up
TP13, TP15 ✓✓✓✓SYNC
Inputting a clock on this pin synchronizes
the TPS7H5001/2/3/4EVM-CVAL to a
frequency half of the input frequency
TP14 ✓✓✓✓VLDO Internal voltage rail for device logic
TP20 ✓✓✓✓VSENSE
Voltage sense for the
TPS7H5001/2/3/4EVM-CVAL. Connected
to converter output voltage in the full
design.
TP21 ✓✓✓✓RSC
Slope compensation selection resistor. Sets
slope compensation slew rate internal to
the device.
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Table 3-1. EVM Board Connections (continued)
Test Point 5001 5002 5003 5004 Connection Description
TP22 ✓✓✓✓HICC
Configurability for the hiccup time of
the converter. While grounded through a
resistor on the EVM, in a full design it is
generally a capacitor.
TP23 ✓✓✓✓FAULT
A signal high on this node turns the
TPS7H5001/2/3/4EVM-CVAL off for any
fault condition needed
TP24 ✓ ✓ SP Configurability for the delay between the
synchronous rectifiers and main output
TP25 ✓✓✓✓RT
Frequency select for the
TPS7H5001/2/3/4EVM-CVAL. Change this
to vary the frequency of the converter.
TP26 ✓ ✓ PS Configurability for the delay between the
main output and synchronous rectifiers
TP27 ✓ ✓ ✓ LEB Configurability for the leading edge
blanking time of the converter
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Table 3-2 describes and lists the connections and configuration for J6. Use J6 to switch between different DCL
connections to test different duty cycle limits. Pin 1 is noted by the dot next to the pin.
Table 3-2. J6 Connections and Configuration
Pin Connection Duty Cycle Limit Configuration Description
Pin 1 and Pin 2 100% DCL is connected high to VLDO,
Used for TPS7H5001/2/3 EVM variants
Pin 2 and Pin 3 50% DCL is connected low to AVSS,
Used for TPS7H5001/4 EVM variants
Floating 75% DCL is left floating,
Used for TPS7H5001/2/3 EVM variants
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4 PCB Layouts
Top Overlay through Board Dimensions show the EVM PCB layout images.
Figure 4-1. Top Overlay
Figure 4-2. Top Solder
Figure 4-3. Top Layer Figure 4-4. Bottom Layer
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Figure 4-5. Bottom Solder Figure 4-6. Bottom Overlay
Figure 4-7. Drill Drawing
Figure 4-8. Board Dimensions
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5 Schematics
Figure 5-1 through Figure 5-12 show the EVM schematics.
VIN
9
COMP 22
CS_ILIM
16
DCL 7
EN
8
FAULT
17
HICC
5
LEB
4
OUTA 10
OUTB 11
PS
2
REFCAP
18
RSC
19
RT
1
SP
3
SRA 13
SRB 12
SS 20
SYNC
6VLDO 15
VSENSE 21
AVSS 14
EP 23
TPS7H5001HKY-EM
U1
AGND AGND
SYNC
SYNC
TP13
AGND
VLDO TP14
AGND
135k
R31
AGND
1.00k
R14
10.0
R24
10.0
R26
20.0k
R15
49.9k
R39
1.00M
R35
30.0k
R40
49.9k
R30
49.9k
R29
10.0k
R9
10.0k
R10
4.70k
R41
5.90k
R27
3.90k
R25
470nF
C15
500pF
C10
20pF
C5
20pF
C17
1µF
C18
10nF
C16
191k
R33
VIN
VIN
TP7
VLDO
VIN
VLDO
0
R12
0
R11
DNP
PXIe-4145 (CH#0) F+
PXIe-4145 (CH#0) S+
PXIe-4145 (CH#0) S-
0
R16
DNP
AGND
AGND
AGND AGND
50V
1µF
C14
DNP
0
R4
PXIe-4112 (CH#1)
PXIe-4112 (CH#1) S+
PXIe-4112 (CH#1) S-
0
R1
100nF
25V
C9
REFCAP
REFCAP
REFCAP
TP10
OUTA OUTB
CS_ILIM
CS_ILIM
CS_ILIM
TP5
G
TP6
AGND
G
TP15 PXIe-4145 (CH#1) F+
PXIe-4145 (CH#1) S+
PXIe-4145 (CH#1) S-
0
R34
DNP
0
R37
DNP
100nF
25V
C19
DNP
SS
TP11
1
2
I_VIN
J5
IVIN_P
IVIN_N
150uF
C1
AGND
0.1uF
C4
10uF
C3
10uF
C2
G
TP12
AGND
VLDO
0
R19
DNP
0
R22
DNP
1.00M
R5
DNP
AGND
OUTA OUTB
OUTA
OUTB
20pF
C6
1.00M
R6
DNP
AGND
20pF
C7
1.00M
R7
DNP
AGND
SRA SRB
20pF
C8
1.00M
R8
DNP
AGND
SRA
SRB
AGND_SENSE
AGND_SENSE
1
2
3 4 5
J1
AGND
OUTA 1
2
3 4 5
J2
AGND
OUTB 1
2
3 4 5
J3
AGND
1
2
3 4 5
J4
AGND
SRA SRB
OUTA
TP1
EN
TP8
SRA
TP3
OUTB
TP2
SRB
TP4
20pF
C5
1.00M
R5
DDNNNNNNP
1.00M1.00M
R5R5
AGND
OUTA OUTB
20pF
C6
1.00M
R6
DDNNNNNNNP
1.00M1.00M
R6R6
AGND
20pF
C7
1.00M
R7
DDNNNNNNNP
1.00M1.00M
R7R7
AGND
SRA SRB
20pF
C8
1.00M
R8
DDNNNNNNNP
1.00M1.00M
R8R8
AGND
1
2
3 4 5
J1
AGND
OUTA 1
2
3 4 5
J2
AGND
OUTB 1
2
3 4 5
J3
AGND
1
2
3 4 5
J4
AGND
SRA SRB
OUTA
TP1
SRA
TP3
OUTB
TP2
SRB
TP4
PWM's Output and Loading
470nF
C15
AGND
50V
1µF
C14
DDDDDNNNNNNNPPP
REFCAP
REFCAP
TP10
REFCAP
AGND
20.0k
R15
10.0k
R9
10.0k
R10
500pF
C10
OUTA OUTB
CS_ILIM
CS_ILIM
TP5
GG
TP6
CS_ILIM
0
R44
0
R13
0
R17
0
R18
0
R20
COMP
TP9
E36311A-1 (+6V)
10nF
C12 DNP
1000pF
C11 DNP
10.0k
R21
DNP
0
R28
DNP
0
R42
0
R38
DIO_6B
DIO_7B
COMP
EN
HICC
FAULT
SP
PS
RT
SYNC
LEB
RSC DCL
VSENSE
SS
PXIe-4113 (CH#1) S+ 0
R3
FAULT
0
R2
PXIe-4113 (CPXPX H#1) S+HH 0
R3
FAULT
0
R2
FAULT
PXIe-4113 (CH#1) S- 0
R43
VSENSE
COMP
1.0k
R36
470nF
C13
DNP
HICC
AGND
1
2
3
J6
AGND
DCL
0
R32
VLDO
PXIe-4137 S-
PXIe-4137 S+
PXIe-4137 F+ DCL
470nF
C13
DDDDDNNNNNNPPP
HICC
AGND
HICC
0
R23
DNP
0
R45
R47
0
R46
PXIe-4113 (CH#1) F+
0
R118
1
2
J11
ED120/2DS
TP28
AGND
TP29TP30TP31
Figure 5-1. TPS7H5001EVM-CVAL Schematic (Page 1)
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PXIe-5162_CH0
PXIe-5162_CH1
PXIe-5162_CH2
PXIe-5162_CH3
OUTA
OUTB
SRA
SRB
0
R48
VLDO
REFCAP
VIN
EN
HICC
FAULT
SP
RT
PS
SYNC
LEB
RSC
VLDO
COMP_BUFFER
VSENSE
SS_BUFFER
0
R60
0
R75
0
R54
0
R68
0
R78
0
R81
0
R84
0
R49
0
R55
0
R61
0
R69
0
R76
0
R79
0
R82
0
R85
0
R74
0
R77
0
R80
0
R83
PXIe-5110_CH0
PXIe-5110_CH1
0
R53
OUTA
SRA 0
R52
DNP
0
R59
OUTB
SRB 0
R58
DNP
DMM_Site1_1
DMM_Site1_2
DMM_Site1_3
AWG_CH1_to_SIte1
PXIe-5172-1_CH1_Site1
PXIe-5172-1_CH3_Site1
PXIe-5172-1_CH5_Site1
PXIe-5172-1_CH7_Site1
PXIe-5172-2_CH1_Site1
PXIe-5172-2_CH3_Site1
PXIe-5172-2_CH5_Site1
PXIe-5172-2_CH7_Site1
DMM_Site1_4
DMM_Site1_5
AWG_CH2_to_SIte1
PXIe-5172-1_CH0_Site1
PXIe-5172-1_CH2_Site1
PXIe-5172-1_CH4_Site1
PXIe-5172-1_CH6_Site1
PXIe-5172-2_CH0_Site1
PXIe-5172-2_CH2_Site1
PXIe-5172-2_CH4_Site1
PXIe-5172-2_CH6_Site1
1
2
3
4
5
OPA354AIDBVR
U5
100nF
25V
C26
DNP
0
R96
0
R86
0
R94
0
R97
DNP
4
1
2
SN74AHCT1G08DCKR
U2A
VCC
5GND 3
SN74AHCT1G08DCKR
U3B
4
1
2
SN74AHCT1G08DCKR
U3A
VCC
5GND 3
SN74AHCT1G08DCKR
U2B
AGND
AGND
AGND AGND
OUTA
SRA
OUTB
SRB
PXIe-5162_CH0
PXIe-5162_CH1
0
R63
0
R70
PXIe-5162_CH0
PXIe-5162_CH1
4
1
2
SN74AHCT1G08DCKR
U2AUU
VCC
5GND 3
SN74AHCT1G08DCKR
U3B
4
1
2
SN74AHCT1G08DCKR
U3A
VCC
5GND 3
SN74AHCT1G08DCKR
U2BUU
AGND
AGND
AGND AGND
OUTATT
SRARR
OUTB
SRB
0
R63
0
R70
PXIe-5162_CH0
PXIe-5162_CH1
Cross Conduction Trigger
In Case Cross Conduction in A, we send trigger to C H1 and we capture OUTA-CH0 and SRA-CH2
In Case Cross Conduction in B, we send trigger to C H0 and we capture OUTB-CH1 and SRB-CH3
COMP COMP_BUFFER
AGND
AGND
1
2
3
4
5
OPA35AA 4AIDBVR
U5
100nF
25V
C26
DDDDDNNNNNPPPPP
0
R96
0
R86
0
R94
0
R97
DDDDDDNNNNNNPPPPP
COMP COMP_BUFFER
AGND
AGND
COMP Buffer
Do we Need a HS Comparator to Adjust VIH??
PXIe-5110_CH0
PXIe-5110_CH1
0
R53
OUTATT
SRARR 0
R52
DDDDDDNNNNPPPP
0
R59
OUTB
SRB 0
R58
DDDDDDNNNNPPPP
PXIe-5110 (PWM Trigger Supported)
PXIe-5162_CH0
PXIe-5162_CH1
PXIe-5162_CH2
PXIe-5162_CH3
OUTATT
OUTB
SRARR
SRB
0
R74
0
R77
0
R80
0
R83
PXIe-5162_CH0
PXIe-5162_CH1
PXIe-5162 (HS Scope) or DPO7XXXX Series
0
R48
VLDO
REFCAP
VIN
EN
RSC
COMP_BUFFER
VSENSE
SS_BUFFER
0
R60
0
R75
0
R54
0
R68
0
R78
0
R81
0
R84
PXIe-5172-1_CH1_Site1
PXIe-5172-1_CH3_Site1
PXIe-5172-1_CH5_Site1
PXIe-5172-1_CH7_Site1
PXIe-5172-1_CH0_Site1
PXIe-5172-1_CH2_Site1
PXIe-5172-1_CH4_Site1
PXIe-5172-1_CH6_Site1
PXIe-5172 (General Purpose Up to 100MHz)
HICC
FAULT
SP
RT
PS
SYNC
LEB
VLDO 0
R49
0
R55
0
R61
0
R69
0
R76
0
R79
0
R82
0
R85
PXIe-5172-2_CH1_Site1
PXIe-5172-2_CH3_Site1
PXIe-5172-2_CH5_Site1
PXIe-5172-2_CH7_Site1
PXIe-5172-2_CH0_Site1
PXIe-5172-2_CH2_Site1
PXIe-5172-2_CH4_Site1
PXIe-5172-2_CH6_Site1
PXIe-5172 (General Purpose Up to 100MHz)
0
R57
DNP
OUTA
SRA 0
R51
DNP
0
R73
DNP
OUTB
SRB 0
R65
DNP
OUTA
OUTB
SRA
SRB
0
R50
DNP
0
R56
DNP
0
R64
DNP
0
R72
DNP
SYNC 0
R89
CS_ILIM 0
R92
AWAA G_CH1_to__ SIte1
AWAA G_CH2_to__ SIte1
SYNC 0
R89
CS_ILIM 0
R92
External CLK Syncronization
0
R87
0
R88
0
R90
0
R91
0
R93
VLDO
REFCAP
VIN
COMP_BUFFER
DMM_Site1_1
DMM_Site1_2
DMM_Site1_3
DMM_Site1_4
DMM_Site1_5
0
R87
0
R88
0
R90
0
R91
0
R93
VLDO
REFCAP
VIN
COMP_BUFFER
DMM
PXIe-5922_CH0_Site1
PXIe-5922_CH1_Site1
1
2
3
4
5
OPA354AIDBVR
U6
100nF
25V
C34
DNP
0
R106
0
R104
0
R105
0
R107
DNP
SS SS_BUFFER
AGND
AGND
1
2
3
4
5
OPA35AA 4AIDBVR
U6
100nF
25V
C34
DDDDDDNNNNNNNNPPPPP
0
R106
0
R104
0
R105
0
R107
DDDDDDNNNNNNPPPPP
SS SS_BUFFER
AGND
AGND
SS Buffer
SS_BUFFER
0
R102
0
R99
COMP_B_IN TP17 COMP_B_OUT
TP16
100nF
25V
C20
1µF
50V
C21
1nF
50V
C22
1µF
50V
C24
1nF
50V
C25
100nF
25V
C23
1µF
50V
C28
1nF
50V
C29
100nF
25V
C27
1µF
50V
C36
1nF
50V
C37
100nF
25V
C35
100nF
25V
C39
DNP
AGND
100nF
25V
C38
DNP
100nF
25V
C32
DNP
100nF
25V
C33
DNP
AGND
SS_B_IN TP19 SS_B_OUT
TP18
SS_BUFFER
COMP_BUFFER
PXIe-5922_CH0_Site1
PXIe-5922_CH1_Site1
0
R102
0
R99
SS_BUFFER
COMP_BUFFER
PXIe-5922 (High Presicion)
0
R62
0
R66
0
R67
0
R71
1 3
2
GND
10
R100
Heater
AGND
PXIe-4139-1 F+
PXIe-4139-1 S+
0
R103
0
R101
PXIe-4139-1 S-
0
R98
1 3
2
GND
10
R100
Heater
AGND
PXIe-4139-1 F+
PXPP Ie-4XX 139-1 S+
0
R103
0
R101
PXPP Ie-4XX 139-1 S-
0
R98
IN
3OUT 2
1
TAB 4
GND
LM1117MPX-5.0
U4
E36311A-1 (+25V)
AGND
10V
47uF
C31
AGND
+5V
+5V
+5V
+5V
0
R95
E36311A-1 (+25V) +5V
IN
3OUT 2
1
TATT B 4
GNDGG
LM1117MPX-5XX .0
U4UU
E36311A-1AA (+25V)
AGND
10V
47uF
C31
AGND
+5V
0
R95
E36311A-1AA (+25V) +5V
LDO
35V
100µF
C30
AGND
RSC
TP21
LEB
TP27
PS
TP26
RT
TP25
SP
TP24
FAULT
TP23
HICC
TP22
VSENSE
TP20
Figure 5-2. TPS7H5001EVM-CVAL Schematic (Page 2)
www.ti.com Schematics
SLVUCD0 – FEBRUARY 2022
Submit Document Feedback
TPS7H500x-SP Evaluation Module User's Guide 13
Copyright © 2022 Texas Instruments Incorporated

1
3
5 6
4
2
7
9 10
8
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
41 42
J8
DNP
1 3 5
6
4
2
7 9
10
8
12 11
14 13
16 15 18 17 20 19 22 21
24 23
26 25 28 27 30 29 32 31
34 33
36 35 38 37 40 39
41
42
J10
DNP
1
3
5 6
4
2
7
9 10
8
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
41 42
J7
DNP
1 3 5
6
4
2
7 9
10
8
12 11
14 13
16 15 18 17 20 19 22 21
24 23
26 25 28 27 30 29 32 31
34 33
36 35 38 37 40 39
41
42
J9
DNP
DIO_6B
DIO_7B
PXIe-4112 (CH#1)
PXIe-4112 (CH#1) S+
PXIe-4112 (CH#1) S-
AGND
AGND
0
R109
0
R111
0
R108
DNP
0
R110
DNP
Bottom Side Pogos
PXIe-4139-1 F+
AGND
AGND EGND
PXIe-4139-1 S+
PXIe-4139-1 S-
PXIe-5162_CH0
PXIe-5162_CH1
PXIe-5162_CH2
PXIe-5162_CH3
PXIe-5110_CH0
PXIe-5110_CH1
PXIe-4145 (CH#0) F+
PXIe-4145 (CH#0) S+
PXIe-4145 (CH#0) S-
PXIe-4145 (CH#1) F+
PXIe-4145 (CH#1) S+
PXIe-4145 (CH#1) S-
1 3 5
6
4
2
7 9
10
8
1211
1413
1615 1817 2019 2221
2423
2625 2827 3029 3231
3433
3635 3837 4039
41
42
JJ10
DDDNNNPPP
Bottom Side Pogos
PXIe-4139-1 F+
AGND
AGND EGND
PXPP Ie-4XX 139-1 S+
PXPP Ie-4XX 139-1 S-
PXIe-5162_CH0
PXIe-5162_CH1
PXIe-5162_CH2
PXIe-5162_CH3
PXIe-5110_CH0
PXIe-5110_CH1
PXIe-4145 (CH#0) F+
PXPP Ie-4XX 145 (C45 H#HH 0) S+
PXPP Ie-4XX 145 (C45 H#HH 0) S-
PXIe-4145 (CH#1) F+
PXPP Ie-4XX 145 (C45 H#HH 1) S+
PXPP Ie-4XX 145 (C45 H#HH 1) S-
1
3
5 6
4
2
7
9 10
8
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
41 42
J8
DDDDNNNPPP
DIO_6B
DIO_7B
0
R109
0
R111
Left Side Pogos
1
3
5 6
4
2
7
9 10
8
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
41 42
J7
DDDDNNNPPP
0
R108
DDDDDDNNNNNNPPPPP
0
R110
DDDDDDNNNNNNPPPPP
Right Side Pogos
E36311A-1 (+6V)
DMM_Site1_1
DMM_Site1_2
DMM_Site1_3
AWG_CH1_to_SIte1
PXIe-5172-1_CH1_Site1
PXIe-5172-1_CH3_Site1
PXIe-5172-1_CH5_Site1
PXIe-5172-1_CH7_Site1
PXIe-5172-2_CH1_Site1
PXIe-5172-2_CH3_Site1
PXIe-5172-2_CH5_Site1
PXIe-5172-2_CH7_Site1
DMM_Site1_4
DMM_Site1_5
AWG_CH2_to_SIte1
PXIe-5172-1_CH0_Site1
PXIe-5172-1_CH2_Site1
PXIe-5172-1_CH4_Site1
PXIe-5172-1_CH6_Site1
PXIe-5172-2_CH0_Site1
PXIe-5172-2_CH2_Site1
PXIe-5172-2_CH4_Site1
PXIe-5172-2_CH6_Site1
1 3 5
6
4
2
7 9
10
8
1211
1413
1615 1817 2019 2221
2423
2625 2827 3029 3231
3433
3635 3837 4039
41
42
JJ9
DDDNNNNNPPP
PXIe-4112 (CH#1)
PXPP Ie-4XX 112 (C12 H#HH 1) S+
PXPP Ie-4XX 112 (C12 H#HH 1) S-
AGND
AGND
DMM_Site1_1
DMM_Site1_2
DMM_Site1_3
AWAA G_CH1_to__ SIte1
PXIe-5172-1_CH1_Site1
PXIe-5172-1_CH3_Site1
PXIe-5172-1_CH5_Site1
PXIe-5172-1_CH7_Site1
PXIe-5172-2_CH1_Site1
PXIe-5172-2_CH3_Site1
PXIe-5172-2_CH5_Site1
PXIe-5172-2_CH7_Site1
DMM_Site1_4
DMM_Site1_5
AWAA G_CH2_to__ SIte1
PXIe-5172-1_CH0_Site1
PXIe-5172-1_CH2_Site1
PXIe-5172-1_CH4_Site1
PXIe-5172-1_CH6_Site1
PXIe-5172-2_CH0_Site1
PXIe-5172-2_CH2_Site1
PXIe-5172-2_CH4_Site1
PXIe-5172-2_CH6_Site1
Upper Side Pogos
E36311A-1 (+25V)
PXIe-5922_CH0_Site1
PXIe-5922_CH1_Site1
PXIe-4113 (CH#1) F+
PXIe-4113 (CH#1) S+
PXIe-4113 (CH#1) S-
PGND
PGND AGND
EGND
PGND AGND
EGND
Local Star GND Connection
0
R112
DNP
0
R114
DNP
0
R113
DNP
0
R115
DNP
0
R117
DNP
0
R116
DNP
PXIe-4137 S-
PXIe-4137 S+
PXIe-4137 F+
Label Assembly Note
ZZ1
This Assembly Note is for PCB labels only
Assembly Note
ZZ2
These assemblies are ESD sensitive, ESD precautions shall be observed.
Assembly Note
ZZ3
These assemblies must be clean and free from flux a nd all contaminants. Use of no clean flux is not ac ceptable.
Assembly Note
ZZ4
These assemblies must comply with workmanship stand ards IPC-A-610 Class 2, unless otherwise specified.
LOGO
PCB
Texas Instruments
NA
A
PCB Number:
PCB Rev:
Size: 0.65" x 0.20 "
PCB Label
LBL1
THT-14-423-10
CE Mark
LOGO
PCB
FCC disclaimer
LOGO
PCB
WEEE logo
1
H1
NY PMS 440 0025 PH
1
H2
NY PMS 440 0025 PH
1
H3
NY PMS 440 0025 PH
1
H4
NY PMS 440 0025 PH
H5
1902C
H6
1902C
H7
1902C
H8
1902C
FID2
DNP
FID1
DNP
FID3
DNP
Figure 5-3. TPS7H5001EVM-CVAL Schematic (Page 3)
Schematics www.ti.com
14 TPS7H500x-SP Evaluation Module User's Guide SLVUCD0 – FEBRUARY 2022
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated

AGND AGND
SYNC
SYNC
TP13
AGND
VLDO TP14
AGND
135k
R31
AGND
1.00k
R14
10.0
R24
10.0
R26
20.0k
R15
49.9k
R39
1.00M
R35
30.0k
R40
49.9k
R30
49.9k
R29
10.0k
R9
10.0k
R10
4.70k
R41
5.90k
R27
3.90k
R25
470nF
C15
500pF
C10
20pF
C5
20pF
C17
1µF
C18
10nF
C16
191k
R33
VIN
VIN
TP7
VLDO
VIN
VLDO
0
R12
0
R11
PXIe-4145 (CH#0) F+
PXIe-4145 (CH#0) S+
PXIe-4145 (CH#0) S-
0
R16
AGND
AGND
AGND AGND
50V
1µF
C14
0
R4
PXIe-4112 (CH#1)
PXIe-4112 (CH#1) S+
PXIe-4112 (CH#1) S-
0
R1
100nF
25V
C9
REFCAP
REFCAP
REFCAP
TP10
OUTA OUTB
CS_ILIM
CS_ILIM
CS_ILIM
TP5
G
TP6
AGND
G
TP15 PXIe-4145 (CH#1) F+
PXIe-4145 (CH#1) S+
PXIe-4145 (CH#1) S-
0
R34
0
R37
100nF
25V
C19
SS TP11
1
2
I_VIN
J5
IVIN_P
IVIN_N
150uF
C1
AGND
0.1uF
C4
10uF
C3
10uF
C2
G
TP12
AGND
VLDO
0
R19
0
R22
1.00M
R5
AGND
OUTA OUTB
OUTA
OUTB
20pF
C6
1.00M
R6
AGND
20pF
C7
1.00M
R7
AGND
SRA SRB
20pF
C8
1.00M
R8
AGND
SRA
SRB
AGND_SENSE
AGND_SENSE
1
2 3 4
5
J1
AGND
OUTA 1
2 3 4
5
J2
AGND
OUTB 1
2 3 4
5
J3
AGND
1
2 3 4
5
J4
AGND
SRA SRB
OUTA
TP1
EN
TP8
SRA
TP3
OUTB
TP2
SRB
TP4
PWM's Output and Loading
REFCAP
CS_ILIM
0
R44
0
R13
0
R17
0
R18
0
R20
COMP
TP9
E36311A-1 (+6V)
10nF
C12
1000pF
C11
10.0k
R21
0
R28
0
R42
0
R38
DIO_6B
DIO_7B
COMP
EN
HICC
FAULT
SP
PS
RT
SYNC
LEB
RSC DCL
VSENSE
SS
PXIe-4113 (CH#1) S+ 0
R3
FAULT
0
R2
FAULT
PXIe-4113 (CH#1) S- 0
R43
VSENSE
COMP
1.0k
R36
470nF
C13
HICC
AGND
1
2
3
J6
AGND
DCL
0
R32
VLDO
PXIe-4137 S-
PXIe-4137 S+
PXIe-4137 F+ DCL
HICC
0
R23
0
R45
0
R47
0
R46
PXIe-4113 (CH#1) F+
0
R118
1
2
J11
ED120/2DS
TP28
AGND
TP29TP30TP31
VIN
9
COMP 22
CS_ILIM
16
DCL 7
EN
8
EP 23
FAULT
17
HICC
5
LEB
4
OUTA 10
PS
2
REFCAP
18
RSC
19
RT
1
SP
3
SRA 13
SS 20
SYNC
6VLDO 15
VSENSE 21
NC 11
NC 12
AVSS 14
TPS7H5002HFT/EM
U1
Figure 5-4. TPS7H5002EVM-CVAL Schematic (Page 1)
www.ti.com Schematics
SLVUCD0 – FEBRUARY 2022
Submit Document Feedback
TPS7H500x-SP Evaluation Module User's Guide 15
Copyright © 2022 Texas Instruments Incorporated

PXIe-5162_CH0
PXIe-5162_CH1
PXIe-5162_CH2
PXIe-5162_CH3
OUTA
OUTB
SRA
SRB
0
R48
VLDO
REFCAP
VIN
EN
HICC
FAULT
SP
RT
PS
SYNC
LEB
RSC
VLDO
COMP_BUFFER
VSENSE
SS_BUFFER
0
R60
0
R75
0
R54
0
R68
0
R78
0
R81
0
R84
0
R49
0
R55
0
R61
0
R69
0
R76
0
R79
0
R82
0
R85
0
R74
0
R77
0
R80
0
R83
PXIe-5110_CH0
PXIe-5110_CH1
0
R53
OUTA
SRA
0
R52
0
R59
OUTB
SRB
0
R58
DMM_Site1_1
DMM_Site1_2
DMM_Site1_3
AWG_CH1_to_SIte1
PXIe-5172-1_CH1_Site1
PXIe-5172-1_CH3_Site1
PXIe-5172-1_CH5_Site1
PXIe-5172-1_CH7_Site1
PXIe-5172-2_CH1_Site1
PXIe-5172-2_CH3_Site1
PXIe-5172-2_CH5_Site1
PXIe-5172-2_CH7_Site1
DMM_Site1_4
DMM_Site1_5
AWG_CH2_to_SIte1
PXIe-5172-1_CH0_Site1
PXIe-5172-1_CH2_Site1
PXIe-5172-1_CH4_Site1
PXIe-5172-1_CH6_Site1
PXIe-5172-2_CH0_Site1
PXIe-5172-2_CH2_Site1
PXIe-5172-2_CH4_Site1
PXIe-5172-2_CH6_Site1
1
2
3
4
5
OPA354AIDBVR
U5
100nF
25V
C26
0
R96
0
R86
0
R94
0
R97
4
1
2
SN74AHCT1G08DCKR
U2A
VCC
5GND 3
SN74AHCT1G08DCKR
U3B
4
1
2
SN74AHCT1G08DCKR
U3A
VCC
5GND 3
SN74AHCT1G08DCKR
U2B
AGND
AGND
AGND AGND
OUTA
SRA
OUTB
SRB
PXIe-5162_CH0
PXIe-5162_CH1
0
R63
0
R70
PXIe-5162_CH0
PXIe-5162_CH1
Cross Conduction T rigger
COMP COMP_BUFFER
AGND
AGND
COMP Buffer
PXIe-5110 (PWM Trigger Supported)
PXIe-5162 (HS Scope) or DPO7XXXX Series
PXIe-5172 (General Purpose Up to 100MHz) PXIe-5172 (General Purpose Up to 100MHz)
0
R57
OUTA
SRA
0
R51
0
R73
OUTB
SRB
0
R65
OUTA
OUTB
SRA
SRB
0
R50
0
R56
0
R64
0
R72
SYNC
0
R89
CS_ILIM
0
R92
External CLK Syncronization
0
R87
0
R88
0
R90
0
R91
0
R93
VLDO
REFCAP
VIN
COMP_BUFFER
DMM
PXIe-5922_CH0_Site1
PXIe-5922_CH1_Site1
1
2
3
4
5
OPA354AIDBVR
U6
100nF
25V
C34
0
R106
0
R104
0
R105
0
R107
SS SS_BUFFER
AGND
AGND
SS Buffer
SS_BUFFER
0
R102
0
R99
COMP_B_INTP17 COMP_B_OUT
TP16
100nF
25V
C20
1µF
50V
C21
1nF
50V
C22
1µF
50V
C24
1nF
50V
C25
100nF
25V
C23
1µF
50V
C28
1nF
50V
C29
100nF
25V
C27
1µF
50V
C36
1nF
50V
C37
100nF
25V
C35
100nF
25V
C39
AGND
100nF
25V
C38
100nF
25V
C32
100nF
25V
C33
AGND
SS_B_IN TP19 SS_B_OUT
TP18
SS_BUFFER
COMP_BUFFER
PXIe-5922 (High Presicion)
0
R62
0
R66
0
R67
0
R71
1 3
2
GND
10
R100
Heater
AGND
PXIe-4139-1 F+
PXIe-4139-1 S+ 0
R103
0
R101
PXIe-4139-1 S- 0
R98
IN
3OUT 2
1
TAB 4
GND
LM1117MPX-5.0
U4
E36311A-1 (+25V)
AGND
10V
47uF
C31
AGND
+5V
+5V
+5V
+5V
0
R95
E36311A-1 (+25V) +5V
LDO
35V
100µF
C30
AGND
RSC
TP21
LEB
TP27
PS
TP26
RT
TP25
SP
TP24
FAULT
TP23
HICC
TP22
VSENSE
TP20
Figure 5-5. TPS7H5002EVM-CVAL Scheamtic (Page 2)
Schematics www.ti.com
16 TPS7H500x-SP Evaluation Module User's Guide SLVUCD0 – FEBRUARY 2022
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated

1
3
5 6
4
2
7
9 10
8
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
41 42
J8
1 3 5
6 4 2
7 9
10
8
12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39
41
42
J10
1
3
5 6
4
2
7
9 10
8
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
41 42
J7
1 3 5
6 4 2
7 9
10
8
12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39
41
42
J9
DIO_6B
DIO_7B
PXIe-4112 (CH#1)
PXIe-4112 (CH#1) S+
PXIe-4112 (CH#1) S-
AGND
AGND
0
R109
0
R111
0
R108
0
R110
Bottom Side Pogos
PXIe-4139-1 F+
AGND
AGND EGND
PXIe-4139-1 S+
PXIe-4139-1 S-
PXIe-5162_CH0
PXIe-5162_CH1
PXIe-5162_CH2
PXIe-5162_CH3
PXIe-5110_CH0
PXIe-5110_CH1
PXIe-4145 (CH#0) F+
PXIe-4145 (CH#0) S+
PXIe-4145 (CH#0) S-
PXIe-4145 (CH#1) F+
PXIe-4145 (CH#1) S+
PXIe-4145 (CH#1) S-
Left Side Pogos Right Side Pogos
E36311A-1 (+6V)
DMM_Site1_1
DMM_Site1_2
DMM_Site1_3
AWG_CH1_to_SIte1
PXIe-5172-1_CH1_Site1
PXIe-5172-1_CH3_Site1
PXIe-5172-1_CH5_Site1
PXIe-5172-1_CH7_Site1
PXIe-5172-2_CH1_Site1
PXIe-5172-2_CH3_Site1
PXIe-5172-2_CH5_Site1
PXIe-5172-2_CH7_Site1
DMM_Site1_4
DMM_Site1_5
AWG_CH2_to_SIte1
PXIe-5172-1_CH0_Site1
PXIe-5172-1_CH2_Site1
PXIe-5172-1_CH4_Site1
PXIe-5172-1_CH6_Site1
PXIe-5172-2_CH0_Site1
PXIe-5172-2_CH2_Site1
PXIe-5172-2_CH4_Site1
PXIe-5172-2_CH6_Site1
Upper Side Pogos
E36311A-1 (+25V)
PXIe-5922_CH0_Site1
PXIe-5922_CH1_Site1
PXIe-4113 (CH#1) F+
PXIe-4113 (CH#1) S+
PXIe-4113 (CH#1) S-
PGND
PGND AGND
EGND
Loca l Star GND Connec tion
0
R112
0
R114
0
R113
0
R115
0
R117
0
R116
PXIe-4137 S-
PXIe-4137 S+
PXIe-4137 F+
Label Assembly Note
ZZ1
This Assembly Note is for PCB labels only
Assembly Note
ZZ2
These assemblies are ESD sensitive, ESD precautions shall be observed.
Assembly Note
ZZ3
These assemblies must be clean and free from flux and all contaminants. Use of no clean flux is not acceptable.
Assembly Note
ZZ4
These assemblies must comply with workmanship standards IPC-A-610 Class 2, unless otherwise specified.
LOGO
PCB
Texas Instruments
NA
B
PCB Number:
PCB Rev:
Size: 0.65" x 0.20 "
PCB Label
LBL1
THT-14-423-10
CE Mark
LOGO
PCB
FCC disclaimer
LOGO
PCB
WEEE logo
1
H1
NY PMS 440 0025 PH
1
H2
NY PMS 440 0025 PH
1
H3
NY PMS 440 0025 PH
1
H4
NY PMS 440 0025 PH
H5
1902C
H6
1902C
H7
1902C
H8
1902C
FID2FID1 FID3
Figure 5-6. TPS7H5002EVM-CVAL Schematic (Page 3)
www.ti.com Schematics
SLVUCD0 – FEBRUARY 2022
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TPS7H500x-SP Evaluation Module User's Guide 17
Copyright © 2022 Texas Instruments Incorporated

AGND AGND
SYNC
SYNC
TP13
AGND
VLDO TP14
AGND
135k
R31
AGND
1.00k
R14
10.0
R24
10.0
R26
20.0k
R15
49.9k
R39
1.00M
R35
30.0k
R40
49.9k
R30
49.9k
R29
10.0k
R9
10.0k
R10
4.70k
R41
5.90k
R27
3.90k
R25
470nF
C15
500pF
C10
20pF
C5
20pF
C17
1µF
C18
10nF
C16
191k
R33
VIN
VIN
TP7
VLDO
VIN
VLDO
0
R12
0
R11
PXIe-4145 (CH#0) F+
PXIe-4145 (CH#0) S+
PXIe-4145 (CH#0) S-
0
R16
AGND
AGND
AGND AGND
50V
1µF
C14
0
R4
PXIe-4112 (CH#1)
PXIe-4112 (CH#1) S+
PXIe-4112 (CH#1) S-
0
R1
100nF
25V
C9
REFCAP
REFCAP
REFCAP
TP10
OUTA OUTB
CS_ILIM
CS_ILIM
CS_ILIM
TP5
G
TP6
AGND
G
TP15 PXIe-4145 (CH#1) F+
PXIe-4145 (CH#1) S+
PXIe-4145 (CH#1) S-
0
R34
0
R37
100nF
25V
C19
SS TP11
1
2
I_VIN
J5
IVIN_P
IVIN_N
150uF
C1
AGND
0.1uF
C4
10uF
C3
10uF
C2
G
TP12
AGND
VLDO
0
R19
0
R22
1.00M
R5
AGND
OUTA OUTB
OUTA
OUTB
20pF
C6
1.00M
R6
AGND
20pF
C7
1.00M
R7
AGND
SRA SRB
20pF
C8
1.00M
R8
AGND
SRA
SRB
AGND_SENSE
AGND_SENSE
1
2 3 4
5
J1
AGND
OUTA 1
2 3 4
5
J2
AGND
OUTB 1
2 3 4
5
J3
AGND
1
2 3 4
5
J4
AGND
SRA SRB
OUTA
TP1
EN
TP8
SRA
TP3
OUTB
TP2
SRB
TP4
PWM's Output and Loading
REFCAP
CS_ILIM
0
R44
0
R13
0
R17
0
R18
0
R20
COMP
TP9
E36311A-1 (+6V)
10nF
C12
1000pF
C11
10.0k
R21
0
R28
0
R42
0
R38
DIO_6B
DIO_7B
COMP
EN
HICC
FAULT
SP
PS
RT
SYNC
LEB
RSC DCL
VSENSE
SS
PXIe-4113 (CH#1) S+ 0
R3
FAULT
0
R2
FAULT
PXIe-4113 (CH#1) S- 0
R43
VSENSE
COMP
1.0k
R36
470nF
C13
HICC
AGND
1
2
3
J6
AGND
DCL
0
R32
VLDO
PXIe-4137 S-
PXIe-4137 S+
PXIe-4137 F+ DCL
HICC
0
R23
0
R45
R47
0
R46
PXIe-4113 (CH#1) F+
0
R118
1
2
J11
ED120/2DS
TP28
AGND
TP29TP30TP31
VIN
9
COMP 22
CS_ILIM
16
DCL 7
EN
8
EP 23
FAULT
17
HICC
5
NC
4
OUTA 10
NC
2
REFCAP
18
RSC
19
RT
1
NC
3
SRA 13
SS 20
SYNC
6VLDO 15
VSENSE 21
NC 11
NC 12
AVSS 14
TPS7H5003HFT/EM
U1
Figure 5-7. TPS7H5003EVM-CVAL Schematic (Page 1)
Schematics www.ti.com
18 TPS7H500x-SP Evaluation Module User's Guide SLVUCD0 – FEBRUARY 2022
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated

PXIe-5162_CH0
PXIe-5162_CH1
PXIe-5162_CH2
PXIe-5162_CH3
OUTA
OUTB
SRA
SRB
0
R48
VLDO
REFCAP
VIN
EN
HICC
FAULT
SP
RT
PS
SYNC
LEB
RSC
VLDO
COMP_BUFFER
VSENSE
SS_BUFFER
0
R60
0
R75
0
R54
0
R68
0
R78
0
R81
0
R84
0
R49
0
R55
0
R61
0
R69
0
R76
0
R79
0
R82
0
R85
0
R74
0
R77
0
R80
0
R83
PXIe-5110_CH0
PXIe-5110_CH1
0
R53
OUTA
SRA
0
R52
0
R59
OUTB
SRB
0
R58
DMM_Site1_1
DMM_Site1_2
DMM_Site1_3
AWG_CH1_to_SIte1
PXIe-5172-1_CH1_Site1
PXIe-5172-1_CH3_Site1
PXIe-5172-1_CH5_Site1
PXIe-5172-1_CH7_Site1
PXIe-5172-2_CH1_Site1
PXIe-5172-2_CH3_Site1
PXIe-5172-2_CH5_Site1
PXIe-5172-2_CH7_Site1
DMM_Site1_4
DMM_Site1_5
AWG_CH2_to_SIte1
PXIe-5172-1_CH0_Site1
PXIe-5172-1_CH2_Site1
PXIe-5172-1_CH4_Site1
PXIe-5172-1_CH6_Site1
PXIe-5172-2_CH0_Site1
PXIe-5172-2_CH2_Site1
PXIe-5172-2_CH4_Site1
PXIe-5172-2_CH6_Site1
1
2
3
4
5
OPA354AIDBVR
U5
100nF
25V
C26
0
R96
0
R86
0
R94
0
R97
4
1
2
SN74AHCT1G08DCKR
U2A
VCC
5GND 3
SN74AHCT1G08DCKR
U3B
4
1
2
SN74AHCT1G08DCKR
U3A
VCC
5GND 3
SN74AHCT1G08DCKR
U2B
AGND
AGND
AGND AGND
OUTA
SRA
OUTB
SRB
PXIe-5162_CH0
PXIe-5162_CH1
0
R63
0
R70
PXIe-5162_CH0
PXIe-5162_CH1
Cross Conduction T rigger
COMP COMP_BUFFER
AGND
AGND
COMP Buffer
PXIe-5110 (PWM Trigger Supported)
PXIe-5162 (HS Scope) or DPO7XXXX Series
PXIe-5172 (General Purpose Up to 100MHz) PXIe-5172 (General Purpose Up to 100MHz)
0
R57
OUTA
SRA
0
R51
0
R73
OUTB
SRB
0
R65
OUTA
OUTB
SRA
SRB
0
R50
0
R56
0
R64
0
R72
SYNC
0
R89
CS_ILIM
0
R92
External CLK Syncronization
0
R87
0
R88
0
R90
0
R91
0
R93
VLDO
REFCAP
VIN
COMP_BUFFER
DMM
PXIe-5922_CH0_Site1
PXIe-5922_CH1_Site1
1
2
3
4
5
OPA354AIDBVR
U6
100nF
25V
C34
0
R106
0
R104
0
R105
0
R107
SS SS_BUFFER
AGND
AGND
SS Buffer
SS_BUFFER
0
R102
0
R99
COMP_B_INTP17 COMP_B_OUT
TP16
100nF
25V
C20
1µF
50V
C21
1nF
50V
C22
1µF
50V
C24
1nF
50V
C25
100nF
25V
C23
1µF
50V
C28
1nF
50V
C29
100nF
25V
C27
1µF
50V
C36
1nF
50V
C37
100nF
25V
C35
100nF
25V
C39
AGND
100nF
25V
C38
100nF
25V
C32
100nF
25V
C33
AGND
SS_B_IN TP19 SS_B_OUT
TP18
SS_BUFFER
COMP_BUFFER
PXIe-5922 (High Presicion)
0
R62
0
R66
0
R67
0
R71
1 3
2
GND
10
R100
Heater
AGND
PXIe-4139-1 F+
PXIe-4139-1 S+ 0
R103
0
R101
PXIe-4139-1 S- 0
R98
IN
3OUT 2
1
TAB 4
GND
LM1117MPX-5.0
U4
E36311A-1 (+25V)
AGND
10V
47uF
C31
AGND
+5V
+5V
+5V
+5V
0
R95
E36311A-1 (+25V) +5V
LDO
35V
100µF
C30
AGND
RSC
TP21
LEB
TP27
PS
TP26
RT
TP25
SP
TP24
FAULT
TP23
HICC
TP22
VSENSE
TP20
Figure 5-8. TPS7H5003EVM-CVAL Schematic (Page 2)
www.ti.com Schematics
SLVUCD0 – FEBRUARY 2022
Submit Document Feedback
TPS7H500x-SP Evaluation Module User's Guide 19
Copyright © 2022 Texas Instruments Incorporated

1
3
5 6
4
2
7
9 10
8
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
41 42
J8
1 3 5
6 4 2
7 9
10
8
12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39
41
42
J10
1
3
5 6
4
2
7
9 10
8
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
41 42
J7
1 3 5
6 4 2
7 9
10
8
12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39
41
42
J9
DIO_6B
DIO_7B
PXIe-4112 (CH#1)
PXIe-4112 (CH#1) S+
PXIe-4112 (CH#1) S-
AGND
AGND
0
R109
0
R111
0
R108
0
R110
Bottom Side Pogos
PXIe-4139-1 F+
AGND
AGND EGND
PXIe-4139-1 S+
PXIe-4139-1 S-
PXIe-5162_CH0
PXIe-5162_CH1
PXIe-5162_CH2
PXIe-5162_CH3
PXIe-5110_CH0
PXIe-5110_CH1
PXIe-4145 (CH#0) F+
PXIe-4145 (CH#0) S+
PXIe-4145 (CH#0) S-
PXIe-4145 (CH#1) F+
PXIe-4145 (CH#1) S+
PXIe-4145 (CH#1) S-
Left Side Pogos Right Side Pogos
E36311A-1 (+6V)
DMM_Site1_1
DMM_Site1_2
DMM_Site1_3
AWG_CH1_to_SIte1
PXIe-5172-1_CH1_Site1
PXIe-5172-1_CH3_Site1
PXIe-5172-1_CH5_Site1
PXIe-5172-1_CH7_Site1
PXIe-5172-2_CH1_Site1
PXIe-5172-2_CH3_Site1
PXIe-5172-2_CH5_Site1
PXIe-5172-2_CH7_Site1
DMM_Site1_4
DMM_Site1_5
AWG_CH2_to_SIte1
PXIe-5172-1_CH0_Site1
PXIe-5172-1_CH2_Site1
PXIe-5172-1_CH4_Site1
PXIe-5172-1_CH6_Site1
PXIe-5172-2_CH0_Site1
PXIe-5172-2_CH2_Site1
PXIe-5172-2_CH4_Site1
PXIe-5172-2_CH6_Site1
Upper Side Pogos
E36311A-1 (+25V)
PXIe-5922_CH0_Site1
PXIe-5922_CH1_Site1
PXIe-4113 (CH#1) F+
PXIe-4113 (CH#1) S+
PXIe-4113 (CH#1) S-
PGND
PGND AGND
EGND
Loca l Star GND Connec tion
0
R112
0
R114
0
R113
0
R115
0
R117
0
R116
PXIe-4137 S-
PXIe-4137 S+
PXIe-4137 F+
Label Assembly Note
ZZ1
This Assembly Note is for PCB labels only
Assembly Note
ZZ2
These assemblies are ESD sensitive, ESD precautions shall be observed.
Assembly Note
ZZ3
These assemblies must be clean and free from flux and all contaminants. Use of no clean flux is not acceptable.
Assembly Note
ZZ4
These assemblies must comply with workmanship standards IPC-A-610 Class 2, unless otherwise specified.
LOGO
PCB
Texas Instruments
NA
A
PCB Number:
PCB Rev:
Size: 0.65" x 0.20 "
PCB Label
LBL1
THT-14-423-10
CE Mark
LOGO
PCB
FCC disclaimer
LOGO
PCB
WEEE logo
1
H1
NY PMS 440 0025 PH
1
H2
NY PMS 440 0025 PH
1
H3
NY PMS 440 0025 PH
1
H4
NY PMS 440 0025 PH
H5
1902C
H6
1902C
H7
1902C
H8
1902C
FID2FID1 FID3
Figure 5-9. TPS7H5003EVM-CVAL Schematic (Page 3)
Schematics www.ti.com
20 TPS7H500x-SP Evaluation Module User's Guide SLVUCD0 – FEBRUARY 2022
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated