Texas Instruments TUSB7340 User manual

TUSB7320/TUSB7340 EVM User's Guide
User's Guide
Literature Number: SLLU146B
May 2011–Revised August 2012

Contents
1 Introduction ........................................................................................................................ 5
2 EVM Board ......................................................................................................................... 6
1 TUSB7320 and TUSB7340 DEMO Boards ............................................................................... 6
2 Hardware Setup .................................................................................................................. 8
2.1 Headers ................................................................................................................... 8
2.2 VBUS ...................................................................................................................... 8
2.3 PCI Express Slot Options .............................................................................................. 8
3 Bringup .............................................................................................................................. 9
4 WAKE Testing Setup .......................................................................................................... 10
5 SMI Support ...................................................................................................................... 11
6 Schematics ....................................................................................................................... 12
1 TUSB7320 DEMO EVM REVB Schematics ............................................................................. 13
2 TUSB7340 DEMO EVM REVB Schematics ............................................................................. 17
Appendix A Bill of Materials ........................................................................................................ 21
2Table of Contents SLLU146B–May 2011–Revised August 2012
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List of Figures
1 TUSB7320 DEMO EVM REVB............................................................................................ 6
2 TUSB7340 DEMO EVM REVB............................................................................................ 7
3 SMI via Location for TUSB7340 DEMO EVM REVB ................................................................. 11
List of Tables
1 TUSB7320 DEMO REVB BOM ......................................................................................... 21
2 TUSB7340 DEMO REVB BOM ......................................................................................... 22
3
SLLU146B–May 2011–Revised August 2012 List of Figures
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www.ti.com
This guide is intended to describe the necessary information needed to operate either the TUSB7320
DEMO EVM REVB or TUSB7340 DEMO EVM REVB boards. In this document you will find how to setup
and use the EVM boards. The schematics and bill of materials are also detailed at the end of the
document.
4List of Tables SLLU146B–May 2011–Revised August 2012
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SLLU146B–May 2011–Revised August 2012
Introduction
The TUSB7340 is a USB 3.0 xHCI 0.96 compliant host controller that supports up to four downstream
ports. The TUSB7320 supports up to two downstream ports. The TUSB73x0 interfaces to the host system
via a PCIe x1 Gen 2 interface and provides SuperSpeed, High-speed, Full-speed, or Low-speed
connections on the downstream USB ports.
5
SLLU146B–May 2011–Revised August 2012 Introduction
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J1
J5
PORT1
PORT2 J2
U1
J26J27
J22
J40
SLLU146B–May 2011–Revised August 2012
EVM Board
1 TUSB7320 and TUSB7340 DEMO Boards
The TUSB7320 and TUSB7340 DEMO boards are both PCI Express X1 Standard Height cards. The
dimensions of both boards are 4.376 inches by 2.571 inches. The two figures below depict how the boards
look.
Figure 1. TUSB7320 DEMO EVM REVB
6EVM Board SLLU146B–May 2011–Revised August 2012
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J1
J5
PORT3
PORT1
PORT2
PORT4
J2
J3
J4
U1
J26J27
J22
J40
www.ti.com TUSB7320 and TUSB7340 DEMO Boards
Figure 2. TUSB7340 DEMO EVM REVB
7
SLLU146B–May 2011–Revised August 2012 EVM Board
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Hardware Setup www.ti.com
2 Hardware Setup
2.1 Headers
The EVM boards are populated with three headers: J22, J26, and J40.
J22 header is used to change the state of AUX_DET signal to the TUSB73XX. By default, this header is
not shorted and therefore AUX_DET will be high. If a jumper shunt is placed over J22, the AUX_DET will
be low.
The J26 header is used to route 5 V from the IDE Power Connector (J5) to the Texas Instruments
TPS2560 USB power switch. This header should always have a Jumper Shunt populated. For more
information on the Texas Instruments TPS2560, please visit www.ti.com.
J40 header is used to select the 3.3-V power source for the TUSB73X0. By default, a Jumper Shunt
should be populated across pins 1 and 2 of J40. When in this position, the 3.3-V power from the PCI
Express slot is routed to the TUSB73X0. If the Jumper Shunt is moved to pins 2 and 3, then the 3.3-V
VAUX power from the PCI Express slot is routed to the TUSB73X0. The Jumper Shunt should only be
moved to positions 2 and 3 if wake testing is required. Otherwise the jumper should be left in the default
position of 1 and 2.
NOTE: The 3.3-V VAUX power supply has a limited current capability. According to the PCI Express
Electromechanical Spec, the 3.3-V VAUX will have a maximum current of 375 mA. Because
of the limited current of 3.3-V VAUX, it is recommended to plug only one device into the
TUSB73X0. If the Jumper Shunt is left on pins 1 and 2 of J40, this current limitation does not
exist and therefore all ports of the TUSB73X0 can be used.
2.2 VBUS
VBUS for all of the USB ports comes from the IDE Power Connector (J5).
2.3 PCI Express Slot Options
Because the TUSB73X0 EVM boards are PCI Express X1, they can be used in any PCI Express Slot
(X1, X4, X8, or X16) on a typical motherboard. The boards can be used in either a PCI Express Gen1
(2.5 Gbps) or Gen2 (5 Gbps) slot. Because of the speed of USB3 (5 Gbps), if used in a PCI Express
Gen1 slot, the performance of the TUSB7320 or TUSB7340 will be negatively impacted. For this reason, it
is recommended to always insert the EVM board into a PCI Express Gen2 slot.
8EVM Board SLLU146B–May 2011–Revised August 2012
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SLLU146B–May 2011–Revised August 2012
Bringup
Below are the steps to bring up the EVM board in a typical system:
1. Remove the power plug from the PC power supply.
2. Make sure the Jumper Shunts are populated on J26 and J40.
3. Insert the EVM board into a PCI Express slot. It is recommended to use a PCI Express Gen2 slot if
one is available.
4. Insert an IDE Power Connector into J5 of the EVM board.
5. Insert the power plug into the PC power supply.
6. Turn the PC on. Once the PC is turned on, all of the green LEDs should be ON. If LED D5 is not
active, please check to make sure the jumper shunt on J40 is populated. If none of the green LEDs
(D1 thru D4) for each USB Port are active, please check to make sure the Jumper Shunt on J26 is
populated and an IDE Power connector is plugged into J5.
7. Once the PC has booted into Windows 7, you will need to install the TI xHCI driver. If the driver has
already been installed on your PC, then you can proceed step 8. Otherwise, you will need to install the
xHCI driver by running the TI xHCI driver setup utility.
8. You can now insert devices into the USB ports.
9
SLLU146B–May 2011–Revised August 2012 Bringup
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SLLU146B–May 2011–Revised August 2012
WAKE Testing Setup
The EVM board can be used to test the WAKE functionality of the TUSB73X0. By default, the EVM is not
configured to support wake testing. Please configure the EVM according to the following if WAKE is
required:
1. Move the Jumper Shunt on J40 to pins 2 and 3.
2. Make sure there is no Jumper Shunt on J22.
3. Use a dedicated 5-V power supply for VBUS. Do NOT use the IDE Power connector provided from the
system power supply. The reason for not using the IDE power from system power supply is when the
system is put in a sleep or hibernate state, the power on the IDE Power connector will be turned off.
NOTE: For some motherboards, WAKE from a PCIe slot is not supported or is only supported on
PCIE X1 slots. Please make sure to use a motherboard that supports WAKE from any PCIe
slot.
10 WAKE Testing Setup SLLU146B–May 2011–Revised August 2012
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SLLU146B–May 2011–Revised August 2012
SMI Support
The SMI pin from the TUSB7320 is brought out to a header labeled SMI. This header is located to the left
of J22.
The SMI pin from the TUSB7340 is brought out to a via located on the bottom of board near U1. The via is
located between C10 and C34 and just above C31.
Figure 3. SMI via Location for TUSB7340 DEMO EVM REVB
11
SLLU146B–May 2011–Revised August 2012 SMI Support
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SLLU146B–May 2011–Revised August 2012
Schematics
The following pages contain schematics for the TUSB7320 and TUSB7340.
12 Schematics SLLU146B–May 2011–Revised August 2012
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EPROM
I2C
DP/DM
VIA AND TRACE REQUIREMENTS:
- MIN VIA PAD SIZE 20mils
- MIN spacing between trace and pad is 5mils
- MIN spacing between VIA and pad is 5mils
- MIN width of trace is 4mils
IMPEDANCE REQUIREMENTS:
- USB_DP/M must be 90-ohm differential (+/-15%)
- USB_SSTXP/N must be 90-ohms differential (+/-15%)
- USB_SSRXP/N must be 90-ohms differential (+/-15%)
- PCIE_TXP/N must be 100-ohms differential (+/-10%)
- PCIE_RXP/N must be 100-ohms differential (+/-10%)
- PCIE_REFCLKP/N must be 100-ohms differential (+/-10%)
LENGTH MATCHING REQUIREMENTS:
- USB_DP/M within 25mils.
- USB_SSTXP/N within 5mils
- USB_SSRXP/N within 5mils
- PCIE_TXP/N within 5mils
- PCIE_RXP/N within 5mils
- PCIE_REFCLKP/N within 25mils.
(U1)
TUSB7320
RX/TX USB3
TYPEA
DOWNSTREAM
PORT1
DOWNSTREAM
PORT2
USB3
TYPEA
RX/TX
DP/DM
RX/TX
PCIE
CONNECTOR
Sheet of
SIZE
SCALE: NONE
DWG NO:
TUSB7320 DEMO REVB
Tuesday, March 08, 2011
B
1 4
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1 TUSB7320 DEMO EVM REVB Schematics
13
SLLU146B–May 2011–Revised August 2012 Schematics
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VSS_OSC
R3
NOPOP
0402
5%
BOARD_3P3V
R4
NOPOP
0402
5%
GPIO0
SCL
C4
22uF
C24
22uF
C5
0.01uF
C6
0.1uF
R11
4.7K
0402
5%
GPIO1
C25
0.1uF
R9
NOPOP
C26
0.1uF
BOARD_3P3V
C27
0.1uF
GPIO2
BOARD_1P1V
AUX_DET
C1
0.1uF
C28
0.1uF
R38
0
C29
0.1uF
VDDA3P3V
TUSB7320
TUSB7320_REVA
U1
CLKREQ#
B36
FREQSEL
B14
GPIO0
A49
GPIO1
B46
GPIO2
B47
GPIO3
B48
GRST#
A15
JTAG_RST#
B32
JTAG_TCK
A32
JTAG_TDI
A35
JTAG_TDO
B31
JTAG_TMS
B30
PCIE_REFCLKN
B41
PCIE_REFCLKP
A45
PCIE_RXN
A42
PCIE_RXP
B39
PCIE_TXN
A41
PCIE_TXP
B38
PERST#
A40
SCL
B2
SDA
A2
SMI
B3
WAKE#
B35
OVERCUR1# A36
OVERCUR2# A37
NC18 B43
NC26 B45
PWRON1# B33
PWRON2# B34
NC17 A46
NC25 A48
R1EXT
A24
R1EXTRTN
B23
USB_DM_DN1 B18
USB_DM_DN2 A13
NC11 A27
NC19 A5
USB_DP_DN1 A20
USB_DP_DN2 B12
NC12 B25
NC20 B5
USB_SSRXN_DN1 B16
USB_SSRXP_DN2 B9
NC13 A29
NC21 A7
USB_SSRXP_DN1 A18
USB_SSRXN_DN2 A10
NC14 B27
NC22 B6
USB_SSTXN_DN1 B15
USB_SSTXN_DN2 B10
NC15 A30
NC23 A8
USB_SSTXP_DN1 A17
USB_SSTXP_DN2 A11
NC16 B28
NC24 B7
VSS_OSC
B21
XI
A23
XO
A22
AUX_DET A52
VDDA_3P3 A25
VDD11 A1 VDD11 A12 VDD11 A16 VDD11 A28 VDD11 A31 VDD11 A33 VDD11 A38 VDD11 A4
NC6
A43
VDD11 A50 VDD11 A6 VDD11 A9 VDD11 B1 VDD11 B17 VDD11 B19 VDD11 B24 VDD11 B37 VDD11 B40 VDD11 B42 VDD11 B44 VDD33 A3 VDD33 A34 VDD33 A39 VDD33 A47 VDD33 A51
VDDA_3P3 A19 VDDA_3P3 A21 VDDA_3P3 A44 VDDA_3P3 B11 VDDA_3P3 B22
NC28
B26
NC27
B4
NC1
A14
NC2
A26
NC3
B13
NC4
B29
VSS
B20
VSS
A53
NC7
C1
NC8
C2
NC9
C3
NC10
C4
R10 9.09K 1%
PLACE CLOSE TO U1
R39
0
BOARD_3P3V
GPIO3
USB_SSTXN_DN2 pg3
USB_SSTXP_DN2 pg3
USB_DM_DN2 pg3
USB_DP_DN2 pg3
PWRON2Z pg3
OVERCUR2Z pg3
USB_SSRXN_DN2 pg3
USB_SSRXP_DN2 pg3
USB_SSRXP_DN1 pg3
USB_SSRXN_DN1 pg3
USB_DP_DN1 pg3
USB_DM_DN1 pg3
OVERCUR1Z pg3
PWRON1Z pg3
USB_SSTXP_DN1 pg3
USB_SSTXN_DN1 pg3
C32
0.1uF
C34
0.1uF
C35
0.1uF
C33
0.01uF
C36
0.01uF
C37
0.1uF
C30
0.01uF
C31
0.1uF
BOARD_3P3V
GPIO0
FB1
220 @ 100MHZ
BOARD_3P3V
VDDA3P3V
GPIO1
FREQSEL
GPIO2
GPIO3
C11
0.1uF
FREQSEL CLOCK
0 48MHz
1 PLL_FREQ_SEL field in the
USB Control Register
C8
0.1uF
C7
0.01uF
POPULATE PULLDOWN IF I2C EEPROM
NOT USED AND DO NOT POPULATE
PULLUP.
C14
0.1uF
C17
0.1uF
C15
0.01uF
C16
0.1uF
GRSTZpg4
PCIE_RXNpg3
PCIE_REFCLKPpg3
PCIE_REFCLKNpg3
PERSTZpg3
PCIE_TXPpg3
PCIE_TXNpg3
PCIE_RXPpg3
WAKEZpg3
SDA
C19
0.1uF
C20
0.1uF
C18
0.01uF
C9
0.1uF
C23
0.1uF
C21
0.01uF
C22
0.1uF
R2
10K
0402
5%
J22
HDR2X1 M .1
12
BOARD_3P3V
JUMPER J22 FOR NO WAKE SUPPORT
POPULATE R2 FOR WAKE SUPPORT.
BOARD_1P1V
C2
18pF
XI
XO
C3
18pF
Y1
ECS-48MHZ
R5
NOPOP
0402
5%
R12 1M
R6
NOPOP
0402
5%
C12
0.01uF
C13
0.1uF
R7
NOPOP
0402
5%
R8
NOPOP
0402
5%
R1EXT
U2
24LC01_NF
A0
1
A1
2
A2
3
GND
4SDA 5
SCL 6
WP 7
VCC 8
C10
0.01uF
R1EXTRTN
FREQSEL
Sheet of
SIZE
SCALE: NONE
DWG NO:
TUSB7320
Tuesday, March 22, 2011
C
2 4
BOARD_3P3V
R1
NOPOP
0402
5%
NC5
B8
TUSB7320 DEMO EVM REVB Schematics www.ti.com
14 Schematics SLLU146B–May 2011–Revised August 2012
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+C44
150uF
R19
30.9K
0402
1%
C43
0.1uF
ILIM1
C38
0.1uF
BOARD_5V
BOARD_3P3V
R13
10K
0402
5%
DS1_VBUS
U3
TPS2560DRC
GND
1
IN
2
IN
3
EN1
4
EN2
5
FAULT2Z 6
ILIM 7
OUT2 8
OUT1 9
FAULT1Z 10
PAD
11
WAKEZ_R
C64
22uF
U26
TPD2EUSB30_NF
D+
1
D-
2
GND 3
U27
TPD2EUSB30_NF
D+
1
D-
2
GND 3
C45
0.1uF +C46
150uF
PCIE_3P3V
J1
USB3_TYPEA_CONNECTER
VBUS 1
DM 2
DP 3
GND 4
SSRXN 5
SSRXP 6
GND 7
SSTXN 8
SSTXP 9
SHIELD0 10
SHIELD1 11
PCIE_3P3V
C62
NOPOP
J4
USB3_TYPEA_CONNECTER
VBUS 1
DM 2
DP 3
GND 4
SSRXN 5
SSRXP 6
GND 7
SSTXN 8
SSTXP 9
SHIELD0 10
SHIELD1 11
DS2_VBUS
USB_SSRXN_DN1
L4
TDK_TCE_1210
1
2 3
4
IND_USB_DP_DN1
USB_SSRXP_DN1
DS1_VBUS
C40 0.1uF
IND_USB_DM_DN1
C39 0.1uF
L2
TDK_TCE_1210
1
2 3
4
R17
1M
0402
CAPDSTXN1
CAPDSTXP1
C41
0.1uF
C42
0.001uF
USB_SSRXP_DN1 pg2
USB_SSRXN_DN1 pg2
USB_DM_DN1 pg2
USB_SSTXP_DN1 pg2
USB_DP_DN1 pg2
DS_SHLD
USB_SSTXN_DN1 pg2
IND_DS_TXN1
IND_DS_TXP1
VAUX
C63
NOPOP
DOWNSTREAM
PORT1
PCIE_RXN pg2
PCIE_RXP pg2
PCIE_REFCLKP pg2
PCIE_REFCLKN pg2
WAKEZpg2
Side B
Component Side
Side A
Solder Side
Key
P1
PCI Express x1 Edge Connector
12V1
B1
12V2
B2
12V5
B3
GND1
B4
SMCLK
B5
SMDAT
B6
GND2
B7
3.3V
B8
J_TRST#
B9
3.3Vaux
B10
WAKE#
B11
RSVD2
B12
GND3
B13
PETp0
B14
PETn0
B15
GND4
B16
PRSNT2#
B17
GND5
B18
PRSNT1# A1
12V3 A2
12V4 A3
GND9 A4
J_TCK A5
J_TDI A6
J_TDO A7
J_TMS A8
3.3V1 A9
3.3V2 A10
PERST# A11
GND8 A12
REFCLK+ A13
REFCLK- A14
GND7 A15
PERp0 A16
PERn0 A17
GND6 A18
PERSTZ pg2
PCIE_TXP
pg2
PCIE_TXN
pg2
C68 0.1uF
C67 0.1uF
CAP_US_TXN
PCIE_PRSNTZ
CAP_US_TXP
PCIE_TDITDO
USB_SSTXN_DN2 pg2
USB_SSTXP_DN2 pg2
IND_DS_TXN2
L7
TDK_TCE_1210
1
2 3
4
L5
TDK_TCE_1210
1
2 3
4
CAPDSTXN2
CAPDSTXP2
R18
NOPOP
USB_SSRXP_DN2
USB_SSRXN_DN2
DS2_VBUS
IND_USB_DP_DN2
IND_USB_DM_DN2
USB_DP_DN2 pg2
USB_DM_DN2 pg2
IND_DS_TXP2
C49
0.1uF
USB_SSRXN_DN2 pg2
R21
1M
0402
C50
0.001uF
USB_SSRXP_DN2 pg2
DS_SHLDDS_SHLD
C48 0.1uF
C47 0.1uF
R20
NOPOP
PWRON2Zpg2
BOARD_12V
PWRON1Zpg2
R15
330
0402
5%
LEDDS1
D1
LED Green 0805
DOWNSTREAM
PORT2
R14
10K
0402
5%
MH1
PLATED_MH
1
MH2
PLATED_MH
1
OVERCUR1Z pg2
J40
HDR1x3
1
2
3
BOARD_3P3V
JUMPER BETWEEN 2 AND
3 FOR WAKE TESTING.
JUMPER BETWEEN 1 AND
2 FOR NORMAL
OPERATION.
C79
1000pF
+C80
NOPOP
PCIE CEM SPEC MAX VALUES:
PCIE_3P3V: 3 AMPS.
VAUX: 375mA
Sheet of
SIZE
SCALE: NONE
DWG NO:
USB3 AND PCIE CONNECTORS
Monday, March 21, 2011
C
3 4
OVERCUR2Z pg2
R16
330
0402
5%
LEDDS3
D2
LED Green 0805
R50 0
www.ti.com TUSB7320 DEMO EVM REVB Schematics
15
SLLU146B–May 2011–Revised August 2012 Schematics
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R34
330
0402
5%
D5
LED Green 0805
1.1V REGULATOR
C69
10uF
R32
4.7K
0402
5% EN1P1
C71
0.01uF SS1P1
C72
NOPOP
U5
TPS74401RGWT
OUT 1
NC
2
NC
3
NC
4
IN
5
IN
6
IN
7
IN
8
PG 9
BIAS
10
EN
11
GND
12
NC
13
NC
14
SS
15
FB 16
NC
17
OUT 18
OUT 19
OUT 20
PAD
21
BOARD_1P1V
R33
1.87K
0402
1%
BOARD_3P3V
R35
4.99K
0402
1%
FB_1PT1V
C70
22uF
C77
22uF_NF
LED3V
R33 R35 OUTPUT
1.13K 4.53K 1.0V
1.37K 4.42K 1.05V
1.87K 4.99K 1.1V (DEFAULT)
2.49K 4.99K 1.2V
+5V
GND0
GND1
+12V
J5
IDE_PWR_CONN
4
3
2
1
C76
22uF
IDE_5V
J26
HDR2X1 M .1
1 2
J27
NOPOP
1 2
BOARD_5V
REG_5V
IDE_5V
GRSTZ pg2
C85
0.1uF
OPTION 1: 5V REGULATOR OPTION 2: 5V FROM IDE CONNECTOR
REG_5V
R37
3.16K_NF
1%
R36
10K_NF
1%
5V VBUS OPTIONS
VSENSE
D6
MBRS540T3_NF
C74
0.01uF_NF
U6
TPS5450_NF
BOOT
1
NC
2
NC_
3
VSENSE
4ENA 5
GND 6
VIN 7
PH 8
GND
9
L1
15uH_NF
BOARD_12V
+C73
330uF_NF
C78
0.01uF_NF
NOTE: USE LOW ESR CAP
C75
0.01uF_NF
NOTE: USE LOW ESR CAP
BOOT PH
Sheet of
SIZE
SCALE: NONE
DWG NO:
POWER
Tuesday, March 22, 2011
B
4 4
BOARD_3P3V
R31
10K
0402
5%
NOTE: ONLY POPULATE ONE OPTION
TUSB7320 DEMO EVM REVB Schematics www.ti.com
16 Schematics SLLU146B–May 2011–Revised August 2012
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EPROM
I2C
DP/DM
VIA AND TRACE REQUIREMENTS:
- MIN VIA PAD SIZE 20mils
- MIN spacing between trace and pad is 5mils
- MIN spacing between VIA and pad is 5mils
- MIN width of trace is 4mils
IMPEDANCE REQUIREMENTS:
- USB_DP/M must be 90-ohm differential (+/-15%)
- USB_SSTXP/N must be 90-ohms differential (+/-15%)
- USB_SSRXP/N must be 90-ohms differential (+/-15%)
- PCIE_TXP/N must be 100-ohms differential (+/-10%)
- PCIE_RXP/N must be 100-ohms differential (+/-10%)
- PCIE_REFCLKP/N must be 100-ohms differential (+/-10%)
LENGTH MATCHING REQUIREMENTS:
- USB_DP/M within 25mils.
- USB_SSTXP/N within 5mils
- USB_SSRXP/N within 5mils
- PCIE_TXP/N within 5mils
- PCIE_RXP/N within 5mils
- PCIE_REFCLKP/N within 25mils.
(U1)
TUSB7340
RX/TX USB3
TYPEA
DOWNSTREAM
PORT1
DOWNSTREAM
PORT2
USB3
TYPEA
DOWNSTREAM
PORT4
DOWNSTREAM
PORT3
USB3
TYPEA
USB3
TYPEA
DP/DM
RX/TX
DP/DM
RX/TX
RX/TX
DP/DM
RX/TX
PCIE
CONNECTOR
Sheet of
SIZE
SCALE: NONE
DWG NO:
TUSB7340_DEMO_REVB
Tuesday, March 08, 2011
B
1 4
www.ti.com TUSB7340 DEMO EVM REVB Schematics
2 TUSB7340 DEMO EVM REVB Schematics
17
SLLU146B–May 2011–Revised August 2012 Schematics
Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated

VSS_OSC
R3
NOPOP
0402
5%
BOARD_3P3V
R4
NOPOP
0402
5%
GPIO0
SCL
C4
22uF
C24
22uF
C5
0.01uF
C6
0.1uF
R11
4.7K
0402
5%
GPIO1
C25
0.1uF
R9
NOPOP
C26
0.1uF
BOARD_3P3V
C27
0.1uF
GPIO2
BOARD_1P1V
AUX_DET
C1
0.1uF
C28
0.1uF
R38
0
C29
0.1uF
VDDA3P3V
TUSB7340
TUSB7340_REVA
U1
CLKREQ#
B36
FREQSEL
B14
GPIO0
A49
GPIO1
B46
GPIO2
B47
GPIO3
B48
GRST#
A15
JTAG_RST#
B32
JTAG_TCK
A32
JTAG_TDI
A35
JTAG_TDO
B31
JTAG_TMS
B30
PCIE_REFCLKN
B41
PCIE_REFCLKP
A45
PCIE_RXN
A42
PCIE_RXP
B39
PCIE_TXN
A41
PCIE_TXP
B38
PERST#
A40
SCL
B2
SDA
A2
SMI
B3
WAKE#
B35
OVERCUR1# A36
OVERCUR2# A37
OVERCUR3# B43
OVERCUR4# B45
PWRON1# B33
PWRON2# B34
PWRON3# A46
PWRON4# A48
R1EXT
A24
R1EXTRTN
B23
USB_DM_DN1 B18
USB_DM_DN2 A13
USB_DM_DN3 A27
USB_DM_DN4 A5
USB_DP_DN1 A20
USB_DP_DN2 B12
USB_DP_DN3 B25
USB_DP_DN4 B5
USB_SSRXN_DN1 B16
USB_SSRXP_DN2 B9
USB_SSRXN_DN3 A29
USB_SSRXN_DN4 A7
USB_SSRXP_DN1 A18
USB_SSRXN_DN2 A10
USB_SSRXP_DN3 B27
USB_SSRXP_DN4 B6
USB_SSTXN_DN1 B15
USB_SSTXN_DN2 B10
USB_SSTXN_DN3 A30
USB_SSTXN_DN4 A8
USB_SSTXP_DN1 A17
USB_SSTXP_DN2 A11
USB_SSTXP_DN3 B28
USB_SSTXP_DN4 B7
VSS_OSC
B21
XI
A23
XO
A22
AUX_DET A52
VDDA_3P3 A25
VDD11 A1 VDD11 A12 VDD11 A16 VDD11 A28 VDD11 A31 VDD11 A33 VDD11 A38 VDD11 A4
NC6
A43
VDD11 A50 VDD11 A6 VDD11 A9 VDD11 B1 VDD11 B17 VDD11 B19 VDD11 B24 VDD11 B37 VDD11 B40 VDD11 B42 VDD11 B44 VDD33 A3 VDD33 A34 VDD33 A39 VDD33 A47 VDD33 A51
VDDA_3P3 A19 VDDA_3P3 A21 VDDA_3P3 A44 VDDA_3P3 B11 VDDA_3P3 B22 VDDA_3P3 B26 VDDA_3P3 B4
NC1
A14
NC2
A26
NC3
B13
NC4
B29
VSS
B20
VSS
A53
NC7
C1
NC8
C2
NC9
C3
NC10
C4
R10 9.09K 1%
PLACE CLOSE TO U1
R39
0
BOARD_3P3V
GPIO3
USB_SSTXN_DN2 pg3
USB_SSTXP_DN2 pg3
USB_DM_DN2 pg3
USB_DP_DN2 pg3
PWRON2Z pg3
OVERCUR2Z pg3
USB_SSRXN_DN2 pg3
USB_SSRXP_DN2 pg3
PWRON3Z pg3
USB_DM_DN3 pg3
USB_DP_DN3 pg3
USB_SSRXN_DN3 pg3
OVERCUR3Z pg3
USB_SSRXP_DN3 pg3
USB_SSTXN_DN3 pg3
USB_SSTXP_DN3 pg3
USB_DM_DN4 pg3
USB_DP_DN4 pg3
USB_SSRXN_DN4 pg3
USB_SSRXP_DN4 pg3
USB_SSTXN_DN4 pg3
USB_SSTXP_DN4 pg3
PWRON4Z pg3
OVERCUR4Z pg3
USB_SSRXP_DN1 pg3
USB_SSRXN_DN1 pg3
USB_DP_DN1 pg3
USB_DM_DN1 pg3
OVERCUR1Z pg3
PWRON1Z pg3
USB_SSTXP_DN1 pg3
USB_SSTXN_DN1 pg3
C32
0.1uF
C34
0.1uF
C35
0.1uF
C33
0.01uF
C36
0.01uF
C37
0.1uF
C30
0.01uF
C31
0.1uF
BOARD_3P3V
GPIO0
FB1
220 @ 100MHZ
BOARD_3P3V
VDDA3P3V
GPIO1
FREQSEL
GPIO2
GPIO3
C11
0.1uF
FREQSEL CLOCK
0 48MHz
1 PLL_FREQ_SEL field in the
USB Control Register
C8
0.1uF
C7
0.01uF
POPULATE PULLDOWN IF I2C EEPROM
NOT USED AND DO NOT POPULATE
PULLUP.
C14
0.1uF
C17
0.1uF
C15
0.01uF
C16
0.1uF
R2
10K
0402
5%
BOARD_3P3V
GRSTZpg4
PCIE_RXNpg3
PCIE_REFCLKPpg3
PCIE_REFCLKNpg3
PERSTZpg3
PCIE_TXPpg3
PCIE_TXNpg3
PCIE_RXPpg3
WAKEZpg3
J22
HDR2X1 M .1
12
SDA
C19
0.1uF
C20
0.1uF
C18
0.01uF
C9
0.1uF
C23
0.1uF
C21
0.01uF
C22
0.1uF
BOARD_1P1V
C2
18pF
XI
XO
C3
18pF
Y1
ECS-48MHZ
R5
NOPOP
0402
5%
R12 1M
R6
NOPOP
0402
5%
C12
0.01uF
C13
0.1uF
R7
NOPOP
0402
5%
R8
NOPOP
0402
5%
R1EXT
U2
24LC01_NF
A0
1
A1
2
A2
3
GND
4SDA 5
SCL 6
WP 7
VCC 8
C10
0.01uF
R1EXTRTN
JUMPER J22 FOR NO WAKE SUPPORTPOPULATE R2 FOR WAKE SUPPORT.
FREQSEL
Sheet of
SIZE
SCALE: NONE
DWG NO:
TUSB7340
Wednesday, February 23, 2011
C
2 4
BOARD_3P3V
R1
NOPOP
0402
5%
NC5
B8
TUSB7340 DEMO EVM REVB Schematics www.ti.com
18 Schematics SLLU146B–May 2011–Revised August 2012
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated

DS_SHLD
C61 0.1uF
USB_SSTXP_DN2 pg2
IND_DS_TXN4
+C44
150uF
R19
30.9K
0402
1%
C43
0.1uF
ILIM1
C38
0.1uF
L10
TDK_TCE_1210
1
2 3
4
BOARD_5V
USB_SSRXN_DN1
L8
TDK_TCE_1210
1
2 3
4
BOARD_3P3V
R13
10K
0402
5%
CAPDSTXN3
CAPDSTXP3
DS3_VBUS
U3
TPS2560DRC
GND
1
IN
2
IN
3
EN1
4
EN2
5
FAULT2Z 6
ILIM 7
OUT2 8
OUT1 9
FAULT1Z 10
PAD
11
L4
TDK_TCE_1210
1
2 3
4
C60 0.1uF
USB_SSTXN_DN2 pg2
WAKEZ_R
C64
22uF
IND_DS_TXN2
+C80
NOPOP
DS3_VBUS
IND_USB_DP_DN3
C65
0.1uF
C66
0.001uF
R30
1M
0402
USB_SSRXP_DN3
USB_SSRXN_DN3
IND_USB_DM_DN3
J3
USB3_TYPEA_CONNECTER
VBUS 1
DM 2
DP 3
GND 4
SSRXN 5
SSRXP 6
GND 7
SSTXN 8
SSTXP 9
SHIELD0 10
SHIELD1 11
DS4_VBUS
IND_USB_DP_DN4
USB_SSRXP_DN4
USB_SSRXN_DN4
J4
USB3_TYPEA_CONNECTER
VBUS 1
DM 2
DP 3
GND 4
SSRXN 5
SSRXP 6
GND 7
SSTXN 8
SSTXP 9
SHIELD0 10
SHIELD1 11
IND_USB_DM_DN4
DOWNSTREAM
PORT3
DOWNSTREAM
PORT4
C45
0.1uF +C46
150uF
PCIE_3P3V
IND_USB_DP_DN1
DS1_VBUS
L7
TDK_TCE_1210
1
2 3
4
USB_SSRXP_DN1
L5
TDK_TCE_1210
1
2 3
4
CAPDSTXN2
CAPDSTXP2
J1
USB3_TYPEA_CONNECTER
VBUS 1
DM 2
DP 3
GND 4
SSRXN 5
SSRXP 6
GND 7
SSTXN 8
SSTXP 9
SHIELD0 10
SHIELD1 11
IND_USB_DM_DN1
C40 0.1uF
PCIE_3P3V
C62
NOPOP
DS2_VBUS
IND_USB_DP_DN2
DS_SHLD
USB_SSRXP_DN2
USB_SSRXN_DN2
OVERCUR2Z pg2
IND_USB_DM_DN2
J2
USB3_TYPEA_CONNECTER
VBUS 1
DM 2
DP 3
GND 4
SSRXN 5
SSRXP 6
GND 7
SSTXN 8
SSTXP 9
SHIELD0 10
SHIELD1 11
DS1_VBUS
C39 0.1uF
IND_DS_TXP4
DS_SHLD
USB_DM_DN4 pg2
VAUX
C63
NOPOP
USB_DM_DN2 pg2
DOWNSTREAM
PORT1
PCIE_RXN pg2
PCIE_RXP pg2
PCIE_REFCLKP pg2
PCIE_REFCLKN pg2
WAKEZpg2
Side B
Component Side
Side A
Solder Side
Key
P1
PCI Express x1 Edge Connector
12V1
B1
12V2
B2
12V5
B3
GND1
B4
SMCLK
B5
SMDAT
B6
GND2
B7
3.3V
B8
J_TRST#
B9
3.3Vaux
B10
WAKE#
B11
RSVD2
B12
GND3
B13
PETp0
B14
PETn0
B15
GND4
B16
PRSNT2#
B17
GND5
B18
PRSNT1# A1
12V3 A2
12V4 A3
GND9 A4
J_TCK A5
J_TDI A6
J_TDO A7
J_TMS A8
3.3V1 A9
3.3V2 A10
PERST# A11
GND8 A12
REFCLK+ A13
REFCLK- A14
GND7 A15
PERp0 A16
PERn0 A17
GND6 A18
PERSTZ pg2
PCIE_TXP
pg2
PCIE_TXN
pg2
C68 0.1uF
C67 0.1uF
CAP_US_TXN
PCIE_PRSNTZ
CAP_US_TXP
USB_DP_DN4 pg2
PCIE_TDITDO
USB_DM_DN3 pg2
IND_DS_TXP2
L2
TDK_TCE_1210
1
2 3
4
USB_DP_DN2 pg2
R17
1M
0402
USB_DP_DN3 pg2
USB_SSRXN_DN4 pg2
PWRON1Zpg2
CAPDSTXP1
BOARD_12V
PWRON3Zpg2
USB_SSRXN_DN2 pg2
R15
330
0402
5%
LEDDS1
D1
LED Green 0805
OVERCUR4Z pg2
USB_SSRXP_DN4 pg2
USB_SSRXP_DN3 pg2
DOWNSTREAM
PORT2
J40
HDR1x3
1
2
3
BOARD_3P3V
U24
TPD2EUSB30_NF
D+
1
D-
2
GND 3
C50
0.001uF
C49
0.1uF
R21
1M
0402
U25
TPD2EUSB30_NF
D+
1
D-
2
GND 3
R14
10K
0402
5%
USB_SSRXP_DN2 pg2
U26
TPD2EUSB30_NF
D+
1
D-
2
GND 3
CAPDSTXN1
U27
TPD2EUSB30_NF
D+
1
D-
2
GND 3
USB_SSRXN_DN3 pg2
MH1
PLATED_MH
1
DS_SHLD
MH2
PLATED_MH
1
DS_SHLD
OVERCUR3Z pg2
C79
1000pF
C48 0.1uF
Sheet of
SIZE
SCALE: NONE
DWG NO:
USB3 AND PCIE CONNECTORS
Wednesday, February 23, 2011
C
3 4
C57 0.1uF
IND_DS_TXN3
OVERCUR1Z pg2
USB_SSTXN_DN4 pg2
USB_SSTXP_DN4 pg2
C47 0.1uF
C41
0.1uF
C42
0.001uF
USB_DM_DN1 pg2
C58
0.1uF
R29
1M
0402
USB_SSRXN_DN1 pg2
USB_SSRXP_DN1 pg2
USB_DP_DN1 pg2
DS_SHLD
C59
0.001uF
USB_SSTXP_DN1 pg2
USB_SSTXN_DN1 pg2
IND_DS_TXP3
+C53
150uF
R27
30.9K
0402
1%
C52
0.1uF
ILIM2
C51
0.1uF
BOARD_5V
BOARD_3P3V
R22
10K
0402
5%
DS2_VBUS
U4
TPS2560DRC
GND
1
IN
2
IN
3
EN1
4
EN2
5
FAULT2Z 6
ILIM 7
OUT2 8
OUT1 9
FAULT1Z 10
PAD
11
L13
TDK_TCE_1210
1
2 3
4
L11
TDK_TCE_1210
1
2 3
4
CAPDSTXN4
CAPDSTXP4
IND_DS_TXP1
IND_DS_TXN1
C56 0.1uF
C54
0.1uF +C55
150uF
JUMPER BETWEEN 2 AND
3 FOR WAKE TESTING.
JUMPER BETWEEN 1 AND
2 FOR NORMAL
OPERATION.
DS4_VBUS
PCIE CEM SPEC MAX VALUES:
PCIE_3P3V: 3 AMPS.
VAUX: 375mA
R16
330
0402
5%
PWRON2Zpg2
PWRON4Zpg2
LEDDS4
LEDDS3
D2
LED Green 0805
R24
330
0402
5%
R23
10K
0402
5%
D3
LED Green 0805
R25
330
0402
5%
LEDDS2
D4
LED Green 0805
R50 0
USB_SSTXN_DN3 pg2
USB_SSTXP_DN3 pg2
DS_SHLD
www.ti.com TUSB7340 DEMO EVM REVB Schematics
19
SLLU146B–May 2011–Revised August 2012 Schematics
Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated

R34
330
0402
5%
D5
LED Green 0805
1.1V REGULATOR
C69
10uF
R32
4.7K
0402
5% EN1P1
C71
0.01uF SS1P1
C72
NOPOP
U5
TPS74401RGWT
OUT 1
NC
2
NC
3
NC
4
IN
5
IN
6
IN
7
IN
8
PG 9
BIAS
10
EN
11
GND
12
NC
13
NC
14
SS
15
FB 16
NC
17
OUT 18
OUT 19
OUT 20
PAD
21
BOARD_1P1V
R33
1.87K
0402
1%
BOARD_3P3V
R35
4.99K
0402
1%
FB_1PT1V
C70
22uF
R33 R35 OUTPUT
1.13K 4.53K 1.0V
1.37K 4.42K 1.05V
1.87K 4.99K 1.1V (DEFAULT)
2.49K 4.99K 1.2V
C77
22uF_NF
LED3V
+5V
GND0
GND1
+12V
J5
IDE_PWR_CONN
4
3
2
1
C76
22uF
IDE_5V
J26
HDR2X1 M .1
1 2
J27
NOPOP
1 2
BOARD_5V
REG_5V
IDE_5V
GRSTZ pg2
C85
0.1uF
OPTION 1: 5V REGULATOR OPTION 2: 5V FROM IDE CONNECTOR
REG_5V
R37
3.16K_NF
1%
R36
10K_NF
1%
5V VBUS OPTIONS
VSENSE
D6
MBRS540T3_NF
C74
0.01uF_NF
U6
TPS5450_NF
BOOT
1
NC
2
NC_
3
VSENSE
4ENA 5
GND 6
VIN 7
PH 8
GND
9
L1
15uH_NF
BOARD_12V
+C73
330uF_NF
C78
0.01uF_NF
NOTE: USE LOW ESR CAP
C75
0.01uF_NF
NOTE: USE LOW ESR CAP
BOOT PH
Sheet of
SIZE
SCALE: NONE
DWG NO:
POWER
Friday, December 03, 2010
B
4 4
BOARD_3P3V
R31
10K
0402
5%
NOTE: ONLY POPULATE ONE OPTION
TUSB7340 DEMO EVM REVB Schematics www.ti.com
20 Schematics SLLU146B–May 2011–Revised August 2012
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated