Texas Instruments TUSB6020EVM User manual

TUSB6020 Evaluation Model (EVM)Compatible With TMS320C6437DaVinci LC EVM
User's Guide
Literature Number: SLAU242February 2008

SLAU242 – February 2008
TUSB6020 EVM
The TUSB6020 is a USB 2.0 high-speed, On-the-Go (OTG) high-performance dual-role USB controllerwith intergrated PHY designed for a seamless connection to the VLYNQ serial interface, and is ideal for awide range of applications. The USB OTG dual-role controller can operate either as a function controllerfor a USB peripheral or as the host/peripheral in point-to-point or multi-point communications with otherfunctions. The integrated USB 2.0 PHY provides one-port operation at low speed (1.5 Mb/s), full speed(12 Mb/s), and high speed (480 Mb/s).
The device is fully compliant with Universal Serial Bus Specification Revision 2.0 and On-The-GoSupplement to the USB 2.0 Specification Revision 1.3.
The TUSB6020 EVM is compatible with several TI DSP platforms that are equipped with a mini-PCIinterface with an active VLYNQ connection. This includes the DM6437 Digital Video DevelopmentPlatform as well as the C6424 DSP Evaluation Module. The TUSB6020 EVM can provide a variety of USBfunctions to a DSP platform. Specifically, the TUSB6020 EVM has proven OTG host and OTG devicecapability. Alternatively, the TUSB6020 EVM can be configured to respond as a USB mass storagedevice.
All trademarks are the property of their respective owners.
TUSB6020 EVM2 SLAU242 – February 2008Submit Documentation Feedback

1.1 TUSB6020 Connection Overview
VLYNQ CRUN
DM6437 TUSB6020
VLYNQ CRUN
VLYNQ CLK VLYNQ CLK
VLYNQ RXD0
VLYNQ RXD1
VLYNQ RXD2
VLYNQ RXD3
VLYNQ TXD0
VLYNQ TXD1
VLYNQ TXD2
VLYNQ TXD3
VLYNQ TXD0
VLYNQ TXD1
VLYNQ TXD2
VLYNQ TXD3
VLYNQ RXD0
VLYNQ RXD1
VLYNQ RXD2
VLYNQ RXD3
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
10.7 kΩ, 1%
VDD1.8
VBUS Power Switch
Dual Voltage
Regulator
USB Micro-AB
Connector
VDD1.8
VIN (5 V)
VDD1.8
VSSREF
VSS
GND
VOUT3
PGOOD3_3 PGOOD1_5
EN
VOUT2
VIN
VIN
VBUS
VBUS
ID
DM
DP
VBUS
ID
DM
DP
VDDA3.3
VDDS3.3
CPEN
VDD1.5
VDDD1.5
VDDCM1.5
VDDA1.5
3.3VSW_EN
1.5V_SWEN
SLEEP
RSTn
CLKIN
(see Note A)
XI
XO
19.2 Mhz
RSVD
RSVD
RSVD_NC
RSVD_NC
R1
www.ti.com TUSB6020 Connection Overview
Figure 1-1 shows a high-level diagram of the connections between the TUSB6020 and the variouscomponents on the TUSB6020 EVM, as well as the DSP platform.
A Only CLKIN or XI/XO is required. This is selected by GPIO6 at power up.
Figure 1-1. TUSB6020 Connection Block Diagram
SLAU242 – February 2008 TUSB6020 EVM 3Submit Documentation Feedback

1.2 TUSB6020 EVM
TUSB6020
Switch
Settings
TUSB6020 EVM www.ti.com
Figure 1-2. TUSB6020 EVM – Top Side
TUSB6020 EVM4 SLAU242 – February 2008Submit Documentation Feedback

1.3 TUSB6020 EVM Features
1.4 Quick Hardware Setup
www.ti.com TUSB6020 EVM Features
•The TUSB6020 EVM is shipped with a USB mini-AB connector, J13, installed. There are alsooverlapping footprints on the EVM for a USB Standard A connector and a USB Standard B connector.If one of these options is needed, the mini-AB connector can be de-soldered from J13, and a Bconnector added to J12 or an A connector added to J11. There is also a jumper, J14, that allows forthe ID pin of the mini-AB connector to be grounded for test purposes if installed.•There are two clock source options available on the TUSB6020 EVM. There is a 24-MHz crystal clocksource, X2, and a 19.2-MHz oscillator clock source, X1. The clock source used by the TUSB6020 isdetemined by the setting of Switch 7 of the toggle switch set, S1.•The toggle switches at S1 connect to the GPIO7:0 pins of the TUSB6020. Switch 8 must be turned onat power-up (GPIO7 = low) for the TUSB6020 to operate properly. The setting of switch 7 at power upis used to determine the clock source. After power up, any of the switches can be used as inputs forthe associated GPIOs.•A reset to the TUSB6020 device can be generated in a variety of ways on the TUSB6020 EVM. Areset can be manually generated using the pushbutton installed at SW1. A reset is generatedautomatically based on the power-good outputs of the voltage regulator at power up. In addition, byinstalling jumper, J9, a reset can be generated and held by installing the jumper to ground.•There are a number of test jumpers and test points on the TUSB6020 EVM that are not necessary toTUSB6020 EVM operation but could be used to test functionalities for use in production designs. Someof these are: the SLEEP jumper at J16, the 1.5V_SWEN jumper at J15, the 3.3V_SWEN jumper atJ10, and the jumper on the level shifted version of CP_EN at J4.•The power circuitry of the TUSB6020 EVM is set up to allow for easy power measurements. The 5-Vpower jack at P1 is not installed because the TUSB6020 can be powered by the DSP platform via themini-PCI interface. To take a power measurement, the trace connecting the associated jumper pinsshould be cut and the jumper installed so that an ammeter can be inserted between the pins. See theschematic for particulars on voltage rails, but traces connect the jumper pins on the following: J37, J38,J39, J40, J42, J43, J45, J46, J51, and J59.
1. Check that switches 7 and 8 in S1 are set to select the TUSB6020 normal device mode and the clocksource. For normal operation, switch 8 must be turned on to pull GPIO7 low. Switch 7 must be turnedon to select the XI clock input (24 MHz) with GPIO6 pulled low or left off to select the CLKIN clockinput (19.2 MHz) with GPIO6 pulled high.2. Insert the TUSB6020 EVM into the mini-PCI slot of the unpowered TMS320C6437 or TMS320C6424EVM.
3. Connect a UART cable from the TMS320C6437 EVM to a PC.4. Connect a mini-USB cable from EMU-USB, J501, of the TMS320C6437 EVM to a PC loaded with theCode Composer, CCStudio v3.3, C6424 software.5. Add wallpower to 5V IN, J14, of the TMS320C6437 EVM.6. Check that LEDs, DS5 and DS502, are lit on the TMS320C6437 EVM.7. Check that LED D1 is lit on the TUSB6020 EVM.
SLAU242 – February 2008 TUSB6020 EVM 5Submit Documentation Feedback

1.5 Quick Software Setup
Quick Software Setup www.ti.com
1. Set up the COM port.
2. Start the Code Composer software select Debug →Connect.
6TUSB6020 EVM SLAU242 – February 2008Submit Documentation Feedback

www.ti.com Quick Software Setup
3. Select File →Load program and select the program and then run it. On the COM port you should see:
SLAU242 – February 2008 TUSB6020 EVM 7Submit Documentation Feedback

1.6 TUSB6020 EVM Features
TUSB6020 EVM Features www.ti.com
4. Connect a USB cable from a PC to the TUSB6020 EVM. You should see the following on the COMport:
5. At the prompt, enter h to display a list of test options.
Table 1-1. Bill of Materials and SchematicsITEM QUANTITY REFERENCE PART PKG MANUFACTURER PART NO. NOTES
C1, C28, C30,C38, C39,C42,1 10 .01 µF 603C44, C53, C56,C59
2 2 C2, C3 33 pF 603
C12, C58, C6,3a 7 C62, C63,C64, 10 µF 603C65
C19, C21, C23,C13, C18,C20,3b 3 C22, C27, C29, 10 µF, Tantalum 805C37,C40, C41,C43, C54,C57
4 15 C60, C66, C67 .1 µF 603
5 2 C14, C45 1 µF 603
6 1 C15 4.7 µF 603
7 1 C26 1 µF 805
8 1 D1 GREEN 805 Panasonic LNJ306G5PRX
9 1 F1 3A FUSE N/A LittelFuse R251003
J4, J5, J6, J9, J10,J14, J15, J16, J37,10 19 J38, J39, J40, J42, HDR2X1 M .1 DNIJ43, J44, J45, J46,J51, J59
11 1 J11 USB Series A N/A DNI
12 1 J12 USB Series B N/A DNI
13 1 J13 USB Mini/Micro AB Mill-Max MNE20-5G5P10
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www.ti.com TUSB6020 EVM Features
Table 1-1. Bill of Materials and Schematics (continued)ITEM QUANTITY REFERENCE PART PKG MANUFACTURER PART NO. NOTES
J20, J21, J22, J23,J24, J25, J26, J27,J28, J29, J30, J31,14 23 PAD DNIJ32, J33, J34, J35,J36, J54, J55, J56,J57, J58, J61
15 1 L1 INDUCTOR mpz.pdf TDK MPZ2012S331AT
16 1 P1 5 V at 3 A CUI Inc CP-202AH
17 1 P2 128 pin Mini PCI Edge N/A N/A N/A DNI
18 1 R2 10.7K 1% 603
R4, R30, R4,R106, R107,R108, R109,19 15 R110, R111, 1K 603R112, R113,R114, R115,R123, R124
R28, R40, R43,R49, R61, R62,R105, R116,20 16 R117, R118, 10K 603R119, R120,R121, R122,R135, R136
R29, R31, R32,21 4 0 603R48
22 1 R33 0 603 DNI
R44, R47, R52,23 4 250K 603R54
24 1 R60 330 603
25 1 SW1 SW TACT Alps SKHHALA010
26 1 S1 SW DIP-8 ITT TDA08H0SK1R
27 1 U1 TUSB6020 ZQE80 TI TUSB6020ZQE
SN74LVC2T45, Dual Bit/Supply28 1 U3 SM8 TI SN74LVC2T45DCTRTransceiver
SN74ALVC08, Multiple AND29 1 U4 SOIC14 TI SN74ALVC08DGate
30 1 U5 TPS3836E18, Reset Supervisor 5SOT-23 TI TPS3836E18
31 1 U8 TPS77618, 1.8 V Regulator SOIC8 TI TPS77618D
TPS70848, Dual Voltage32 1 U9 SM20 TI TPS70848PWPRregulator
33 1 U11 TPS2051B, V
BUS
Power Switch DBV5 TI TPS2051BDBV
34 1 X1 19.2 MHz, CSX-1 SMT Crystek 601512
35 1 X2 24 MHz, C
L
= 20 pF SMT Crystek 16808
SLAU242 – February 2008 TUSB6020 EVM 9Submit Documentation Feedback

1.7 TUSB6020 Schematics
Design Note: X1 should be placed close to U1
Design Note: X2, C2 and C3 should be placed close to U1
Design Note: R2 should be placed close to U1
Design Note: Pull-down
resistors are required on
"No Connect" signals:
A8, B7, B8, B9, C6, C7,
C8, D6, D8, E7, G4 and
J5.
J23
PAD
J24
PAD
R112
1K
J26
PAD
J25
PAD
J27
PAD
J28
PAD
R114
1K
J29
PAD
J30
PAD
R123
1K
J31
PAD
J32
PAD
R106
1K
R108
1K
J21
PAD
R110
1K
J22
PAD
R115
1K
R113
1K
R111
1K
R109
1K
R107
1K
1 2
J16
SLEEP
R4
1K
R30
1K
VDDA_3.3V
VLYNQ_TXD[3..0] 7
VLYNQ_TXD2
VLYNQ_TXD3
VLYNQ_TXD0
VLYNQ_TXD1
VLYNQ_RXD3
VLYNQ_RXD1
VLYNQ_RXD2
VLYNQ_RXD0
VLYNQ_RXD[3..0] 7
VLYNQ_CRUN 7
VLYNQ_CLK 7
VSS1 A2
VSS2 A6
VSS3 B4
RSVD4 B9
VSS5 E5
VLYNQ_CRUN E9
VSS6 G1
VLYNQ_TXD1 G9
VSS9 J2
NC4 J4
VSS10 J8
VSSREF B1
VSSCM1P5 D3
VSSA3P3 E4
VSSA1P5 E1
VSSD1P5 F4
R1
C2
XO
A3 XI
A4
VDD15_2
A1
VDD15_3
A9
VDD15_4
B3
VDD15_5
C5 VSS4 D9
VDDCM1P5
D2
VLYNQ_CLK F9
VDD15_6
J3
VDDD1P5
F1
VDDA1P5
E3
DP
D1
DM
E2
VBUS
F3
ID
F2
VDD18_1
A7
VDD18_2
B5
VLYNQ_TXD0 H9
VDD18_4
J1
VLYNQ_RXD3 J6
VDDA3P3
C1
NC1 F6
GPIO3
E6
NC2 G5
VDDS3P3_2
G6
NC3 H5
VLYNQ_RXD2 H6
VLYNQ_RXD0 H7
VLYNQ_TXD2 H8
VDDS3P3_1
F8
VLYNQ_TXD3 F7
RSVD9 D8
RSVD6 C7
VDD15_1
D7
RSVD7 C8
RSVD2 B7
RSVD3 B8
GPIO0
H4
GPIO1
D5
GPIO2
B6
VDD18_3
E8
GPIO4
C4
RSVD10 E7
GPIO6
F5
GPIO7
B2
VDDS3P3_3
J9
RSTn
H1
CPEN
H2
SLEEP H3
1.5V_SWEN
G2 3.3V_SWEN
G3
RSVD11 G4
VSS7 G7
VSS8 G8
RSVD1 A8
CLKIN
A5
GPIO5
C9
RSVD8 D6
TEST D4
VLYNQ_RXD1 J7
RSVD12 J5
RSVD5 C6
U1
TUSB6020
DM3
DP3
ID3
VBUS
3.3V_SWEN
VDDD_1.5V
1.5V_SWEN
VDDCM_1.5V
VDDA_1.5V
VDDA_3.3V
VDD_1.8V_TUSB6020
VDD_1.5V
1 2
J10
1 2
J15
CP_EN2
GPIO26
GPIO06
RESETn2
GPIO16
GPIO46
GPIO56
GPIO66
GPIO36
GPIO76
J33
PAD J34
PAD
J35
PAD
R124
1K
1 2
X2
24 MHz, CL = 20pF
C2
33pF
C3
33pF
R2
10.7K 1%
J36
PAD
J20
PAD
J54
PAD
J55
PAD
J56
PAD
J57
PAD
R105 10K
J58
PAD
VDD_1.8V
VCC
4
EN
1
GND
2OUT 3
X1
19.2 MHz, CSX-1
C1
.01uF
TUSB6020 Schematics www.ti.com
Figure 1-3. TUSB6020
10 TUSB6020 EVM SLAU242 – February 2008Submit Documentation Feedback

R31 0
1 2
J9
R28
10K
R32
0
VDD_1.8V
1
4
2
3
SW1
SW TACT
CT 1
GND 2
MRn 3
VDD
5
RESETn
4
U5
TPS3836xxx
R29
0
R33
0, NO POP SILKSCREEN: RESET
PGOOD3_34
VDD_1.8V
PGOOD1_54
VCC 14
4B 13
4A 12
4Y 11
3B 10
3A 9
3Y 8
1A
1
1B
2
1Y
3
2A
4
2B
5
2Y
6
GND
7
U4
SN74ALVC08
PGOOD
Silkscreen: RSTn
RESETn1
CP_EN1 ENABLE 4
VDD_1.8V
R136
10K
VDD_5.0V
VCCA 1
A1 2
A2 3
DIR
5B2
6B1
7
GND 4
VCCB
8
U3
SN74LVC2T45
www.ti.com TUSB6020 Schematics
Figure 1-4. Reset
SLAU242 – February 2008 TUSB6020 EVM 11Submit Documentation Feedback

DP1
DM1
ID1
VBUS
1
DM
2
DP
3
GND
4
S1
S1
S2
S2
J11
USB Series A
VBUS
1
DM
2
DP
3
GND
4
S1
S1
S2
S2
J12
USB Series B
L1
INDUCTOR
SILKSCREEN: USB ID
1 2
J14
VBUS
1
DM
2
DP
3
GND
5
S1
S1
S2
S2
ID
4
S3 S3
S4 S4
J13
USB Mini / Micro AB
VBUS
PLACEMENT NOTES: OVERLAP SHORTED USB SERIES A, SERIES B, AND MINI / MICRO AB
FOOTPRINTS. ROUTE DP/DM LINES ON TOP LAYER OF BOARD AS 90 OHM DIFFERENTIAL PAIRS.
SURROUND DP/DM LINES WITH GROUND PLANE AND GROUND VIAS.
TUSB6020 Schematics www.ti.com
Figure 1-5. USB Connectors
12 TUSB6020 EVM SLAU242 – February 2008Submit Documentation Feedback

VBUS_REGULATOR
C66
.1uF
C67
.1uF
C26
1uF
R40
10K
OUT 1
GND 2
ENABLE
4
OC/ 3
IN
5
U11
TPS2051B
VBUS Regulator
1 2
J5
SILKSCREEN: EN1
1 2
J6
ENABLE2 1 2
J4
R43
10K
R41
1K
R49
10K
SILKSCREEN: 3.3EN/
SILKSCREEN: 1.5EN/
VDD_5.0V
VDD_5.0V
R61
10K
R62
10K
Design Note: J4 should have a default
trace run between pins 1 and 2 on the
top layer.
PGOOD1_5 2
C23
10uF
VOUT2_REGULATOR
VOUT3_REGULATOR
C21
10uF
PGOOD3_3 2
R54
250K
VIN1A
3
VIN1
2
NC1
1
RESET/
7
EN2/
6
MR/
4
EN1/
5
GND
8
VIN2
9
VIN2A
10 NC2 11
VOUT2A 12
VOUT2 13
VSENSE2/FB2 14
PG2 15
VOUT1A 18
VSENSE1/FB1 17
PG1 16
VOUT1 19
NC3 20
U9
TPS70848
3.3V & 1.5V LDO Regulator
C20
.1uF
C22
.1uF
R44
250K
R52
250K
C19
10uF
C13
.1uF
C14
1uF
C15
4.7uF
1
2
D1
GREEN
R60
330
C12
10uF
VDD_MMOD_REGULATOR
SILKSCREEN: 5V IN
IN2
3
EN
2
GND
1
FB 7
OUT1 6
IN1
4
OUT2 5
PG 8
U8
TPS77618
C18
.1uF
SILKSCREEN: 5V
1.8V LDO Regulator
R47
250K
1 2
F1
3A FUSE
11
2
2
3
3
P1
5V @ 3A
VDD_5.0V
R48
0
www.ti.com TUSB6020 Schematics
Figure 1-6. Voltage Regulators
SLAU242 – February 2008 TUSB6020 EVM 13Submit Documentation Feedback

Design Note: J37, J38, J39, J40, J42, J43,
J45, J46, J51, and J59 should have default
trace run between pins 1 and 2 on the top
layer. These should be thick power traces.
Design Note: VDDA3P3 and VDDS3P3 are tied
together in this design.
C27
.1uF
C29
.1uF
1 2
J45
VDDA_3.3V
VDD_1.8V_TUSB6020
VBUS
C38
.01uF
VDD_1.8V
C40
.1uF
C44
.01uF
VDD_MMOD_CONNECTOR
C45
1uF
VOUT2_REGULATOR
C63
10uF
C28
.01uF
C30
.01uF
C37
.1uF
1 2
J43
VBUS_REGULATOR
1 2
J44
1 2
J46
C65
10uF
VDD_MMOD_REGULATOR
SS: 3.3R
SS: 1.8R
SS: 1.8C
SS: VBUSR
SS: VDD1.8
1 2
J51
VDDCM_1.5V
VDD_1.5V
C61
10uF
1 2
J37
C59
.01uF
1 2
J38
1 2
J39
1 2
J40
C57
.1uF
C56
.01uF
1 2
J42
C41
.1uF
C39
.01uF
VOUT3_REGULATOR
VDDA_1.5V
C53
.01uF
C64
10uF
C54
.1uF
C60
.1uF
SS: VDDD
SS: VDDCM
SS: VDD
SS: 1.5R SS: VDDA
C58
10uF
C62
10uF
C42
.01uF
C43
.1uF
VDDD_1.5V
TUSB6020 Schematics www.ti.com
Figure 1-7. Power Jumpers
14 TUSB6020 EVM SLAU242 – February 2008Submit Documentation Feedback

R116
10K
Design Note: GPIO7 must always be pulled low, directly to
ground, for the TUSB6020 to operate properly. GPIO6
can be pulled low to select the XI input, otherwise the
TUSB6020 will select the CLKIN as the clock source.
VDD_1.8V
GPIO11
GPIO01
GPIO21
GPIO41
GPIO31
GPIO61
GPIO51
GPIO71
R117
10K
R118
10K
R119
10K
R120
10K
R121
10K
R122
10K
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
S1
SW DIP-8
R135
10K
www.ti.com TUSB6020 Schematics
Figure 1-8. GPIO Switches
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Design Note: The trace lengths
of the VLYNQ signals should be
matched as closely as possible.
GND_9
9
GND_14
14
GND_20
20
GND_23
23
GND_25
25
GND_27
27
GND_32
32
GND_33
33
GND_34
34
GND_35
35
GND_37
37
GND_41
41
GND_42
42
GND_45
45 GND_44
44
GND_46
46
GND_48
48
GND_50
50
GND_52
52
GND_54
54
GND_56
56
GND_58
58
GND_60
60
GND_62
62
GND_64
64
GND_66
66
GND_68
68
GND_69
69
GND_72
72
GND_74
74
GND_76
76
GND_78
78
GND_79
79
GND_81
81
GND_83
83
GND_85
85
GND_87
87
GND_90
90
GND_91
91
GND_92
92
GND_94
94
GND_95
95
GND_96
96
GND_99
99
GND_101
101
GND_102
102
GND_110
110
GND_114
114
GND_119
119
HOLE1 125
HOLE2 126 GND_PAD1
127
GND_PAD2
128
WLAD_UART_RXD
122
WLAD_UART_TXD
120
WLAN_RS232_RXD
118
WLAN_RS232_TXD
117
JTAG_WLAN_TCK
13
JTAG_WLAN_TMS
12
JTAG_WLAN_TRSTN
10
JTAG_WLAN_TDI
11
JTAG_WLAN_TDO
8
DBG_I2C_SCL
107
DBG_I2C_SDA
106
DBG_I2C_SA2
108
DBG_EE_WP
105
RSVD_15 15
RSVD_55 55
RSVD_57 57
DBG_JTAG_WLAN_3V
17
DBG_GPIO_3V
39
DBG_RS232_3V
123
D1_5V 2
5V_97 97
5V_103 103
VBAT 1
D3_3V_19 19
D3_3V_28 28
D3_3V_31 31
D3_3V_40 40
D3_3V_63 63
D3_3V_70 70
D3_3V_88 88
D3_3V_89 89
D1_8V 111
VIOXIO_3V 115
VLYNQ_SDIO_VIO 18
OSC32_768KHZ 7
SLP_CLK_EN 3
PM_EN 5
WLAN_RESET 26
WLAN_ELP_REQ 4
WLAN_INTR 6
1.8V_BTH_SHUTDOWN 29
1.8V_BTH_ELP_WKUP 38
1.8V_BTH_INTR 30
1.8V_BTH_UART_RTS 113
1.8V_BTH_UART_CTS 116
1.8V_BTH_UART_TXD 104
1.8V_BTH_UART_RXD 109
1.8V_BTH_PCM_CLK 71
1.8V_BTH_PCM_FS 73
1.8V_BTH_PCM_TXD 75
1.8V_BTH_PCM_RXD 77
WLAN_VLYNQ_CLK/SDIO_CLK 16
WLAN_VLYNQ_SCRUN/SDIO_DO 24
WLAN_VLYNQ_TD0/SDIO_CMD 21
WLAN_VLYNQ_TD1/DSIO_D3 22
WLAN_VLYNQ_RD0/SDIO)D2 36
WLAN_VLYNQ_RD1/SDIO_D1 43
WLAN_VLYNQ2_CLK 93
WLAN_VLYNQ2_SCRUN 124
WLAN_VLYNQ2_TXD0 98
WLAN_VLYNQ2_TXD1 100
WLAN_VLYNQ2_RXD0 112
WLAN_VLYNQ2_RXD1 121
BT_RF_SD 47
BT_FREQ 49
BT_PRI_DATA 51
BT_PA_ON_OR_RX 53
WLAN_VLYNQ_TD2 59
WLAN_VLYNQ_TD3 61
WLAN_VLYNQ_RD2 65
WLAN_VLYNQ_RD3 67
WLAN_VLYNQ2_TD2 80
WLAN_VLYNQ2_TD3 82
WLAN_VLYNQ2_RD2 84
WLAN_VLYNQ2_RD3 86
P2
128 pin Mini PCI Edge
1 2
J59
VDD_5.0V
J61 PAD VDD_MMOD_CONNECTOR
VLYNQ_CRUN 1
VLYNQ_CLK 1
VLYNQ_TXD1
VLYNQ_TXD0
VLYNQ_RXD1
VLYNQ_RXD0
VLYNQ_RXD3
VLYNQ_TXD2
VLYNQ_TXD3
VLYNQ_RXD2
VLYNQ_RXD[3..0] 1
VLYNQ_TXD[3..0] 1
TUSB6020 Schematics www.ti.com
Figure 1-9. Mini PCI Connector
16 TUSB6020 EVM SLAU242 – February 2008Submit Documentation Feedback

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