Texas Instruments bq24070 User manual

User's GuideSLUU248 – May 2006
bq24070 1.5-A Single-Chip Li-Ion and Li-Pol ChargeManagement IC EVM
This user’s guide describes the bq24070 evaluation module (EVM). The EVM providesa convenient method for evaluating the performance of a charge management andsystem power solution for portable applications using the bq24070 product family. Acompletly designed and tested module is presented. The charger is designed to deliverup to 1.5 A of continuous current to the system or charger for one-cell Li-ion orLi-polymer applications using a dc power supply. The charger is programmed from thefactory to deliver 1 A of charging current.
Contents1 Introduction .......................................................................................... 22 Considerations When Testing and Using bq24070 ICs ....................................... 23 Performance Specification Summary ............................................................ 34 Test Summary ...................................................................................... 35 Schematic ........................................................................................... 66 Physical Layouts .................................................................................... 77 Bill of Materials .................................................................................... 118 References ......................................................................................... 11
List of Figures
1 Test Diagram ........................................................................................ 32 bq24070 EVM Schematic.......................................................................... 63 Top Assembly View ................................................................................ 74 Top Silkscreen ...................................................................................... 85 Board Layout – Top Etch Layer .................................................................. 86 Board Layout – Second Etch Layer .............................................................. 97 Board Layout – Third Etch Layer ................................................................. 98 Board Layout – Bottom Etch Layer ............................................................. 10
List of Tables
1 Performance Specification Summary For bq24070 EVM ..................................... 32 Bill of Materials .................................................................................... 11
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1 Introduction
2 Considerations When Testing and Using bq24070 ICs
Introduction
The bq24070 powers the system while independently charging the battery. This feature reduces thecharge and discharge cycles on the battery, allows for proper charge termination, and allows the systemto run with an absent or defective battery pack. This feature also allows for the system to turn oninstantaneously from an external power source even when using a deeply discharged battery pack.
The IN pin can be programmed to perform like a USB input by pulling the MODE pin low or like an adapterinput if the MODE pin is pulled high. An external resistor, RSET1, sets the magnitude of the chargecurrent. If the charge current exceeds the available input current, the voltage on the OUT pin drops to theDPPM
OUT
threshold or the battery voltage, whichever is higher. The charging current is reduced to whatcurrent is available (I
BAT
= I
IN
– I
OUT
).
The bq24070 charges the battery in three phases: conditioning, constant current, and constant voltage.Charge is terminated based on minimum current. A resistor-programmable charge timer provides abackup safety for charge termination. The bq24070 automatically restarts the charge if the battery voltagefalls below an internal threshold. The bq24070 automatically enters sleep mode when both supplies areremoved (a drop to the battery voltage).
It is recommended to read the bq24070 data sheet prior to evaluating this EVM. Consider the followingnoteworthy items while testing and using the bq24070 IC.
The two potential sources to power the system ( V
OUT
) are: IN (adapter or USB source) and the battery.The IC is designed to power the system continuously. The battery, in most cases, is the last line ofbackup. If the adapter or USB input is not available (or disabled), the battery connects to the system.
In thermal regulation condition (T
J
= 125°C—not a first-choice design mode of operation), the chargecurrent is reduced to the battery, and the system still gets its power from the input. The batterysupplement is still available in thermal regulation if V
OUT
falls to V
BAT
. In thermal cutoff (~155°C), the inputsources are disconnected, but the internal battery FET connects the battery to V
OUT
.
There are two types of OUT-pin short circuit, one associated with the input IN pin (V
OUT
< 1 V) and theother associated with the BAT pin (V
BAT
– V
OUT
> 200 mV). For the BAT short circuit, the battery FETopens if a short on V
OUT
pulls more than ~4 A of current (>200-mV drop across the BAT FET) from thebattery. The recovery method is from a 10-mA current source between the BAT and OUT pins, so theshort and any system load must be removed before the OUT pin can recover within 200 mV of V
BAT
. Notethat the current source is ~10 mA with the OUT pin near 0 V, but falls off to ~2 mA as the OUT pin goesabove 1 V. For the IN-to-OUT short-circuit case where the OUT pin is less than 1 V, the recovery methodis by a 500- Ωpullup resistor from IN to OUT. The system load must be reduced (>200 Ω) such that thepullup can pull V
OUT
above 1 V.
When there is no power to the system and the battery is hot-plugged, the BAT-pin voltage leads theOUT-pin voltage due to the system capacitance, and the output may go into BAT short-circuit mode. Toavoid this, a feature was added to the DPPM pin. If the voltage on the DPPM pin is held below 1 V, thenthe short-circuit feature is disabled. Therefore, placing a small capacitor (~1 nF to 10 nF) across theDPPM resistor delays the short-circuit protection on input power-up by a few microseconds.
Another feature that protects system integrity is dynamic power path management (DPPM). The voltageon the DPPM pin (DPPM
IN
) times a scaling factor of ~1.15 is the DPPM
OUT
voltage. The DPPM
OUT
voltageis the critical voltage, determined by the designer, where battery charging current is reduced to keep thesystem voltage ( V
OUT
) from further decay. A special feature to keep in mind is that when in DPPM mode,the internal oscillator timer is slowed in proportion to the reduction in programmed charger current. Thisallows the timers (safety and others) to be appropriately adjusted during operation. Therefore, whenperforming any test where time is measured, keep in mind this adjustment factor.
The MODE (High/Low) sets which input source is present (adapter or USB). The CE pin (going high)immediately enables the chip; disabling it (going low) delays handoff for 5 ms.
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3 Performance Specification Summary
4 Test Summary
4.1 Equipment
4.2 Equipment Setup
10 to 30W W
J4
J1
5.25 VDC AC
GND
DMM
#1
DMM
#3
P/A
#1
DMM
#2
J2
+
+
+
–
–
–
TS
OUT
BAT+
B0136-01
(DC–) BAT–
GND
HPA180 UUT®
TP4
LDO
bq24070 Charger EVM
Li-Ion, Single-Cell,
1- to 2- A h Capacity×
Performance Specification Summary
Table 1 summarizes the performance specifications of the EVM.
Table 1. Performance Specification Summary For bq24070 EVM
SPECIFICATION TEST CONDITIONS MIN TYP MAX UNITS
Input dc voltage, V
I(AC)
4.8 5 6.5
VInput dc USB voltage, V
I(USB)
5Battery charge current, I
O(CHG)
1 2+ APower dissipation, bq24070 IC, 1 cell P
DISS
= (V
IN
– V
OUT
)Iout + (V
IN
– See
(1)
WV
BAT
)I
BAT
+ (V
IN
– V
LDO
)I
LDO
(1)
The HPA180 (bq24070) thermal design is optimized (8
+
vias, 0.031-inch PWB, 2 oz. copper) to give θ
JA
~ 27°C/W.
This section covers the setup and tests performed in evaluating the EVM.
•Power supply (5.25 ± 0.25 VDC), current limit set to 2.0 A ± 0.2 A for AC input to the UUT•Three Fluke 75 DMMs (equivalent or better)•Oscilloscope, Model TDS220 (equivalent or better)
•Preset the UUT power supply voltage and current prior to connection to UUT; turn off the power supplyand connect the supply to J1-IN/GND (+ to IN and – to GND).•Connect a 10- Ωto 30- Ωload to J4-OUT/GND.•Connect a fully discharged (< 2.8-VDC) single-cell Li-ion or Li-polymer battery to J2-BAT+/BAT–.•Connect the DMMs as shown in Figure 1 .
Figure 1. Test Diagram
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4.3 Test Procedure
Test Summary
1. Verify that the equipment is set up according to Equipment Setup,Section 4.2 .2. Set jumpers on the UUT as follows: JMP1 to 0.5; JMP2 to HI; JMP3 to EN; install jumpers on JMP4through JMP6.3. Adjust R_DPPM until TP1 is 36.5 k Ω±0.1 k Ωwith respect to GND, and adjust R_TMR until TP2 is50 k Ωwith respect to GND.4. Verify that V
OUT
is approximately equal to V
BAT
(if V
OUT
< 1.1 V, the output is in short-circuit mode. Toget out of this mode, momentarily disconnect the 10- Ωload).5. Power up the 5.25-VDC supply to the UUT.6. Verify V
BAT
is between 2.4 VDC and 3 VDC, and the charger is in pre-charge state: LEDs STAT1 (D2),STAT2 (D3), and ACPG (D1) are on.If V
BAT
is above the low-voltage threshold (V
(LOWV)
~3 V), then the IC is in fast-charge mode [STAT2(D3) is off (High)]. If the IC is in fast charge, skip to step 10.7. Verify I
BAT
is ~0.1 A ( I
BAT
~=I
IN
– (V
OUT
/ R
OUT
) – 0.01 A)8. Verify V
OUT
is between 4.3 VDC and 4.5 VDC.9. Verify V
LDO
(TP4) is between 3.2 VDC and 3.4 VDC.10. Allow the battery to charge until V
BAT
is between 3.2 VDC and 4.0 VDC. The charger should deliverthe programmed constant current to the battery unless the input cannot source the required current.11. Verify D3 (STAT2) has turned off.12. Verify I
BAT
is ~1.0 A [for a 10-k Ωresistor on ISET1, I
BAT
~=I
IN
– (V
OUT
/ R
OUT
) – 0.01 A].13. Apply a short between J3-4 (CE) and J3-3 (GND) on the UUT. This overrides the JMP3 100-k Ωpullup,disables the charging, puts the IC in low-power mode, and connects the battery to the OUT pin. Notethat if CE is floated (JMP3 is removed and J3-3 to 4 connection is removed), the IC may bouncebetween the charging and disabled states. Verify on the scope that V
OUT
does not drop out whenswitching between the input source and the battery source.14. Verify D2 (STAT1) has turned off.15. Verify I
IN
drops below 10 mA [should be < 200 µA into the IC if PG LED (current) JMP6 is removed].16. Verify V
OUT
is within –50 mV of V
BAT
.17. Remove short betwen J3-4 and J3-3 on UUT. Verify on the scope that V
OUT
does not drop out. VerifyD2 (STAT1) has turned on, charging has resumed, and V
OUT
is powered from the input.18. Disconnect the 5.25-VDC input supply from the UUT IN input. Verify on the scope that V
OUT
does notdrop out. Verify V
OUT
is within –50 mV of V
BAT
and D2 (STAT1) and D1 ( PG) LEDs turn off. Thisdemonstrates battery power backup for loss of adapter power.19. Reapply the +5.25-VDC supply to the UUT IN input. Verify on the scope that V
OUT
does not drop out.Verify D2 (STAT1) and D1 ( PG) LEDs turn on.20. Reduce the current limit on the input supply to ~ 1 A (going to the IN pin on the UUT) and verify on thescope that V
OUT
has dropped to the VDPPM level of ~4.2 V [(3.65 V at TP1) × 1.15 = 4.2 V]. Note thatthe current into the battery is ~ 580 mA (1-A input minus 420 mA to the system), which has beenreduced to keep the output from falling below the programmed DPPM OUTPUT threshold of 4.2 V.This demonstrates DPPM operation (charging current to the battery is reduced if output drops to theDPPM OUTPUT voltage threshold attempting to keep the output voltage from dropping further).21. Further reduce the input current limit to 250 mA. Verify on the scope that V
OUT
does not drop out.Verify that V
OUT
drops just below V
BAT
(< 50 mV). Because the available input current is less than thesystem OUT load, reducing the battery charging current to zero is still not enough reduction in load tokeep the output from dropping. Once the output drops below ~ 50 mV, the internal battery FET turnson and allows the battery to source the OUT pin system load. This demonstrates battery supplementmode.
22. Return the current limit of the 5.25-V supply to ~2 A. Verify V
OUT
returns to ~4.4 V.23. Set JMP2 (MODE) to LO (USB mode). Verify that the input current, I
IN
, drops to between 400 mA and500 mA. The programmed charge current of ~1 A and the system load of 10 Ωexceeds the USB-mode0.5-A limit; therefore, V
OUT
drops until the DPPM OUTPUT voltage threshold, or battery voltage, isreached (whichever is higher). If the DPPM OUTPUT threshold is higher, the charging current isreduced to keep the output voltage from dropping further. If the battery voltage is higher, the batterysupplements the current to keep the output from dropping too much (20 mV to 200 mV) below thebattery voltage.
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Test Summary
24. Set JMP2 (MODE) to HI and verify that the input supply is providing ~1.5 A of current (~0.44, for a10- Ωresistor, to the load and 1 A to the battery).25. Set JMP1 to 0.1 on the UUT. Verify that the battery charge has dropped in half. The input currentshould be ~I
BAT
(~0.5 A) + IOUT (~4.4 V/10 Ω= 0.44 A) ≈0.94 A.26. Set JMP1 to 0.5. Continue to let the battery charge. Note that once the battery voltage reachesregulation (~4.2 VDC), the charging current tapers off.27. Verify that the charging terminates when the battery current tapers to C/10 or 100 mA (1 A/10,programmed charge current divided by 10). Verify D2 (STAT1) turns off (High) and D3 (STAT2) turnson (Low).28. If a load is applied across the battery such that the battery is discharged to ~4.1 V, the charger startsa new charging cycle.
This concludes the evaluation of the bq24070 EVM. Several more features implemented in the IC are notdemonstrated in this user's guide. See the data sheet to learn more about thermal regulation, thermalcutoff, USB boot up, and short-circuit protection.
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5 Schematic
S0200-01
Schematic
Figure 2. bq24070 EVM Schematic
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6 Physical Layouts
6.1 Board Layout
K001
2.30
1.79
Physical Layouts
This section contains the board layout and assembly drawings for the EVM.
Figure 3 shows the top assembly view of the EVM. Figure 5 shows the top etch layer of the EVM. Figure 6shows the board second etch layer of the EVM. Figure 7 shows the board third etch layer of the EVM.Figure 8 shows the bottom etch layer of the EVM.
Figure 3. Top Assembly View
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K002
2.30
1.79
K003
2.30
1.79
Physical Layouts
Figure 4. Top Silkscreen
Figure 5. Board Layout – Top Etch Layer
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K004
2.30
1.79
K005
2.30
1.79
Physical Layouts
Figure 6. Board Layout – Second Etch Layer
Figure 7. Board Layout – Third Etch Layer
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K006
2.30
1.79
Physical Layouts
Figure 8. Board Layout – Bottom Etch Layer
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