Texas Instruments VLYNQ Port User manual

TMS320DM644x DMSoCVLYNQ Port
User's Guide
Literature Number: SPRUE36ASeptember 2007

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Contents
Preface ............................................................................................................................... 71 Introduction ................................................................................................................ 91.1 Purpose of the Peripheral ....................................................................................... 91.2 Features ........................................................................................................... 91.3 Functional Block Diagram ..................................................................................... 101.4 Industry Standard(s) Compliance Statement ............................................................... 102 Peripheral Architecture .............................................................................................. 112.1 Clock Control .................................................................................................... 112.2 Signal Descriptions ............................................................................................. 122.3 Pin Multiplexing ................................................................................................. 122.4 Protocol Description ............................................................................................ 122.5 VLYNQ Functional Description ............................................................................... 132.6 Initialization ...................................................................................................... 162.7 Auto-Negotiation ................................................................................................ 162.8 Serial Interface Width Configuration ......................................................................... 162.9 Address Translation ............................................................................................ 172.10 Flow Control ..................................................................................................... 202.11 Reset Considerations .......................................................................................... 212.12 Interrupt Support ................................................................................................ 212.13 DMA Event Support ............................................................................................ 232.14 Power Management ............................................................................................ 242.15 Emulation Considerations ..................................................................................... 243 VLYNQ Port Registers ................................................................................................ 253.1 Revision Register (REVID) .................................................................................... 263.2 Control Register (CTRL) ....................................................................................... 273.3 Status Register (STAT) ........................................................................................ 293.4 Interrupt Priority Vector Status/Clear Register (INTPRI) .................................................. 313.5 Interrupt Status/Clear Register (INTSTATCLR) ............................................................ 313.6 Interrupt Pending/Set Register (INTPENDSET) ............................................................ 323.7 Interrupt Pointer Register (INTPTR) ......................................................................... 323.8 Transmit Address Map Register (XAM)...................................................................... 333.9 Receive Address Map Size 1 Register (RAMS1) .......................................................... 343.10 Receive Address Map Offset 1 Register (RAMO1) ........................................................ 343.11 Receive Address Map Size 2 Register (RAMS2) .......................................................... 353.12 Receive Address Map Offset 2 Register (RAMO2) ........................................................ 353.13 Receive Address Map Size 3 Register (RAMS3) .......................................................... 363.14 Receive Address Map Offset 3 Register (RAMO3) ........................................................ 363.15 Receive Address Map Size 4 Register (RAMS4) .......................................................... 373.16 Receive Address Map Offset 4 Register (RAMO4) ........................................................ 373.17 Chip Version Register (CHIPVER) ........................................................................... 383.18 Auto Negotiation Register (AUTNGO) ....................................................................... 384 Remote Configuration Registers ................................................................................. 39Appendix A VLYNQ Protocol Specifications ........................................................................ 40A.1 Special 8b/10b Code Groups ................................................................................. 40
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A.2 Supported Ordered Sets ....................................................................................... 40A.3 VLYNQ 2.0 Packet Format .................................................................................... 41A.4 VLYNQ 2.X Packets ............................................................................................ 43Appendix B Write/Read Performance .................................................................................. 45B.1 Write Performance.............................................................................................. 45B.2 Read Performance ............................................................................................. 47Appendix C Revision History ............................................................................................. 48
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List of Figures
1 VLYNQ Port Functional Block Diagram ................................................................................. 102 External Clock Block Diagram ............................................................................................ 113 Internal Clock Block Diagram ............................................................................................. 114 VLYNQ Module Structure ................................................................................................. 135 Write Operations ........................................................................................................... 146 Read Operations ........................................................................................................... 157 Example Address Memory Map .......................................................................................... 188 Interrupt Generation Mechanism Block Diagram ....................................................................... 229 Revision Register (REVID) ................................................................................................ 2610 Control Register (CTRL) ................................................................................................... 2711 Status Register (STAT) .................................................................................................... 2912 Interrupt Priority Vector Status/Clear Register (INTPRI) .............................................................. 3113 Interrupt Status/Clear Register (INTSTATCLR) ........................................................................ 3114 Interrupt Pending/Set Register (INTPENDSET) ........................................................................ 3215 Interrupt Pointer Register (INTPTR) ..................................................................................... 3216 Transmit Address Map Register (XAM) ................................................................................. 3317 Receive Address Map Size 1 Register (RAMS1) ...................................................................... 3418 Receive Address Map Offset 1 Register (RAMO1) .................................................................... 3419 Receive Address Map Size 2 Register (RAMS2) ...................................................................... 3520 Receive Address Map Offset 2 Register (RAMO2) .................................................................... 3521 Receive Address Map Size 3 Register (RAMS3) ...................................................................... 3622 Receive Address Map Offset 3 Register (RAMO3) .................................................................... 3623 Receive Address Map Size 4 Register (RAMS4) ...................................................................... 3724 Receive Address Map Offset 4 Register (RAMO4) .................................................................... 3725 Chip Version Register (CHIPVER) ....................................................................................... 3826 Auto Negotiation Register (AUTNGO) ................................................................................... 38A-1 Packet Format (10-bit Symbol Representation) ........................................................................ 41
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List of Tables
1 VLYNQ Port Pins ........................................................................................................... 122 Serial Interface Width ...................................................................................................... 163 Address Translation Example (Single Mapped Region) .............................................................. 184 Address Translation Example (Single Mapped Region) .............................................................. 195 VLYNQ Register Address Space ......................................................................................... 256 VLYNQ Port Controller Registers ........................................................................................ 257 Revision Register (REVID) Field Descriptions ......................................................................... 268 Control Register (CTRL) Field Descriptions ............................................................................ 279 Status Register (STAT) Field Descriptions ............................................................................. 2910 Interrupt Priority Vector Status/Clear Register (INTPRI) Field Descriptions ........................................ 3111 Interrupt Status/Clear Register (INTSTATCLR) Field Descriptions .................................................. 3112 Interrupt Pending/Set Register (INTPENDSET) Field Descriptions ................................................. 3213 Interrupt Pointer Register (INTPTR) Field Descriptions ............................................................... 3214 Address Map Register (XAM) Field Descriptions ...................................................................... 3315 Receive Address Map Size 1 Register (RAMS1) Field Descriptions ................................................ 3416 Receive Address Map Offset 1 Register (RAMO1) Field Descriptions .............................................. 3417 Receive Address Map Size 2 Register (RAMS2) Field Descriptions ................................................ 3518 Receive Address Map Offset 2 Register (RAMO2) Field Descriptions .............................................. 3519 Receive Address Map Size 3 Register (RAMS3) Field Descriptions ................................................ 3620 Receive Address Map Offset 3 Register (RAMO3) Field Descriptions .............................................. 3621 Receive Address Map Size 4 Register (RAMS4) Field Descriptions ................................................ 3722 Receive Address Map Offset 4 Register (RAMO4) Field Descriptions .............................................. 3723 Chip Version Register (CHIPVER) Field Descriptions................................................................. 3824 Auto Negotiation Register (AUTNGO) Field Descriptions ............................................................ 3825 VLYNQ Port Remote Controller Registers .............................................................................. 39A-1 Special 8b/10b Code Groups ............................................................................................. 40A-2 Supported Ordered Sets .................................................................................................. 40A-3 Packet Format (10-bit Symbol Representation) Description .......................................................... 42B-1 Scaling Factors ............................................................................................................. 46B-2 Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ) .................................... 46B-3 Relative Performance with Various Latencies .......................................................................... 47C-1 Document Revision History ............................................................................................... 48
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PrefaceSPRUE36A – September 2007
Read This First
About This Document
This document describes the VLYNQ™ communications interface port in the TMS320DM644x DigitalMedia System-on-Chip (DMSoC).
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas InstrumentsThe following documents describe the TMS320DM644x Digital Media System-on-Chip (DMSoC). Copiesof these documents are available on the Internet at www.ti.com .Tip: Enter the literature number in thesearch box provided at www.ti.com.
The current documentation that describes the DM644x DMSoC, related peripherals, and other technicalcollateral, is available in the C6000 DSP product folder at: www.ti.com/c6000 .
SPRUE14 —TMS320DM644x DMSoC ARM Subsystem Reference Guide. Describes the ARMsubsystem in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The ARM subsystem isdesigned to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM isresponsible for configuration and control of the device; including the DSP subsystem, the videoprocessing subsystem, and a majority of the peripherals and external memories.
SPRUE15 —TMS320DM644x DMSoC DSP Subsystem Reference Guide. Describes the digital signalprocessor (DSP) subsystem in the TMS320DM644x Digital Media System-on-Chip (DMSoC).
SPRUE19 —TMS320DM644x DMSoC Peripherals Overview Reference Guide. Provides an overviewand briefly describes the peripherals available on the TMS320DM644x Digital MediaSystem-on-Chip (DMSoC).
SPRAA84 —TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from theTexas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. Theobjective of this document is to indicate differences between the two cores. Functionality in thedevices that is identical is not included.
SPRU732 —TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPUarchitecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digitalsignal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generationcomprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement ofthe C64x DSP with added functionality and an expanded instruction set.
SPRU871 —TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digitalsignal processor (DSP) megamodule. Included is a discussion on the internal direct memory access(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidthmanagement, and the memory and cache.
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Related Documentation From Texas Instruments
SPRAAA6 —EDMA v3.0 (EDMA3) Migration Guide for TMS320DM644x DMSoC. Describes migratingfrom the Texas Instruments TMS320C64x digital signal processor (DSP) enhanced direct memoryaccess (EDMA2) to the TMS320DM644x Digital Media System-on-Chip (DMSoC) EDMA3. Thisdocument summarizes the key differences between the EDMA3 and the EDMA2 and providesguidance for migrating from EDMA2 to EDMA3.Trademarks
VLYNQ is a trademark of Texas Instruments.
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1 Introduction
1.1 Purpose of the Peripheral
1.2 Features
User's GuideSPRUE36A – September 2007
VLYNQ Port
The VLYNQ™ communications interface port is a low pin count, high-speed, point-to-point serial interfacein the TMS320DM644x Digital Media System-on-Chip (DMSoC) used for connecting to host processorsand other VLYNQ-compatible devices. The VLYNQ port is a full-duplex serial bus where transmit andreceive operations occur separately and simultaneously without interference.
VLYNQ enables the extension of an internal bus segment to one or more external physical devices. Theexternal devices are mapped to local physical address space and appear as if they are on the internal busof the DM644x DMSoC. The external devices must also have a VLYNQ interface.
VLYNQ uses a simple block code (8b/10b) packet format and supports in-band flow control so that noextra terminals are needed to indicate that overflow conditions might occur.
The VLYNQ module on the DM644x DMSoC serializes a write transaction to the remote/external deviceand transfers the write via the VLYNQ port (TX pins). The remote VLYNQ module deserializes thetransaction on the other side.
The read transactions to the remote/external device follow the same process, but the remote device'sVLYNQ module serializes the read return data and transfers it to the VLYNQ port (RX pins). The readreturn data is finally deserialized and released to the device internal bus.
The external device can also initiate read and write transactions.
The general features of the VLYNQ port are:•Low pin count (10 pin interface, scalable to as low as 3 pins)•No tri-state signals– All signals are dedicated and driven by only one device– Necessary to allow support for high-speed PHYs•Scalable Performance
– Programmable frequency and 1 to 4 bits for TX and RX data– Performance increases linearly as the data port width increases•Simple packet-based transfer protocol for memory-mapped access– Write request/data packet– Read request packet– Read response data packet– Interrupt request packet•Auto width negotiation
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1.3 Functional Block Diagram
Slave
config
bus
Interface
Master
config
Interface
bus
VLYNQ module
VLYNQ register
access
CPU/EDMA initiated
transfers to
remote device
Off chip
(remote)
device access
ARM/EDMA
memory
System
VLYNQ_SCRUN
VLYNQ_CLOCK
VLYNQ_RXD[3:0]
VLYNQ_TXD[3:0]
INT31
ARM interrupt
controller
VLQINT
1.4 Industry Standard(s) Compliance Statement
Introduction
•Symmetric Operations– Transmit (TX) pins on the first device connect to the receive (RX) pins on the second device andvice-versa.
– Data pin widths are automatically detected after reset– Re-request packets, response packets, and flow control information are all multiplexed and sentacross the same physical pins.– Supports both host/peripheral and peer-to-peer communication models•Simple block code packet formatting (8b/10b)•Supports in-band and flow control– No extra pins are needed– Allows the receiver to momentarily throttle the transmitter back when overflow is about to occur– Uses the special built-in block code capability to interleave flow control information seamlessly withuser data•Automatic packet formatting optimizations•Internal loopback modes are provided•Connects to legacy VLYNQ devices
Figure 1 shows a functional block diagram of the VLYNQ port.
Figure 1. VLYNQ Port Functional Block Diagram
VLYNQ is an interface defined by Texas Instruments and does not conform to any other industry standard.
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2 Peripheral Architecture
2.1 Clock Control
CLKDIR=0
VLYNQ
DMxxx device
VLYNQ.CLK
CLKDIR=0
VLYNQ
VLYNQ device
CLKDIR=1
VLYNQ
DMxxx device
VLYNQ.CLK
CLKDIR=0
VLYNQ
VLYNQ device
Don't
care
VLYNQ
internal
sys clk
Peripheral Architecture
This section discusses the architecture and basic functions of the VLYNQ peripheral.
The module's serial clock direction and frequency are software configurable through the CLKDIR andCLKDIV bits in the VLYNQ control register (CTRL). The VLYNQ serial clock can be sourced from theinternal system clock (CLKDIR = 1) or by an external clock source (CLKDIR = 0) for its serial operations.
The CLKDIV bit can divide the serial clock (1/1 - 1/8) down when the internal clock is selected as thesource. The serial clock is not affected by the CLKDIV bit values, if the serial clock is externally sourced.
The reset value of the CLKDIR bit is 0 (external clock source).
The external clock source is shown in Figure 2 . The internal clock source is shown in Figure 3 .
Figure 2. External Clock Block Diagram
Figure 3. Internal Clock Block Diagram
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2.2 Signal Descriptions
2.3 Pin Multiplexing
2.4 Protocol Description
Peripheral Architecture
The VLYNQ module on the DM644x device is configurable for a 1 to 4 bit-wide RX/TX. Chip-level pinmultiplexing registers control the configuration. See the pin multiplexing information in the device-specificdata manual.
If the configured width does not match the number of transmit/receive lines that are available on theremote device, negotiation between the two VLYNQ devices automatically configures the width (seeSection 2.7 ).
The VLYNQ interface signals are shown in Table 1 .
Table 1. VLYNQ Port Pins
Pin Name Signal Name I/O Description
VLYNQ_CLOCK VLYNQ serial clock I/O The VLYNQ reference clock supports the internally or externally generatedclock.VLYNQ_SCRUN VLYNQ serial clock I/O The VLYNQ serial clock run request allows remote requests for the VLYNQrun request serial clock to be turned off for system power management.(Active low) Low: The request VLYNQ serial clock is active.High: The VLYNQ serial clock is requested to be high when all transactions arecomplete.VLYNQ_RXD[0:3] VLYNQ receive data I VLYNQ receive data is synchronous with the VLYNQ serial clock.VLYNQ_TXD[0:3] VLYNQ transmit data O VLYNQ transmit data is synchronous with the VLYNQ serial clock.
The VLYNQ signals share pins on the processor package with other processor functions. The VLYNQmodule pins are not enabled at reset. In order to change the default function of device pins at reset, thepin multiplexing registers (PINMUX n) must be configured appropriately. See the pin multiplexinginformation in the device-specific data manual for more detailed information on the processor pinmultiplexing and configuration registers.
VLYNQ relies on 8b/10b block coding to minimize the number of serial pins and allows for in-band packetdelineation and control.
Appendix A provides general information on 8b/10b coding definitions and their implementation within theVLYNQ module in the DM644x device.
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2.5 VLYNQ Functional Description
Address
translation commands
Outbound Outbound
command
FIFO
data
Return
FIFO
data
FIFO
Return
command
Inbound
FIFO
Registers
translation
Address
TxSM 8B/10B
encoding Serializer
commands
Inbound RxSM Deserializer
decoding
8B/10B
Serial
TxData
Serial
TxClk
Serial
RxClk
Serial
RxData
Master
config bus
interface
System clock VLYNQ clock
Slave
config bus
interface
(FIFO3)
(FIFO2)
(FIFO0)
(FIFO1)
Peripheral Architecture
The VLYNQ core supports both host-to-peripheral and peer-to-peer communication models and issymmetrical. The VLYNQ module structure is shown in Figure 4 .
Figure 4. VLYNQ Module Structure
The VLYNQ core module implements two 32-bit configuration bus interfaces. Transmit operations andcontrol register access require the slave configuration bus interface. The master configuration businterface is required for receive operations. Converting to and from the 32-bit bus to the external serialinterface requires serializer and deserializer blocks.
8b/10b block coding encodes data on the serial interface. Frame delineation, initialization, and flow controluse special overhead code groups.
FIFOs buffer the entire burst on the bus for maximum performance, thus minimizing bus latency. Usingwrite operations of each VLYNQ module interfaced is typically recommended to ensure the bestperformance on both directions of the link.
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2.5.1 Write Operations
Address
translation commands
Outbound Outbound
command
FIFO
data
Return
FIFO
data
FIFO
Return
command
Inbound
FIFO
Registers
translation
Address
TxSM 8B/10B
encoding Serializer
commands
Inbound RxSM Deserializer
decoding
8B/10B
Serial
TxData
Serial
RxData
System clock
Address
translation
Registers
commands
Inbound
translation
Address
commands
Outbound
8B/10B
decoding
FIFO
FIFO
command
Inbound
data
Return
FIFO
RxSM Deserializer
RxData
Serial
encoding
8B/10B
VLYNQ Clock
command
Return
data
FIFO
Outbound
TxSM Serializer
TxData
Serial
Slave
config bus
interface
System clock VLYNQ clock
Local VLYNQ
Remote VLYNQ
Master
config bus
interface
Master
config bus
interface
Slave
config bus
interface
Peripheral Architecture
Write requests that initiate from the slave configuration bus interface of the local device write to theoutbound command (CMD) FIFO. Data is subsequently read from the FIFO and encapsulated in a writerequest packet. The address is translated, and the packet is encoded and serialized before beingtransmitted to remote device. The remote device subsequently deserializes and decodes the receive dataand writes it into the inbound CMD FIFO. A write operation initiates on the remote device’s masterconfiguration bus interface after reading the address and data from the FIFO.
The data flow between two VLYNQs that are connected is shown in Figure 5 . In the example shown inFigure 5 , the write originates from the DM644x device.
Figure 5. Write Operations
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2.5.2 Read Operations
Address
translation commands
Outbound Outbound
command
FIFO
data
Return
FIFO
data
FIFO
Return
command
Inbound
FIFO
Registers
translation
Address
TxSM 8B/10B
encoding Serializer
commands
Inbound RxSM Deserializer
decoding
8B/10B
Serial
TxData
Serial
RxData
System clock
Address
translation
Registers
commands
Inbound
translation
Address
commands
Outbound
8B/10B
decoding
FIFO
FIFO
command
Inbound
data
Return
FIFO
RxSM Deserializer
RxData
Serial
encoding
8B/10B
VLYNQ Clock
command
Return
data
FIFO
Outbound
TxSM Serializer
TxData
Serial
Slave
config bus
interface
VLYNQ Clock
System clock
Local VLYNC
Remote VLYNQ
Master
config bus
interface
Slave
config bus
interface
Master
config bus
interface
Peripheral Architecture
Read requests from the slave configuration bus interface are written to the outbound CMD FIFO (similar tothe write requests). Data is subsequently read from the FIFO and encapsulated into a read requestpacket. The packet is encoded and serialized before it is transmitted to the remote device. Next, theremote device deserializes, decodes the receive data, and writes the receive data to the inbound CMDFIFO. After reading the address from the FIFO, a master configuration bus interface read operationinitiates in the remote device. When the remote master configuration bus interface receives the read data,the data is written to the return data FIFO before it is encoded and serialized. When the receive datareaches the local VLYNQ module, it is deserialized, decoded, and written to the return data FIFO (localdevice). Finally, the read data is transferred on the local device’s slave configuration interface.
The data flow between two connected VLYNQ devices with read requests that originate from the DM644xdevice is shown in Figure 6 . The remote VLYNQ device returns the read data. Read data is shown withdotted arrows.
Figure 6. Read Operations
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2.6 Initialization
2.7 Auto-Negotiation
2.8 Serial Interface Width Configuration
Peripheral Architecture
Note: Not servicing read operations results in deadlock. The only way to recover from a deadlocksituation is to perform a hard reset. Read operations are typically not serviced due to readrequests that are issued to a non-existent remote VLYNQ device or they are not serviceddue to trying to perform reads on the VLYNQ memory map prior to establishing the link.
Generally, you should not use read operations to transfer data packets since the serial nature of theinterface could potentially result in longer latencies. See Appendix B for more information.
Since VLYNQ devices can be controlled solely over the serial interface (that is, no local CPU exists), anautomatic reliable initialization sequence (without user configuration) establishes a connection betweentwo VLYNQ devices, just after a VLYNQ module is enabled and auto-negotiation occurs. Auto-negotiationis defined in Section 2.7 . The same sequence is used to recover from error conditions.
Bit 0 in the VLYNQ status register (LINK bit) is set to 1 when a link is established.
A link pulse timer generates a periodic link code every 2048 serial clock cycles. The link is lost when timeexpires and no link code has been detected during a period of 4096 serial clock cycles.
Auto-negotiation occurs after reset. It involves placing a negotiation protocol in the outbound data andprocessing the inbound data to establish connection information. The width of the data pins on the serialinterface is automatically determined at reset as a part of the initialization sequence. For a connectionbetween two VLYNQ devices of version 2.0 and later (VLYNQ on DM644x device is version 2.6), thenegotiation protocol using the available serial pins is used to convey the maximum width capability of eachdevice. The TXD data pins are not required to have the same width as the RXD data pins.
The auto width negotiation does not occur until after completion of the VLYNQ 1.x legacy widthconfiguration, which involves a period of 2000 VLYNQ 1.x system clock cycles for connection to VLYNQ1.x devices. After the VLYNQ 1.x has determined its width, it receives the VLYNQ2.x auto widthnegotiation protocol. The VLYNQ 1.x device does not recognize this protocol and transmits error codesover the serial interface. The received error codes allow the VLYNQ 2.x devices to determine how manyserial pins are valid on the connected VLYNQ 1.x device.
Once the width is established, VLYNQ further identifies the version (version 1.x or version 2.x ) of theremote VLYNQ. This better determines the capabilities of the connected VLYNQ device. This is softwarereadable via the VLYNQ auto-negotiation register (AUTNGO), bit 16 (0 = Ver 1.x , 1 = Ver 2.x), after thelink has been established.
The VLYNQWD bit in the pin multiplexing register 0 (PINMUX0) controls the data width on the DM644xdevice, thus allowing you to program the serial interface width (as shown in Table 2 ).
Table 2. Serial Interface Width
VLYNQWD VLYNQ Data Width
00 VLYNQ TXD[0] , VLYNQ RXD[0]01 VLYNQ TXD[0:1] , VLYNQ RXD[0:1]11 VLYNQ TXD[0:2] , VLYNQ RXD[0:2]10 VLYNQ TXD[0:3] , VLYNQ RXD[0:3]
For detailed information on the processor pin multiplexing and configuration register, see the pinmultiplexing information in the device-specific data manual.
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2.9 Address Translation
Peripheral Architecture
Remote VLYNQ device(s) are memory mapped to the local (host) device’s address space when a link isestablished (this is similar to any other on-chip peripherals). Enumerating the VLYNQ devices (single ormultiple) into a coherent memory map for accessing each device is part of the initialization sequence.
After the enumeration, the host (local) device can access the remote device address map using localdevice addresses. The VLYNQ module in the host device manages the address translation of the localaddress to the remote address. A remote VLYNQ device is mapped to the local device’s address via theaddress map registers (TX address map, RX address map size n, RX address map offset n, where n= 1to 4). The transmit side has a contiguous map; the size of the map is the same as the remote device map.Figure 7 illustrates this mapping.
In the local device, the address of the VLYNQ remote memory map in the local configuration space is thetransmit address accessing remote devices over the serial interface. The address of the VLYNQ remotememory map is programmed in the TX address map register (XAM). When the local device transmits, firstit strips off the transmit address offset in the local device memory map. Then, the local device sends thedata with an address offset from the transmit address.
VLYNQ allows each receive packet address to be translated into one of the four mapped regions. The sizeand offset of each memory region must be aligned to 32-bit words. No restriction is placed onprogramming the size or on the offset of each mapped region, as long as the total memory that is mappedinto these one to four regions is not more then 64 MBytes.
Note: Care should be taken while programming the receive address map size register (RAMS n)and the receive address map offset register (RAMO n) values. These registers should beprogrammed with valid address locations and memory size to match the devicespecifications. See the Memory Map Summary and the System Interconnect sections in yourdevice-specific data manual to identify the valid memory regions that can be accessed by anoff-chip peer device through the VLYNQ interface.
The transmitted address is used to determine which remote mapped region is being accessed at theremote device. This is achieved by summing each memory size sequentially until the memory size islarger than the transmitted address. The last memory size that is added is the targeted region. A memorysize and an offset specify the remote map. The remote map is programmed in the RX address map sizeregister (RAMS n) and in the RX address map offset register (RAMO n) in the remote device.
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Map region 1
Map region 2
Map region 3
Map region 4
0400:0000
(0C00:0000 on CONFIG bus)
0800:0000
07FF:FFFF
0800:0100
0800:00FF
0801:0100
0801:00FF
0841:00FF
Map region 1
Map region 2
Map region 3
Map region 4
DMxxx device (local)
Remote
VLYNQ device
0000:0000
03FF:FFFF
0400:0000
0400:00FF
0500:0000
0500:FFFF
0B00:0000
0B3F:FFFF
Peripheral Architecture
Figure 7. Example Address Memory Map
The following shows an example illustrating the address translation used in each VLYNQ module.
Address bits [31:26] are not used for address translation to remote devices on the DM644x device.
Table 3 illustrates address map register configuration when the DM644x device is transmitting data to theremote device.
Table 3. Address Translation Example (Single Mapped Region)
Register DM644x VLYNQ Module Remote VLYNQ Module
TX Address Map 0000 : 0000h Do not careRX Address Map Size 1 Do not care 0000 : 0100hRX Address Map Offset 1 Do not care 0800 : 0000h
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Peripheral Architecture
DM644x VLYNQ Module:
0C00 : 0054h Initial address at the slave configuration bus0000 : 0054h Initial address [25:0] at the slave configuration bus interfacesubtract 0000 : 0000h TX address map register (there is no need to change the reset value of theDM644x device for this register)0000 : 0054h
Remote VLYNQ Module:
0000 : 0054h Initial address from the RX serial interfacecompare 0000 : 0100h RX address map size 1 register0000 : 0054hadd 0800 : 0000h RX address map offset 1 register0800 : 0054h Translated address to remote device
The local address 0C00 : 0054h (or 0000 0054h) was translated to 0800 : 0054h on the remote VLYNQdevice in Table 4 .
Table 4 illustrates the address map register configuration when the DM644x device is receiving data fromthe remote device.
Table 4. Address Translation Example (Single Mapped Region)
Register DM644x VLYNQ Module Remote VLYNQ Module
TX Address Map Do not care 0400 : 0000hRX Address Map Size 1 0000 : 0100h Do not careRX Address Map Offset 1 0200 : 0000h Do not careRX Address Map Size 2 0000 : 0100h Do not careRX Address Map Offset 2 8200 : 0000h Do not care
Remote VLYNQ Module:
0400 : 0154h Initial address at the slave configuration bus for the remote devicesubtract 0400 : 0000h TX address map register0000 : 0154h Translated address to remote device via serial interface
DM644x VLYNQ Module:
0000 : 0154h Initial address from the RX serial interfacecompare 0000 : 0100h RX address map size 1 register0000 : 0154h The RX packet address is greater than the value in the RX address map size 1registercompare 0000 : 0200h RX address map size 1 register + RX address map size 2Since the RX packet address < the RX address map size 1 register +RX address map size 2 registeradd 8200 : 0000h RX address map offset 2 registersubtract 0000 : 0100h RX address map size 1 register8200 : 0054h Translated address to DM644x device
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2.10 Flow Control
Peripheral Architecture
Example 1. Address Translation Example
The remote address 0x 0400 : 0154 (or 0x0000 0054) was translated to 0x 8200 : 0054 on the DM644x(local) device in this example.
The translated address for packets received on the serial interface is determined as follows:
If ( RX Packet Address < RX Address Map Size 1 Register) {Translated Address = RX Packet Address +RX Address Map Offset 1 Register
} else if ( RX Packet Address < (RX Address Map Size 1 Register +RX Address Map Size 2 Register)) {Translated Address = RX Packet Address +RX Address Map Offset 2 Register -RX Address Map Size 1 Register} else if ( RX Packet Address < (RX Address Map Size 1 Register +RX Address Map Size 2 Register +RX Address Map Size 3 Register)) {Translated Address = RX Packet Address +RX Address Map Offset 3 Register -RX Address Map Size 1 Register -RX Address Map Size 2 Register
} else if ( RX Packet Address < (RX Address Map Size 1 Register +RX Address Map Size 2 Register +RX Address Map Size 3 Register +RX Address Map Size 4 Register)) {Translated Address = RX Packet Address +RX Address Map Offset 4 Register -RX Address Map Size 1 Register -RX Address Map Size 2 Register -RX Address Map Size 3 Register} else {Translated Address = 0x0
}
The VLYNQ module includes flow control features. The VLYNQ module automatically generates flowcontrol enable requests, /P/, when the RX/inbound FIFOs (FIFO1 and FIFO2) resources are consumed.The FIFOs can take up to 16 32-bit words.
The remote device will begin transmitting idles, /I/, starting on the first byte boundary following reception ofthe request. When sufficient RX FIFO resources have been made available, a flow control disable request,/C/, is transmitted to the remote device. In response, the remote device will resume transmission of data.See Appendix A .
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