Texas Instruments TRF7964A User manual

Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
TRF7964A
SLOS787H –MAY 2012–REVISED APRIL 2014
TRF7964A Multiprotocol Fully Integrated 13.56-MHz RFID Reader and Writer IC
1 Device Overview
1.1 Features
1
• Completely Integrated Protocol Handling for • Integrated Voltage Regulator Output for Other
ISO15693, ISO18000-3, ISO14443A/B, and System Components (MCU, Peripherals,
FeliCa™ Indicators), 20 mA (Max)
• Integrated State Machine for ISO14443A • Programmable Modulation Depth
Anticollision (Broken Bytes) Operation • Dual Receiver Architecture With RSSI for
• Input Voltage Range: 2.7 VDC to 5.5 VDC Elimination of "Read Holes" and Adjacent Reader
System or Ambient In-Band Noise Detection
• Programmable Output Power: +20 dBm (100 mW),
+23 dBm (200 mW) • Programmable Power Modes for Ultra Low-Power
System Design (Power Down <1 µA)
• Programmable I/O Voltage Levels From 1.8 VDC
to 5.5 VDC • Parallel or SPI Interface (With 127-Byte FIFO)
• Programmable System Clock Frequency Output • Temperature Range: –40°C to 110°C
(RF, RF/2, RF/4) from 13.56-MHz or 27.12-MHz • 32-Pin QFN Package (5 mm x 5 mm)
Crystal or Oscillator
1.2 Applications
• Public Transport or Event Ticketing • Medical Equipment or Consumables
• Passport or Payment (POS) Reader Systems • Access Control, Digital Door Locks
• Product Identification or Authentication
1.3 Description
The TRF7964A device is an integrated analog front end and data-framing device for a 13.56-MHz RFID
system. Built-in programming options make the device suitable for a wide range of applications for
proximity and vicinity identification systems.
Built-in user-configurable programming options make the device suitable for a wide range of applications.
The TRF7964A device is configured by selecting the desired protocol in the control registers. Direct
access to all control registers allows fine tuning of various reader parameters as needed.
Documentation, reference designs, EVM, and source code TI MSP430™ MCUs or ARM®MCUs are
available.
Device Information
PART NUMBER PACKAGE BODY SIZE
TRF7964ARHB VQFN (32) 5 mm x 5 mm
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

MUX
RX_IN1
RX_IN2
PHASE&
AMPLITUDE
DETECTOR
GAIN RSSI
(AUX)
LOGIC
LEVEL SHIFTER
STATE
CONTROL
LOGIC
[CONTROL
REGISTERS &
COMMAND
LOGIC]
127-BYTE
FIFO
MCU
INTERFACE
VDD_I/O
I/O_0
I/O_1
I/O_2
I/O_3
I/O_4
I/O_5
I/O_6
I/O_7
IRQ
SYS_CLK
DATA _CLK
ISO
PROTOCOL
HANDLING DECODER
RSSI
(EXTERNAL)
PHASE&
AMPLITUDE
DETECTOR
GAIN
RSSI
(MAIN)
FILTER
& AGC DIGITIZER
BIT
FRAMING
FRAMING
SERIAL
CONVERSION
CRC & PARITY
TRANSMITTER ANALOG
FRONT END
TX_OUT
VDD_PA
VSS_PA
DIGITAL CONTROL
STATE MACHINE
CRYSTAL OR OSCILLATOR
TIMING SYSTEM
EN
EN2
ASK/OOK
MOD
OSC_IN
OSC_OUT
VOLTAGE SUPPLY REGULATOR SYSTEMS
(SUPPLY REGULATORS AND REFERENCE VOLTAGES)
VSS_A
VSS_RF
VDD_RF
VDD_X
VSS_D
VSS
VIN
VDD_A
BAND_GAP
RF LEVEL
DETECTOR
TRF7964A
SLOS787H –MAY 2012–REVISED APRIL 2014 www.ti.com
1.4 Functional Block Diagram
Figure 1-1 shows the block diagram.
Figure 1-1. Block Diagram
2Device Overview Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TRF7964A

TRF7964A
www.ti.com SLOS787H –MAY 2012–REVISED APRIL 2014
Table of Contents
1 Device Overview ......................................... 16.7 Transmitter – Analog Section ....................... 25
1.1 Features .............................................. 16.8 Transmitter – Digital Section........................ 26
6.9 Transmitter – External Power Amplifier and
1.2 Applications........................................... 1Subcarrier Detector ................................. 26
1.3 Description............................................ 16.10 TRF7964A IC Communication Interface ............ 28
1.4 Functional Block Diagram ............................ 26.11 Special Direct Mode for Improved MIFARE™
2 Revision History ......................................... 4Compatibility......................................... 46
3 Device Characteristics.................................. 56.12 Direct Commands from MCU to Reader ............ 46
4 Terminal Configuration and Functions.............. 66.13 Register Description................................. 50
4.1 Pin Assignments...................................... 67 Application Schematic and Layout
4.2 Terminal Functions ................................... 7Considerations.......................................... 68
5 Specifications ............................................ 97.1 TRF7964A Reader System Using Parallel
Microcontroller Interface............................. 68
5.1 Absolute Maximum Ratings .......................... 97.2 TRF7964A Reader System Using SPI With SS
5.2 Recommended Operating Conditions................ 9Mode ................................................ 69
5.3 Electrical Characteristics............................ 10 7.3 Layout Considerations .............................. 70
5.4 Handling Ratings.................................... 11 7.4 Impedance Matching TX_Out (Pin 5) to 50 Ω...... 70
5.5 Thermal Characteristics............................. 11 7.5 Reader Antenna Design Guidelines ................ 72
5.6 Switching Characteristics ........................... 11 8 Device and Documentation Support ............... 73
6 Detailed Description ................................... 12 8.1 Community Resources.............................. 73
6.1 Overview ............................................ 12 8.2 Trademarks.......................................... 73
6.2 System Block Diagram.............................. 13 8.3 Electrostatic Discharge Caution..................... 73
6.3 Power Supplies...................................... 13 8.4 Glossary............................................. 73
6.4 Receiver – Analog Section.......................... 19 9 Mechanical Packaging and Orderable
6.5 Receiver – Digital Section........................... 20 Information .............................................. 73
6.6 Oscillator Section ................................... 24 9.1 Packaging Information .............................. 73
Copyright © 2012–2014, Texas Instruments Incorporated Table of Contents 3
Submit Documentation Feedback
Product Folder Links: TRF7964A

TRF7964A
SLOS787H –MAY 2012–REVISED APRIL 2014 www.ti.com
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (February 2014) to Revision H Page
• Changed Figure 1-1 to show 127-byte FIFO...................................................................................... 2
• Moved Section 3 ...................................................................................................................... 5
• Changed title of Section 4 .......................................................................................................... 6
• Changed title of Section 5 ........................................................................................................... 9
• Added ASK/OOK and MOD to VIL and VIH ........................................................................................ 9
• Moved Section 5.3 .................................................................................................................. 10
• Changed VDD_A TYP value from 3.5 V to 3.4 V ................................................................................. 10
• Moved Section 5.4 .................................................................................................................. 11
• Added V(ESD) MIN values, test specifications, and notes....................................................................... 11
• Changed title of Section 5.5 from Dissipation Ratings to Thermal Characteristics......................................... 11
• Moved Section 5.6 .................................................................................................................. 11
• Changed title of Section 6.......................................................................................................... 12
• Moved previous Section 3, Device Overview, to Section 6.1.................................................................. 12
• Changed from "By default, the AGC is frozen after..." to "By default, the AGC window comparator is set after..." ... 19
• Changed from "TX Pulse Length Control register (0x05)" to "TX Pulse Length Control register (0x06)" ............... 25
• Changed from "18.8 s" to "18.8 µs" in the sentence that starts with "If the register contains all zeros..."............... 25
• Changed command 0x18 to "Test internal RF" ................................................................................. 46
• Changed command 0x19 to "Test external RF" ................................................................................ 46
• Moved Section 6.13................................................................................................................. 50
• Changed the sentence that starts "The AGC action is fast..." from "finishes after four subcarrier pulses" to
"finishes within eight subcarrier pulses" ......................................................................................... 59
• Moved Section 7..................................................................................................................... 68
• Deleted previous Section 10, System Design, and moved contents to Section 7.3 through Section 7.5 ............... 70
• Removed references to figure numbers in Figure 7-3.......................................................................... 71
4Revision History Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TRF7964A

TRF7964A
www.ti.com SLOS787H –MAY 2012–REVISED APRIL 2014
3 Device Characteristics
Table 3-1 shows the supported modes of operation for the TRF7964A device.
Table 3-1. Supported Protocols
Supported Protocols
ISO-14443A/B FeliCa
ISO-15693,
Device ISO-18000-3 212 kbps,
106 kbps 212 kbps 424 kbps 848 kbps (Mode 1) 424 kbps
TRF7964A √√√√√√
Copyright © 2012–2014, Texas Instruments Incorporated Device Characteristics 5
Submit Documentation Feedback
Product Folder Links: TRF7964A

VDD_A
VIN
VDD_RF
VDD_PA
TX_OUT
VSS_PA
VSS_RX
RX_IN1
I/0_7
RX_IN2 VSS BG
ASK/OOK
IRQ MOD VSS_A VDD_I/O
Pad
VDD_X
OSC_IN
OSC_OUT
VSS_D
EN
SYS_CLK
DATA_CLK
EN2
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
I/0_6
I/0_5
I/0_4
I/0_3
I/0_2
I/0_1
I/0_0
TRF7964A
SLOS787H –MAY 2012–REVISED APRIL 2014 www.ti.com
4 Terminal Configuration and Functions
4.1 Pin Assignments
Figure 4-1 shows the pin assignments for the 32-pin RHB package.
Figure 4-1. 32-Pin RHB Package (Top View)
6Terminal Configuration and Functions Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TRF7964A

TRF7964A
www.ti.com SLOS787H –MAY 2012–REVISED APRIL 2014
4.2 Terminal Functions
Table 4-1 describes the signals.
Table 4-1. Terminal Functions
TERMINAL TYPE (1) DESCRIPTION
NAME NO.
VDD_A 1 OUT Internal regulated supply (2.7 V to 3.4 V) for analog circuitry
VIN 2 SUP External supply input to chip (2.7 V to 5.5 V)
VDD_RF 3 OUT Internal regulated supply (2.7 V to 5 V), normally connected to VDD_PA (pin 4)
VDD_PA 4 INP Supply for PA; normally connected externally to VDD_RF (pin 3)
TX_OUT 5 OUT RF output (selectable output power, 100 mW or 200 mW, with VDD = 5 V)
VSS_PA 6 SUP Negative supply for PA; normally connected to circuit ground
VSS_RX 7 SUP Negative supply for RX inputs; normally connected to circuit ground
RX_IN1 8 INP Main RX input
RX_IN2 9 INP Auxiliary RX input
VSS 10 SUP Chip substrate ground
BAND_GAP 11 OUT Bandgap voltage (VBG = 1.6 V); internal analog voltage reference
Selection between ASK and OOK modulation (0 = ASK, 1 = OOK) for Direct Mode 0 or 1.
ASK/OOK 12 BID Can be configured as an output to provide the received analog signal output.
IRQ 13 OUT Interrupt request
INP External data modulation input for Direct Mode 0 or 1
MOD 14 OUT Subcarrier digital data output (see registers 0x1A and 0x1B)
VSS_A 15 SUP Negative supply for internal analog circuits; connected to GND
VDD_I/O 16 INP Supply for I/O communications (1.8 V to VIN) level shifter. VIN should be never exceeded.
I/O_0 17 BID I/O pin for parallel communication
I/O_1 18 BID I/O pin for parallel communication
I/O pin for parallel communication
I/O_2 19 BID TX Enable (in Special Direct Mode)
I/O pin for parallel communication
I/O_3 20 BID TX Data (in Special Direct Mode)
I/O pin for parallel communication
I/O_4 21 BID Slave Select signal in SPI mode
I/O pin for parallel communication
I/O_5 22 BID Data clock output in Direct Mode 1 and Special Direct Mode
I/O pin for parallel communication
I/O_6 23 BID MISO for serial communication (SPI)
Serial bit data output in Direct Mode 1 or subcarrier signal in Direct Mode 0
I/O pin for parallel communication.
I/O_7 24 BID MOSI for serial communication (SPI)
Selection of power down mode. If EN2 is connected to VIN, then VDD_X is active during power
EN2 25 INP down mode 2 (for example, to supply the MCU).
DATA_CLK 26 INP Data Clock input for MCU communication (parallel and serial)
If EN = 1 (EN2 = don't care) the system clock for MCU is configured. Depending on the crystal
that is used, options are as follows (see register 0x09):
SYS_CLK 27 OUT 13.56-MHz crystal: Off, 3.39 MHz, 6.78 MHz, or 13.56 MHz
27.12-MHz crystal: Off, 6.78 MHz, 13.56 MHz, or 27.12 MHz
If EN = 0 and EN2 = 1, then system clock is set to 60 kHz
EN 28 INP Chip enable input (If EN = 0, then chip is in sleep or power-down mode).
VSS_D 29 SUP Negative supply for internal digital circuits
(1) SUP = Supply, INP = Input, BID = Bidirectional, OUT = Output
Copyright © 2012–2014, Texas Instruments Incorporated Terminal Configuration and Functions 7
Submit Documentation Feedback
Product Folder Links: TRF7964A

TRF7964A
SLOS787H –MAY 2012–REVISED APRIL 2014 www.ti.com
Table 4-1. Terminal Functions (continued)
TERMINAL TYPE (1) DESCRIPTION
NAME NO.
OSC_OUT 30 OUT Crystal or oscillator output
INP Crystal or oscillator input
OSC_IN 31 OUT Crystal oscillator output
Internally regulated supply (2.7 V to 3.4 V) for digital circuit and external devices (for example,
VDD_X 32 OUT MCU)
Thermal Pad PAD SUP Chip substrate ground
8Terminal Configuration and Functions Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TRF7964A

TRF7964A
www.ti.com SLOS787H –MAY 2012–REVISED APRIL 2014
5 Specifications
5.1 Absolute Maximum Ratings (1) (2)
over operating free-air temperature range (unless otherwise noted)
VIN Input voltage range -0.3 V to 6 V
IIN Maximum current VIN 150 mA
Any condition 140°C
TJMaximum operating virtual junction temperature Continuous operation, long-term reliability (3) 125°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Operating Conditions are not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to substrate ground terminal VSS.
(3) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability or lifetime of the device.
5.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT
VIN Operating input voltage 2.7 5 5.5 V
TAOperating ambient temperature -40 25 110 °C
TJOperating virtual junction temperature -40 25 125 °C
I/O lines, IRQ, SYS_CLK, DATA_CLK, 0.2 x
VIL Input voltage - logic low V
EN, EN2, ASK/OOK, MOD VDD_I/O
I/O lines, IRQ, SYS_CLK, DATA_CLK, 0.8 x
VIH Input voltage threshold, logic high V
EN, EN2, ASK/OOK, MOD VDD_I/O
Copyright © 2012–2014, Texas Instruments Incorporated Specifications 9
Submit Documentation Feedback
Product Folder Links: TRF7964A

TRF7964A
SLOS787H –MAY 2012–REVISED APRIL 2014 www.ti.com
5.3 Electrical Characteristics
TYP operating conditions are TA= 25°C, VIN = 5 V, full-power mode (unless otherwise noted)
MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
All building blocks disabled, including supply-
IPD1 Supply current in Power Down Mode 1 voltage regulators; measured after 500-ms 0.5 5 µA
settling time (EN = 0, EN2 = 0)
The SYS_CLK generator and VDD_X remain
Supply current in Power Down Mode 2
IPD2 active to support external circuitry; measured 120 200 µA
(Sleep Mode) after 100-ms settling time (EN = 0, EN2 = 1)
Oscillator running, supply-voltage regulators in
ISTBY Supply current in stand-by mode 1.9 3.5 mA
low-consumption mode (EN = 1, EN2 = x)
Supply current without antenna driver Oscillator, regulators, RX and AGC active, TX
ION1 10.5 14 mA
current is off
Oscillator, regulators, RX and AGC and TX
ION2 Supply current – TX (half power) 70 78 mA
active, POUT = 100 mW
Oscillator, regulators, RX and AGC and TX
ION3 Supply current – TX (full power) 130 150 mA
active, POUT = 200 mW
VPOR Power-on reset voltage Input voltage at VIN 1.4 2 2.6 V
VBG Bandgap voltage (pin 11) Internal analog reference voltage 1.5 1.6 1.7 V
Regulated output voltage for analog
VDD_A VIN = 5 V 3.1 3.4 3.8 V
circuitry (pin 1)
VDD_X Regulated supply for external circuitry Output voltage pin 32, VIN = 5 V 3.1 3.4 3.8 V
IVDD_Xmax Maximum output current of VDD_X Output current pin 32, VIN = 5 V 20 mA
Half-power mode, VIN = 2.7 V to 5.5 V 8 12
RRFOUT Antenna driver output resistance (1) Ω
Full-power mode, VIN = 2.7 V to 5.5 V 4 6
RRFIN RX_IN1 and RX_IN2 input resistance 4 10 20 kΩ
Maximum RF input voltage at RX_IN1 and
VRF_INmax VRF_INmax should not exceed VIN 3.5 Vpp
RX_IN2 fSUBCARRIER= 424 kHz 1.4 2.5
Minimum RF input voltage at RX_IN1 and
VRF_INmin mVpp
RX_IN2 (input sensitivity)(2) fSUBCARRIER = 848 kHz 2.1 3
fSYS_CLK SYS_CLK frequency In power mode 2, EN = 0, EN2 = 1 25 60 120 kHz
fCCarrier frequency Defined by external crystal 13.56 MHz
Time until oscillator stable bit is set (register
tCRYSTAL Crystal run-in time 3 ms
0x0F)(3)
Depends on capacitive load on the I/O lines,
fD_CLKmax Maximum DATA_CLK frequency(4) 2 8 10 MHz
recommendation is 2 MHz(4)
ROUT Output resistance I/O_0 to I/O_7 500 800 Ω
RSYS_CLK Output resistance RSYS_CLK 200 400 Ω
(1) Antenna driver output resistance
(2) Measured with subcarrier signal at RX_IN1 or RX_IN2 and measured the digital output at MOD pin with register 0x1A bit 6 = 1.
(3) Depends on the crystal parameters and components
(4) Recommended DATA_CLK speed is 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not
exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output
resistance of 400 Ω(12-ns time constant when 30-pF load used).
10 Specifications Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TRF7964A

TRF7964A
www.ti.com SLOS787H –MAY 2012–REVISED APRIL 2014
5.4 Handling Ratings
MIN MAX UNIT
TSTG Storage temperature range -55 150 °C
V(ESD) Electrostatic discharge Human-Body Model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) -2 2 kV
Charged-Device Model (CDM), per JEDEC specification JESD22-C101, -500 500 V
all pins(2)
Machine Model (MM) -200 200 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 2 kV
may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 500 V
may actually have higher performance.
5.5 Thermal Characteristics
POWER RATING(2)
PACKAGE θJC θJA(1) TA≤25°C TA≤85°C
RHB (32 pin) 31°C/W 36.4°C/W 2.7 W 1.1 W
(1) This data was taken using the JEDEC standard high-K test PCB.
(2) Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to increase substantially.
Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-
term reliability.
5.6 Switching Characteristics
TYP operating conditions are TA= 25°C, VIN = 5 V, full-power mode (unless otherwise noted)
MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DATA_CLK time high or low, one half of
tLO/HI Depends on capacitive load on the I/O lines(1) 250 62.5 50 ns
DATA_CLK at 50% duty cycle
Slave select lead time, slave select low to
tSTE,LEAD 200 ns
clock
Slave select lag time, last clock to slave
tSTE,LAG 200 ns
select high
Slave select disable time, slave select
tSTE,DIS rising edge to next slave select falling 300 ns
edge
tSU,SI MOSI input data setup time 15 ns
tHD,SI MOSI input data hold time 15 ns
tSU,SO MISO input data setup time 15 ns
tHD,SO MISO input data hold time 15 ns
tVALID,SO MISO output data valid time DATA_CLK edge to MISO valid, CL≤30 pF 30 50 75 ns
(1) Recommended DATA_CLK speed is 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not
exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output
resistance of 400 Ω(12-ns time constant when 30-pF load used).
Copyright © 2012–2014, Texas Instruments Incorporated Specifications 11
Submit Documentation Feedback
Product Folder Links: TRF7964A

TRF7964A MCU
(MSP430 or ARM)
Matching
VDD_X VDD_I/O
TX_OUT
RX_IN 1
RX_IN2 VSS VIN
Parallel
or SPI
Supply: 2.7 V – 5.5 V
VDD
VDD
Crystal
13.56 MHz
XIN
TRF7964A
SLOS787H –MAY 2012–REVISED APRIL 2014 www.ti.com
6 Detailed Description
6.1 Overview
6.1.1 RFID – Reader and Writer
The is a high performance 13.56-MHz HF RFID Transceiver IC composed of an integrated analog front
end (AFE) and a built-in data framing engine for ISO15693, ISO14443A/B, and FeliCa. This includes data
rates up to 848 kbps for ISO14443 with all framing and synchronization tasks on board (in default mode).
This architecture enables the customer to build a complete cost-effective yet high-performance multi-
protocol 13.56-MHz RFID system together with a low-cost microcontroller.
Other standards and even custom protocols can be implemented by using either of the Direct Modes that
the device offers. These Direct Modes (0 and 1) allow the user to fully control the analog front end (AFE)
and also gain access to the raw subcarrier data or the unframed but already ISO formatted data and the
associated (extracted) clock signal.
The receiver system has a dual input receiver architecture. The receivers also include various automatic
and manual gain control options. The received input bandwidth can be selected to cover a broad range of
input subcarrier signal options.
The received signal strength from transponders, ambient sources, or internal levels is available through
the RSSI register. The receiver output is selectable among a digitized subcarrier signal and any of the
integrated subcarrier decoders. The selected subcarrier decoder delivers the data bit stream and the data
clock as outputs.
The TRF7964A also includes a receiver framing engine. This receiver framing engine performs the CRC
or parity check, removes the EOF and SOF settings, and organizes the data in bytes for ISO14443A/B,
ISO15693, and FeliCa protocols. Framed data is then accessible to the microcontroller (MCU) through a
127-byte FIFO register.
Figure 6-1. Application Block Diagram
A parallel or serial interface (SPI) can be used for the communication between the MCU and the
TRF7964A reader. When the built-in hardware encoders and decoders are used, transmit and receive
functions use a 127-byte FIFO register. For direct transmit or receive functions, the encoders and
decoders can be bypassed so that the MCU can process the data in real time. The TRF7964A supports
data communication voltage levels from 1.8 V to 5.5 V for the MCU I/O interface. The transmitter has
selectable output-power levels of 100 mW (+20 dBm) or 200 mW (+23 dBm) equivalent into a 50-Ωload
when using a 5-V supply.
12 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TRF7964A

MUX
RX_IN1
RX_IN2
PHASE&
AMPLITUDE
DETECTOR
GAIN RSSI
(AUX)
LOGIC
LEVEL SHIFTER
STATE
CONTROL
LOGIC
[CONTROL
REGISTERS &
COMMAND
LOGIC]
127-BYTE
FIFO
MCU
INTERFACE
VDD_I/O
I/O_0
I/O_1
I/O_2
I/O_3
I/O_4
I/O_5
I/O_6
I/O_7
IRQ
SYS_CLK
DATA _CLK
ISO
PROTOCOL
HANDLING DECODER
RSSI
(EXTERNAL)
PHASE&
AMPLITUDE
DETECTOR
GAIN
RSSI
(MAIN)
FILTER
& AGC DIGITIZER
BIT
FRAMING
FRAMING
SERIAL
CONVERSION
CRC & PARITY
TRANSMITTER ANALOG
FRONT END
TX_OUT
VDD_PA
VSS_PA
DIGITAL CONTROL
STATE MACHINE
CRYSTAL OR OSCILLATOR
TIMING SYSTEM
EN
EN2
ASK/OOK
MOD
OSC_IN
OSC_OUT
VOLTAGE SUPPLY REGULATOR SYSTEMS
(SUPPLY REGULATORS AND REFERENCE VOLTAGES)
VSS_A
VSS_RF
VDD_RF
VDD_X
VSS_D
VSS
VIN
VDD_A
BAND_GAP
RF LEVEL
DETECTOR
TRF7964A
www.ti.com SLOS787H –MAY 2012–REVISED APRIL 2014
The transmitter supports OOK and ASK modulation with selectable modulation depth. The TRF7964A also
includes a data transmission engine that comprises low-level encoding for ISO15693, ISO14443A/B and
FeliCa. Included with the transmit data coding is the automatic generation of Start Of Frame (SOF), End
Of Frame (EOF), Cyclic Redundancy Check (CRC), or parity bits.
Several integrated voltage regulators ensure a proper power-supply noise rejection for the complete
reader system. The built-in programmable auxiliary voltage regulator VDD_X (pin 32), is able to deliver up to
20 mA to supply a microcontroller and additional external circuits within the reader system.
6.2 System Block Diagram
Figure 6-2 shows a block diagram of the TRF7964A.
Figure 6-2. System Block Diagram
6.3 Power Supplies
The TRF7964A positive supply input VIN (pin 2) sources three internal regulators with output voltages
VDD_RF, VDD_A and VDD_X. All regulators use external bypass capacitors for supply noise filtering and must
be connected as indicated in reference schematics. These regulators provide a high power supply reject
ratio (PSRR) as required for RFID reader systems. All regulators are supplied by VIN (pin 2).
The regulators are not independent and have common control bits in register 0x0B for output voltage
setting. The regulators can be configured to operate in either automatic or manual mode (register 0x0B,
bit 7). The automatic regulator setting mode ensures an optimal compromise between PSRR and the
highest possible supply voltage for RF output (to ensure maximum RF power output). The manual mode
allows the user to manually configure the regulator settings.
6.3.1 Supply Arrangements
Regulator Supply Input: VIN
Copyright © 2012–2014, Texas Instruments Incorporated Detailed Description 13
Submit Documentation Feedback
Product Folder Links: TRF7964A

TRF7964A
SLOS787H –MAY 2012–REVISED APRIL 2014 www.ti.com
The positive supply at VIN (pin 2) has an input voltage range of 2.7 V to 5.5 V. VIN provides the supply
input sources for three internal regulators with the output voltages VDD_RF, VDD_A, and VDD_X. External
bypass capacitors for supply noise filtering must be used (per reference schematics).
NOTE
VIN must be the highest voltage supplied to the TRF7964A.
RF Power Amplifier Regulator: VDD_RF
The VDD_RF (pin 3) regulator is supplying the RF power amplifier. The voltage regulator can be set for
either 5-V or 3-V operation. External bypass capacitors for supply noise filtering must be used (per
reference schematics). When configured for 5-V manual-operation, the VDD_RF output voltage can be set
from 4.3 V to 5 V in 100-mV steps. In 3-V manual-operation, the output can be programmed from 2.7 V to
3.4 V in 100-mV steps. The maximum output current capability for 5-V operation is 150 mA and for 3-V
operation is 100 mA.
Analog Supply Regulator: VDD_A
Regulator VDD_A (pin 1) supplies the analog circuits of the device. The output voltage setting depends on
the input voltage and can be set for 5-V and 3-V operation. When configured for 5-V manual-operation,
the output voltage is fixed at 3.4 V. External bypass capacitors for supply noise filtering must be used (per
reference schematics). When configured for 3-V manual-operation, the VDD_A output can be set from 2.7 V
to 3.4 V in 100-mV steps (see Table 6-2).
Note: the configuration of VDD_A and VDD_X regulators are not independent from each other. The VDD_A
output current should not exceed 20 mA.
Digital Supply Regulator: VDD_X
The digital supply regulator VDD_X (pin 32) provides the power for the internal digital building blocks and
can also be used to supply external electronics within the reader system. When configured for 3-V
operation, the output voltage can be set from 2.7 to 3.4 V in 100-mV steps. External bypass capacitors for
supply noise filtering must be used (per reference schematics).
Note: the configuration of the VDD_A and VDD_X regulators are not independent from each other. The VDD_X
output current should not exceed 20 mA.
The RF power amplifier regulator (VDD_RF), analog supply regulator (VDD_A) and digital supply regulator
(VDD_X) can be configured to operate in either automatic or manual mode described in Section 6.3.2. The
automatic regulator setting mode ensures an optimal compromise between PSRR and the highest
possible supply voltage to ensure maximum RF power output.
By default, the regulators are set in automatic regulator setting mode. In this mode, the regulators are
automatically set every time the system is activated by setting EN input High or each time the automatic
regulator setting bit, B7 in register 0x0B is set to a 1. The action is started on the 0 to 1 transition. This
means that, if the user wants to re-run the automatic setting from a state in which the automatic setting bit
is already high, the automatic setting bit (B7 in register 0x0B) should be changed: 1-0-1.
By default, the regulator setting algorithm sets the regulator outputs to a "Delta Voltage" of 250 mV below
VIN, but not higher than 5 V for VDD_RF and 3.4 V for VDD_A and VDD_A. The "Delta Voltage" in automatic
regulator mode can be increased up to 400 mV (for details, see bits B0 to B2 in register 0x0B).
14 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TRF7964A

TRF7964A
www.ti.com SLOS787H –MAY 2012–REVISED APRIL 2014
Power Amplifier Supply: VDD_PA
The power amplifier of the TRF7964A is supplied through VDD_PA(pin 4). The positive supply pin for the RF
power amplifier is externally connected to the regulator output VDD_RF (pin 3).
I/O Level Shifter Supply: VDD_I/O
The TRF7964A has a separate supply input VDD_I/O (pin 16) for the built-in I/O level shifter. The supported
input voltage ranges from 1.8 V to VIN, not exceeding 5.5 V. Pin 16 is used to supply the I/O interface pins
(I/O_0 to I/O_7), IRQ, SYS_CLK, and DATA_CLK pins of the reader. In typical applications, VDD_I/O is
directly connected to VDD_X, while VDD_X also supplies the MCU. This ensures that the I/O signal levels of
the MCU match the logic levels of the TRF7964A.
Negative Supply Connections: VSS, VSS_TX, VSS_RX, VSS_A, VSS_PA
The negative supply connections VSS_X of each functional block are all externally connected to GND.
The substrate connection is VSS (pin 10), the analog negative supply is VSS_A (pin 15), the logic negative
supply is VSS_D (pin 29), the RF output stage negative supply is VSS_PA (pin 6), and the negative supply for
the RF receiver VSS_RX (pin 7).
Copyright © 2012–2014, Texas Instruments Incorporated Detailed Description 15
Submit Documentation Feedback
Product Folder Links: TRF7964A

TRF7964A
SLOS787H –MAY 2012–REVISED APRIL 2014 www.ti.com
6.3.2 Supply Regulator Settings
The input supply voltage mode of the reader needs to be selected. This is done in the Chip Status Control
register (0x00). Bit 0 in register 0x00 selects between 5-V or 3-V input supply voltage. The default
configuration is 5 V, which reflects an operating supply voltage range of 4.3 V to 5.5 V. If the supply
voltage is below 4.3 V, the 3-V configuration should be used.
The various regulators can be configured to operate in automatic or manual mode. This is done in the
Regulator and I/O Control register (0x0B) as shown in Table 6-1 and Table 6-2.
Table 6-1. Supply Regulator Setting: 5-V System
Register Option Bits Setting in Regulator Control Register (1)
Address Comments
B7 B6 B5 B4 B3 B2 B1 B0
(hex)
Automatic Mode (default)
0B 1 x x x x x 0 0 Automatic regulator setting 400-mV difference
Manual Mode
0B 0 x x x x 1 1 1 VDD_RF = 5 V, VDD_A = 3.4 V, VDD_X = 3.4 V
0B 0 x x x x 1 1 0 VDD_RF = 4.9 V, VDD_A = 3.4 V, VDD_X = 3.4 V
0B 0 x x x x 1 0 1 VDD_RF = 4.8 V, VDD_A = 3.4 V, VDD_X = 3.4 V
0B 0 x x x x 1 0 0 VDD_RF = 4.7 V, VDD_A = 3.4 V, VDD_X = 3.4 V
0B 0 x x x x 0 1 1 VDD_RF = 4.6 V, VDD_A = 3.4 V, VDD_X = 3.4 V
0B 0 x x x x 0 1 0 VDD_RF = 4.5 V, VDD_A = 3.4 V, VDD_X = 3.4 V
0B 0 x x x x 0 0 1 VDD_RF = 4.4 V, VDD_A = 3.4 V, VDD_X = 3.4 V
0B 0 x x x x 0 0 0 VDD_RF = 4.3 V, VDD_A = 3.4 V, VDD_X = 3.4 V
(1) x = Don't care
Table 6-2. Supply Regulator Setting: 3-V System
Register Option Bits Setting in Regulator Control Register (1)
Address Comments
B7 B6 B5 B4 B3 B2 B1 B0
(hex)
Automatic Mode (default)
0B 1 x x x x x 0 0 Automatic regulator setting 400-mV difference
Manual Mode
0B 0 x x x x 1 1 1 VDD_RF = 3.4 V, VDD_A = 3.4 V, VDD_X = 3.4 V
0B 0 x x x x 1 1 0 VDD_RF = 3.3 V, VDD_A = 3.3 V, VDD_X = 3.3 V
0B 0 x x x x 1 0 1 VDD_RF = 3.2 V, VDD_A = 3.2 V, VDD_X = 3.2 V
0B 0 x x x x 1 0 0 VDD_RF = 3.1 V, VDD_A = 3.1 V, VDD_X = 3.1 V
0B 0 x x x x 0 1 1 VDD_RF = 3.0 V, VDD_A = 3.0 V, VDD_X = 3.0 V
0B 0 x x x x 0 1 0 VDD_RF = 2.9 V, VDD_A = 2.9 V, VDD_X = 2.9 V
0B 0 x x x x 0 0 1 VDD_RF = 2.8 V, VDD_A = 2.8 V, VDD_X = 2.8 V
0B 0 x x x x 0 0 0 VDD_RF = 2.7 V, VDD_A = 2.7 V, VDD_X = 2.7 V
(1) x = Don't care
The regulator configuration function adjusts the regulator outputs by default to 400 mV below VIN level, but
not higher than 5 V for VDD_RF, 3.4 V for VDD_A and VDD_X. This ensures the highest possible supply
voltage for the RF output stage while maintaining an adequate PSRR (power supply rejection ratio).
16 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TRF7964A

TRF7964A
www.ti.com SLOS787H –MAY 2012–REVISED APRIL 2014
6.3.3 Power Modes
The chip has several power states, which are controlled by two input pins (EN and EN2) and several bits
in the chip status control register (0x00) (see Table 6-3 and Table 6-4).
Table 6-3. 3.3-V Operation Power Modes(1)
Chip Regulator Typical
Status SYS_CLK Typical
Control SYS_CLK Power
Mode EN2 EN Control Transmitter Receiver (13.56 VDD_X Current
Register (60 kHz) Out
Register MHz) (mA)
(0x0B) (dBm)
(0x00)
Power Down 0 0 XX XX OFF OFF OFF OFF OFF <0.001 -
Sleep Mode 1 0 XX XX OFF OFF OFF ON ON 0.120 -
Standby Mode at X 1 80 00 OFF OFF ON X ON 2 -
+3.3 VDC
Mode 1 at +3.3 VDC X 1 00 00 OFF OFF ON X ON 3 -
Mode 2 at +3.3 VDC X 1 02 00 OFF ON ON X ON 9 -
Mode 3 (Half Power) at X 1 30 07 ON ON ON X ON 53 14.5
+3.3 VDC
Mode 4 (Full Power) at X 1 20 07 ON ON ON X ON 67 17
+3.3 VDC
(1) X = Don't care
Table 6-4. 5-V Operation Power Modes(1)
Chip Regulator Typical
Status SYS_CLK Typical
Control SYS_CLK Power
Mode EN2 EN Control Transmitter Receiver (13.56 VDD_X Current
Register (60 kHz) Out
Register MHz) (mA)
(0x0B) (dBm)
(0x00)
Power Down 0 0 XX XX OFF OFF OFF OFF OFF <0.001 -
Sleep Mode 1 0 XX XX OFF OFF OFF ON ON 0.120 -
Standby Mode at X 1 81 07 OFF OFF ON X ON 3 -
+5 VDC
Mode 1 at +5 VDC X 1 01 07 OFF OFF ON X ON 5 -
Mode 2 at +5 VDC X 1 03 07 OFF ON ON X ON 10.5 -
Mode 3 (Half Power) at X 1 31 07 ON ON ON X ON 70 20
+5 VDC
Mode 4 (Full Power) at X 1 21 07 ON ON ON X ON 130 23
+5 VDC
(1) X = Don't care
Table 6-3 and Table 6-4 show the configuration for the different power modes when using a 3.3-V or 5-V
system supply, respectively. The main reader enable signal is pin EN. When EN is set high, all of the
reader regulators are enabled, the 13.56-MHz oscillator is running and the SYS_CLK (output clock for
external micro controller) is also available.
The input pin EN2 has two functions:
• A direct connection from EN2 to VIN to ensure the availability of the regulated supply VDD_X and an
auxiliary clock signal (60 kHz, SYS_CLK) for an external MCU. This mode (EN = 0, EN2 = 1) is
intended for systems in which the MCU is also being supplied by the reader supply regulator (VDD_X)
and the MCU clock is supplied by the SYS_CLK output of the reader. This allows the MCU supply and
clock to be available during sleep mode.
• EN2 enables the start-up of the reader system from complete power down (EN = 0, EN2 = 0). In this
case the EN input is being controlled by the MCU (or other system device) that is without supply
voltage during complete power down (thus unable to control the EN input). A rising edge applied to the
EN2 input (which has an approximately 1-V threshold level) starts the reader supply system and 13.56-
MHz oscillator (identical to condition EN = 1).
Copyright © 2012–2014, Texas Instruments Incorporated Detailed Description 17
Submit Documentation Feedback
Product Folder Links: TRF7964A

VIN
EN2
EN
5 ms
6 ms
VIN
SS
EN2
EN
2 ms
5 ms
6 ms
TRF7964A
SLOS787H –MAY 2012–REVISED APRIL 2014 www.ti.com
When user MCU is controlling EN and EN2, a delay of 1 ms between EN and EN2 must be used. If the
MCU controls only EN, EN2 is recommended to be connected to either VIN or GND, depending on the
application MCU requirements for VDD_X and SYS_CLK.
Figure 6-3. Nominal Start-Up Sequence Using SPI With SS (MCU Controls EN2)
Figure 6-4. Nominal Start-Up Sequence Using Parallel (MCU Controls EN2)
This start-up mode lasts until all of the regulators have settled and the 13.56-MHz oscillator has stabilized.
If the EN input is set high (EN = 1) by the MCU (or other system device), the reader stays active. If the EN
input is not set high (EN = 0) within 100 µs after the SYS_CLK output is switched from auxiliary clock (60
kHz) to high-frequency clock (derived from the crystal oscillator), the reader system returns to complete
Power-Down Mode 1. This option can be used to wake-up the reader system from complete Power Down
(PD Mode 1) by using a pushbutton switch or by sending a single pulse.
After the reader EN line is high, the other power modes are selected by control bits within the chip status
control register (0x00). The power mode options and states are listed in Table 6-3.
When EN is set high (or on rising edge of EN2 and then confirmed by EN = 1) the supply regulators are
activated and the 13.56-MHz oscillator started. When the supplies are settled and the oscillator frequency
is stable, the SYS_CLK output is switched from the auxiliary frequency of 60 kHz to the 13.56-MHz
frequency derived from the crystal oscillator. At this point, the reader is ready to communicate and perform
the required tasks. The MCU can then program the chip status control register 0x00 and select the
operation mode by programming the additional registers.
• Stand-by Mode (bit 7 = 1 of register 0x00), the reader is capable of recovering to full operation in
100 µs.
• Mode 1 (active mode with RF output disabled, bit 5 = 0 and bit 1 = 0 of register 0x00) is a low power
mode which allows the reader to recover to full operation within 25 µs.
• Mode 2 (active mode with only the RF receiver active, bit 1 = 1 of register 0x00) can be used to
measure the external RF field (as described in RSSI measurements paragraph) if reader-to-reader
anticollision is implemented.
• Modes 3 and 4 (active modes with the entire RF section active, bit 5 = 1 of register 0x00) are the
normal modes used for normal transmit and receive operations.
18 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TRF7964A

TRF7964A
www.ti.com SLOS787H –MAY 2012–REVISED APRIL 2014
6.4 Receiver – Analog Section
6.4.1 Main and Auxiliary Receivers
The TRF7964A has two receiver inputs: RX_IN1 (pin 8) and RX_IN2 (pin 9). Each of the input is
connected to an external capacitive voltage divider to ensure that the modulated signal from the tag is
available on at least one of the two inputs. This architecture eliminates any possible communication holes
that may occur from the tag to the reader.
The two RX inputs (RX_IN1 and RX_IN2) are multiplexed into two receivers - the main receiver and the
auxiliary receiver. Only the main receiver is used for reception, the auxiliary receiver is used for signal
quality monitoring. Receiver input multiplexing is controlled by bit B3 in the Chip Status Control register
(address 0x00).
After startup, RX_IN1 is multiplexed to the main receiver which is composed of an RF envelope detection,
first gain and band-pass filtering stage, second gain and filtering stage with AGC. Only the main receiver
is connected to the digitizing stage which output is connected to the digital processing block. The main
receiver also has an RSSI measuring stage, which measures the strength of the demodulated signal
(subcarrier signal).
The primary function of the auxiliary receiver is to monitor the RX signal quality by measuring the RSSI of
the demodulated subcarrier signal (internal RSSI). After startup, RX_IN2 is multiplexed to the auxiliary
receiver. The auxiliary receiver has an RF envelope detection stage, first gain and filtering with AGC stage
and finally the auxiliary RSSI block.
The default MUX setting is RX_IN1 connected to the main receiver and RX_IN2 connected to the auxiliary
receiver. To determine the signal quality, the response from the tag is detected by the "main" (pin RX_IN1)
and "auxiliary" (pin RX_IN2) RSSI. Both values measured and stored in the RSSI level register (address
0x0F). The MCU can read the RSSI values from the TRF7964A RSSI register and make the decision if
swapping the input- signals is preferable or not. Setting B3 in Chip Status Control register (address 0x00)
to 1 connects RX_IN1 (pin 8) to the auxiliary received and RX_IN2 (pin 9) to the main receiver. This
mechanism needs to be used to avoid reading holes.
The main and auxiliary receiver input stages are RF envelope detectors. The RF amplitude at RX_IN1 and
RX_IN2 should be approximately 3 VPP for a VINsupply level greater than 3.3 V. If the VIN level is lower,
the RF input peak-to-peak voltage level should not exceed the VINlevel.
6.4.2 Receiver Gain and Filter Stages
The first gain and filtering stage has a nominal gain of 15 dB with an adjustable band-pass filter. The
band-pass filter has programmable 3d-B corner frequencies between 110 kHz to 450 kHz for the high-
pass filter and 570 kHz to 1500 kHz for the low-pass filter. After the band-pass filter, there is another gain-
and-filtering stage with a nominal gain of 8 dB and with frequency characteristics identical to the first band-
pass stage.
The internal filters are configured automatically depending on the selected ISO communication standard in
the ISO Control register (address 0x01). If required, additional fine tuning can be done by writing directly
to the RX special setting registers (address 0x0A).
The main receiver also has a second receiver gain and digitizer stage which is included in the AGC loop.
The AGC loop is activated by setting the bit B2 = 1 in the Chip Status Control register (0x00). When
activated, the AGC continuously monitors the input signal level. If the signal level is significantly higher
than an internal threshold level, gain reduction is activated.
By default, the AGC window comparator is set after the first 4 pulses of the subcarrier signal. This
prevents the AGC from interfering with the reception of the remaining data packet. In certain situations,
this AGC freeze is not optimal, so it can be removed by setting B0 = 1 in the RX special setting register
(address 0x0A).
Copyright © 2012–2014, Texas Instruments Incorporated Detailed Description 19
Submit Documentation Feedback
Product Folder Links: TRF7964A

TRF7964A
SLOS787H –MAY 2012–REVISED APRIL 2014 www.ti.com
Table 6-5. RX Special Setting Register (0x0A)
Function: Sets the gains and filters directly
Default: 0x40 at POR = H or EN = L, and at each write to the ISO Control register 0x01. When bits B7, B6, B5 and B4 are all zero, the
filters are set for ISO14443B (240 kHz to 1.4 MHz).
Bit Name Function Description
B7 C212 Bandpass 110 kHz to 570 kHz Appropriate for 212-kHz subcarrier system (FeliCa)
B6 C424 Bandpass 200 kHz to 900 kHz Appropriate for 424-kHz subcarrier used in ISO15693
Appropriate for Manchester-coded 848-kHz subcarrier used in ISO14443A
B5 M848 Bandpass 450 kHz to 1.5 MHz and B
Bandpass 100 kHz to 1.5 MHz
B4 hbt Appropriate for highest bit rate (848 kbps) used in high-bit-rate ISO14443
Gain reduced for 18 dB
B3 gd1 00 = Gain reduction 0 dB
01 = Gain reduction for 5 dB Sets the RX gain reduction, and reduces sensitivity
10 = Gain reduction for 10 dB
B2 gd2 11 = Gain reduction for 15 dB AGC activation level changed from five times the digitizing level to three
times the digitizing level.
B1 agcr AGC activation level change 1 = 3x
0 = 5x
AGC action can be done any time during receive process. It is not limited
to the start of receive ("max hold").
B0 no-lim AGC action is not limited in time 1 = continuously – no time limit
0 = 8 subcarrier pulses
Table 6-5 shows the various settings for the receiver analog section. It is important to note that setting B4,
B5, B6, and B7 to 0 results to a band-pass characteristic of 240 kHz to 1.4 MHz, which is appropriate for
ISO14443B 106 kbps, ISO14443A/B data-rates of 212 kbps and 424 kbps and FeliCa 424 kbps.
6.5 Receiver – Digital Section
The output of the TRF7964A analog receiver block is a digitized subcarrier signal and is the input to the
digital receiver block. This block includes a Protocol Bit Decoder section and the Framing Logic section.
The protocol bit decoders convert the subcarrier coded signal into a serial bit stream and a data clock.
The decoder logic is designed for maximum error tolerance. This enables the decoder section to
successfully decode even partly corrupted subcarrier signals that otherwise would be lost due to noise or
interference.
In the framing logic section, the serial bit stream data is formatted in bytes. Special signals such as the
start of frame (SOF), end of frame (EOF), start of communication, and end of communication are
automatically removed. The parity bits and CRC bytes are also checked and removed. This "clean" data is
then sent to the
127-byte FIFO register where it can be read by the external microcontroller system. Providing the data this
way, in conjunction with the timing register settings of the TRF7964A means the firmware developer has
to know about much less of the finer details of the ISO protocols to create a very robust application,
especially in low cost platforms where code space is at a premium and high performance is still required.
The start of the receive operation (successfully received SOF) sets the IRQ-flags in the IRQ and Status
register (0x0C). The end of the receive operation is signaled to the external system MCU by setting pin 13
(IRQ) to high. When data is received in the FIFO, an interrupt is sent to the MCU to signal that there is
data to be read from the FIFO. The FIFO status register (0x1C) should be used to provide the number of
bytes that should be clocked out during the actual FIFO read.
Any error in the data format, parity, or CRC is detected and notified to the external system by an interrupt-
request pulse. The source condition of the interrupt request pulse is available in the IRQ status register
(0x0C). The main register controlling the digital part of the receiver is the ISO Control register (0x01). By
writing to this register, the user selects the protocol to be used. With each new write in this register, the
default presets are reloaded in all related registers, so no further adjustments in other registers are
needed for proper operation.
20 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TRF7964A