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TRF7964A
SLOS787H –MAY 2012–REVISED APRIL 2014
TRF7964A Multiprotocol Fully Integrated 13.56-MHz RFID Reader and Writer IC
1 Device Overview
1.1 Features
1
• Completely Integrated Protocol Handling for • Integrated Voltage Regulator Output for Other
ISO15693, ISO18000-3, ISO14443A/B, and System Components (MCU, Peripherals,
FeliCa™ Indicators), 20 mA (Max)
• Integrated State Machine for ISO14443A • Programmable Modulation Depth
Anticollision (Broken Bytes) Operation • Dual Receiver Architecture With RSSI for
• Input Voltage Range: 2.7 VDC to 5.5 VDC Elimination of "Read Holes" and Adjacent Reader
System or Ambient In-Band Noise Detection
• Programmable Output Power: +20 dBm (100 mW),
+23 dBm (200 mW) • Programmable Power Modes for Ultra Low-Power
System Design (Power Down <1 µA)
• Programmable I/O Voltage Levels From 1.8 VDC
to 5.5 VDC • Parallel or SPI Interface (With 127-Byte FIFO)
• Programmable System Clock Frequency Output • Temperature Range: –40°C to 110°C
(RF, RF/2, RF/4) from 13.56-MHz or 27.12-MHz • 32-Pin QFN Package (5 mm x 5 mm)
Crystal or Oscillator
1.2 Applications
• Public Transport or Event Ticketing • Medical Equipment or Consumables
• Passport or Payment (POS) Reader Systems • Access Control, Digital Door Locks
• Product Identification or Authentication
1.3 Description
The TRF7964A device is an integrated analog front end and data-framing device for a 13.56-MHz RFID
system. Built-in programming options make the device suitable for a wide range of applications for
proximity and vicinity identification systems.
Built-in user-configurable programming options make the device suitable for a wide range of applications.
The TRF7964A device is configured by selecting the desired protocol in the control registers. Direct
access to all control registers allows fine tuning of various reader parameters as needed.
Documentation, reference designs, EVM, and source code TI MSP430™ MCUs or ARM®MCUs are
available.
Device Information
PART NUMBER PACKAGE BODY SIZE
TRF7964ARHB VQFN (32) 5 mm x 5 mm
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

MUX
RX_IN1
RX_IN2
PHASE&
AMPLITUDE
DETECTOR
GAIN RSSI
(AUX)
LOGIC
LEVEL SHIFTER
STATE
CONTROL
LOGIC
[CONTROL
REGISTERS &
COMMAND
LOGIC]
127-BYTE
FIFO
MCU
INTERFACE
VDD_I/O
I/O_0
I/O_1
I/O_2
I/O_3
I/O_4
I/O_5
I/O_6
I/O_7
IRQ
SYS_CLK
DATA _CLK
ISO
PROTOCOL
HANDLING DECODER
RSSI
(EXTERNAL)
PHASE&
AMPLITUDE
DETECTOR
GAIN
RSSI
(MAIN)
FILTER
& AGC DIGITIZER
BIT
FRAMING
FRAMING
SERIAL
CONVERSION
CRC & PARITY
TRANSMITTER ANALOG
FRONT END
TX_OUT
VDD_PA
VSS_PA
DIGITAL CONTROL
STATE MACHINE
CRYSTAL OR OSCILLATOR
TIMING SYSTEM
EN
EN2
ASK/OOK
MOD
OSC_IN
OSC_OUT
VOLTAGE SUPPLY REGULATOR SYSTEMS
(SUPPLY REGULATORS AND REFERENCE VOLTAGES)
VSS_A
VSS_RF
VDD_RF
VDD_X
VSS_D
VSS
VIN
VDD_A
BAND_GAP
RF LEVEL
DETECTOR
TRF7964A
SLOS787H –MAY 2012–REVISED APRIL 2014 www.ti.com
1.4 Functional Block Diagram
Figure 1-1 shows the block diagram.
Figure 1-1. Block Diagram
2Device Overview Copyright © 2012–2014, Texas Instruments Incorporated
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Table of Contents
1 Device Overview ......................................... 16.7 Transmitter – Analog Section ....................... 25
1.1 Features .............................................. 16.8 Transmitter – Digital Section........................ 26
6.9 Transmitter – External Power Amplifier and
1.2 Applications........................................... 1Subcarrier Detector ................................. 26
1.3 Description............................................ 16.10 TRF7964A IC Communication Interface ............ 28
1.4 Functional Block Diagram ............................ 26.11 Special Direct Mode for Improved MIFARE™
2 Revision History ......................................... 4Compatibility......................................... 46
3 Device Characteristics.................................. 56.12 Direct Commands from MCU to Reader ............ 46
4 Terminal Configuration and Functions.............. 66.13 Register Description................................. 50
4.1 Pin Assignments...................................... 67 Application Schematic and Layout
4.2 Terminal Functions ................................... 7Considerations.......................................... 68
5 Specifications ............................................ 97.1 TRF7964A Reader System Using Parallel
Microcontroller Interface............................. 68
5.1 Absolute Maximum Ratings .......................... 97.2 TRF7964A Reader System Using SPI With SS
5.2 Recommended Operating Conditions................ 9Mode ................................................ 69
5.3 Electrical Characteristics............................ 10 7.3 Layout Considerations .............................. 70
5.4 Handling Ratings.................................... 11 7.4 Impedance Matching TX_Out (Pin 5) to 50 Ω...... 70
5.5 Thermal Characteristics............................. 11 7.5 Reader Antenna Design Guidelines ................ 72
5.6 Switching Characteristics ........................... 11 8 Device and Documentation Support ............... 73
6 Detailed Description ................................... 12 8.1 Community Resources.............................. 73
6.1 Overview ............................................ 12 8.2 Trademarks.......................................... 73
6.2 System Block Diagram.............................. 13 8.3 Electrostatic Discharge Caution..................... 73
6.3 Power Supplies...................................... 13 8.4 Glossary............................................. 73
6.4 Receiver – Analog Section.......................... 19 9 Mechanical Packaging and Orderable
6.5 Receiver – Digital Section........................... 20 Information .............................................. 73
6.6 Oscillator Section ................................... 24 9.1 Packaging Information .............................. 73
Copyright © 2012–2014, Texas Instruments Incorporated Table of Contents 3
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SLOS787H –MAY 2012–REVISED APRIL 2014 www.ti.com
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (February 2014) to Revision H Page
• Changed Figure 1-1 to show 127-byte FIFO...................................................................................... 2
• Moved Section 3 ...................................................................................................................... 5
• Changed title of Section 4 .......................................................................................................... 6
• Changed title of Section 5 ........................................................................................................... 9
• Added ASK/OOK and MOD to VIL and VIH ........................................................................................ 9
• Moved Section 5.3 .................................................................................................................. 10
• Changed VDD_A TYP value from 3.5 V to 3.4 V ................................................................................. 10
• Moved Section 5.4 .................................................................................................................. 11
• Added V(ESD) MIN values, test specifications, and notes....................................................................... 11
• Changed title of Section 5.5 from Dissipation Ratings to Thermal Characteristics......................................... 11
• Moved Section 5.6 .................................................................................................................. 11
• Changed title of Section 6.......................................................................................................... 12
• Moved previous Section 3, Device Overview, to Section 6.1.................................................................. 12
• Changed from "By default, the AGC is frozen after..." to "By default, the AGC window comparator is set after..." ... 19
• Changed from "TX Pulse Length Control register (0x05)" to "TX Pulse Length Control register (0x06)" ............... 25
• Changed from "18.8 s" to "18.8 µs" in the sentence that starts with "If the register contains all zeros..."............... 25
• Changed command 0x18 to "Test internal RF" ................................................................................. 46
• Changed command 0x19 to "Test external RF" ................................................................................ 46
• Moved Section 6.13................................................................................................................. 50
• Changed the sentence that starts "The AGC action is fast..." from "finishes after four subcarrier pulses" to
"finishes within eight subcarrier pulses" ......................................................................................... 59
• Moved Section 7..................................................................................................................... 68
• Deleted previous Section 10, System Design, and moved contents to Section 7.3 through Section 7.5 ............... 70
• Removed references to figure numbers in Figure 7-3.......................................................................... 71
4Revision History Copyright © 2012–2014, Texas Instruments Incorporated
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3 Device Characteristics
Table 3-1 shows the supported modes of operation for the TRF7964A device.
Table 3-1. Supported Protocols
Supported Protocols
ISO-14443A/B FeliCa
ISO-15693,
Device ISO-18000-3 212 kbps,
106 kbps 212 kbps 424 kbps 848 kbps (Mode 1) 424 kbps
TRF7964A √√√√√√
Copyright © 2012–2014, Texas Instruments Incorporated Device Characteristics 5
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VDD_A
VIN
VDD_RF
VDD_PA
TX_OUT
VSS_PA
VSS_RX
RX_IN1
I/0_7
RX_IN2 VSS BG
ASK/OOK
IRQ MOD VSS_A VDD_I/O
Pad
VDD_X
OSC_IN
OSC_OUT
VSS_D
EN
SYS_CLK
DATA_CLK
EN2
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
I/0_6
I/0_5
I/0_4
I/0_3
I/0_2
I/0_1
I/0_0
TRF7964A
SLOS787H –MAY 2012–REVISED APRIL 2014 www.ti.com
4 Terminal Configuration and Functions
4.1 Pin Assignments
Figure 4-1 shows the pin assignments for the 32-pin RHB package.
Figure 4-1. 32-Pin RHB Package (Top View)
6Terminal Configuration and Functions Copyright © 2012–2014, Texas Instruments Incorporated
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4.2 Terminal Functions
Table 4-1 describes the signals.
Table 4-1. Terminal Functions
TERMINAL TYPE (1) DESCRIPTION
NAME NO.
VDD_A 1 OUT Internal regulated supply (2.7 V to 3.4 V) for analog circuitry
VIN 2 SUP External supply input to chip (2.7 V to 5.5 V)
VDD_RF 3 OUT Internal regulated supply (2.7 V to 5 V), normally connected to VDD_PA (pin 4)
VDD_PA 4 INP Supply for PA; normally connected externally to VDD_RF (pin 3)
TX_OUT 5 OUT RF output (selectable output power, 100 mW or 200 mW, with VDD = 5 V)
VSS_PA 6 SUP Negative supply for PA; normally connected to circuit ground
VSS_RX 7 SUP Negative supply for RX inputs; normally connected to circuit ground
RX_IN1 8 INP Main RX input
RX_IN2 9 INP Auxiliary RX input
VSS 10 SUP Chip substrate ground
BAND_GAP 11 OUT Bandgap voltage (VBG = 1.6 V); internal analog voltage reference
Selection between ASK and OOK modulation (0 = ASK, 1 = OOK) for Direct Mode 0 or 1.
ASK/OOK 12 BID Can be configured as an output to provide the received analog signal output.
IRQ 13 OUT Interrupt request
INP External data modulation input for Direct Mode 0 or 1
MOD 14 OUT Subcarrier digital data output (see registers 0x1A and 0x1B)
VSS_A 15 SUP Negative supply for internal analog circuits; connected to GND
VDD_I/O 16 INP Supply for I/O communications (1.8 V to VIN) level shifter. VIN should be never exceeded.
I/O_0 17 BID I/O pin for parallel communication
I/O_1 18 BID I/O pin for parallel communication
I/O pin for parallel communication
I/O_2 19 BID TX Enable (in Special Direct Mode)
I/O pin for parallel communication
I/O_3 20 BID TX Data (in Special Direct Mode)
I/O pin for parallel communication
I/O_4 21 BID Slave Select signal in SPI mode
I/O pin for parallel communication
I/O_5 22 BID Data clock output in Direct Mode 1 and Special Direct Mode
I/O pin for parallel communication
I/O_6 23 BID MISO for serial communication (SPI)
Serial bit data output in Direct Mode 1 or subcarrier signal in Direct Mode 0
I/O pin for parallel communication.
I/O_7 24 BID MOSI for serial communication (SPI)
Selection of power down mode. If EN2 is connected to VIN, then VDD_X is active during power
EN2 25 INP down mode 2 (for example, to supply the MCU).
DATA_CLK 26 INP Data Clock input for MCU communication (parallel and serial)
If EN = 1 (EN2 = don't care) the system clock for MCU is configured. Depending on the crystal
that is used, options are as follows (see register 0x09):
SYS_CLK 27 OUT 13.56-MHz crystal: Off, 3.39 MHz, 6.78 MHz, or 13.56 MHz
27.12-MHz crystal: Off, 6.78 MHz, 13.56 MHz, or 27.12 MHz
If EN = 0 and EN2 = 1, then system clock is set to 60 kHz
EN 28 INP Chip enable input (If EN = 0, then chip is in sleep or power-down mode).
VSS_D 29 SUP Negative supply for internal digital circuits
(1) SUP = Supply, INP = Input, BID = Bidirectional, OUT = Output
Copyright © 2012–2014, Texas Instruments Incorporated Terminal Configuration and Functions 7
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Table 4-1. Terminal Functions (continued)
TERMINAL TYPE (1) DESCRIPTION
NAME NO.
OSC_OUT 30 OUT Crystal or oscillator output
INP Crystal or oscillator input
OSC_IN 31 OUT Crystal oscillator output
Internally regulated supply (2.7 V to 3.4 V) for digital circuit and external devices (for example,
VDD_X 32 OUT MCU)
Thermal Pad PAD SUP Chip substrate ground
8Terminal Configuration and Functions Copyright © 2012–2014, Texas Instruments Incorporated
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5 Specifications
5.1 Absolute Maximum Ratings (1) (2)
over operating free-air temperature range (unless otherwise noted)
VIN Input voltage range -0.3 V to 6 V
IIN Maximum current VIN 150 mA
Any condition 140°C
TJMaximum operating virtual junction temperature Continuous operation, long-term reliability (3) 125°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Operating Conditions are not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to substrate ground terminal VSS.
(3) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability or lifetime of the device.
5.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT
VIN Operating input voltage 2.7 5 5.5 V
TAOperating ambient temperature -40 25 110 °C
TJOperating virtual junction temperature -40 25 125 °C
I/O lines, IRQ, SYS_CLK, DATA_CLK, 0.2 x
VIL Input voltage - logic low V
EN, EN2, ASK/OOK, MOD VDD_I/O
I/O lines, IRQ, SYS_CLK, DATA_CLK, 0.8 x
VIH Input voltage threshold, logic high V
EN, EN2, ASK/OOK, MOD VDD_I/O
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5.3 Electrical Characteristics
TYP operating conditions are TA= 25°C, VIN = 5 V, full-power mode (unless otherwise noted)
MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
All building blocks disabled, including supply-
IPD1 Supply current in Power Down Mode 1 voltage regulators; measured after 500-ms 0.5 5 µA
settling time (EN = 0, EN2 = 0)
The SYS_CLK generator and VDD_X remain
Supply current in Power Down Mode 2
IPD2 active to support external circuitry; measured 120 200 µA
(Sleep Mode) after 100-ms settling time (EN = 0, EN2 = 1)
Oscillator running, supply-voltage regulators in
ISTBY Supply current in stand-by mode 1.9 3.5 mA
low-consumption mode (EN = 1, EN2 = x)
Supply current without antenna driver Oscillator, regulators, RX and AGC active, TX
ION1 10.5 14 mA
current is off
Oscillator, regulators, RX and AGC and TX
ION2 Supply current – TX (half power) 70 78 mA
active, POUT = 100 mW
Oscillator, regulators, RX and AGC and TX
ION3 Supply current – TX (full power) 130 150 mA
active, POUT = 200 mW
VPOR Power-on reset voltage Input voltage at VIN 1.4 2 2.6 V
VBG Bandgap voltage (pin 11) Internal analog reference voltage 1.5 1.6 1.7 V
Regulated output voltage for analog
VDD_A VIN = 5 V 3.1 3.4 3.8 V
circuitry (pin 1)
VDD_X Regulated supply for external circuitry Output voltage pin 32, VIN = 5 V 3.1 3.4 3.8 V
IVDD_Xmax Maximum output current of VDD_X Output current pin 32, VIN = 5 V 20 mA
Half-power mode, VIN = 2.7 V to 5.5 V 8 12
RRFOUT Antenna driver output resistance (1) Ω
Full-power mode, VIN = 2.7 V to 5.5 V 4 6
RRFIN RX_IN1 and RX_IN2 input resistance 4 10 20 kΩ
Maximum RF input voltage at RX_IN1 and
VRF_INmax VRF_INmax should not exceed VIN 3.5 Vpp
RX_IN2 fSUBCARRIER= 424 kHz 1.4 2.5
Minimum RF input voltage at RX_IN1 and
VRF_INmin mVpp
RX_IN2 (input sensitivity)(2) fSUBCARRIER = 848 kHz 2.1 3
fSYS_CLK SYS_CLK frequency In power mode 2, EN = 0, EN2 = 1 25 60 120 kHz
fCCarrier frequency Defined by external crystal 13.56 MHz
Time until oscillator stable bit is set (register
tCRYSTAL Crystal run-in time 3 ms
0x0F)(3)
Depends on capacitive load on the I/O lines,
fD_CLKmax Maximum DATA_CLK frequency(4) 2 8 10 MHz
recommendation is 2 MHz(4)
ROUT Output resistance I/O_0 to I/O_7 500 800 Ω
RSYS_CLK Output resistance RSYS_CLK 200 400 Ω
(1) Antenna driver output resistance
(2) Measured with subcarrier signal at RX_IN1 or RX_IN2 and measured the digital output at MOD pin with register 0x1A bit 6 = 1.
(3) Depends on the crystal parameters and components
(4) Recommended DATA_CLK speed is 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not
exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output
resistance of 400 Ω(12-ns time constant when 30-pF load used).
10 Specifications Copyright © 2012–2014, Texas Instruments Incorporated
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