
An internal reference source provides a constant voltage of 1.7V at the VLDO output to drive the external bridge. As the
Wheatstone bridge has high source impedance and the output common-mode voltage is relative high, so the output of the
bridge is connected to an INA (first stage). The good CMRR specification of the INA will reject the common-mode DC voltage at
the bridge output and amplifying the differential signal voltage, the difference in voltage between the two lines only. The high
input impedance and low bias current of the INA will reduce the error caused by measurement circuit to minimum.
The first-stage gain (A1) is set by the external resistor (Rg) and the 100-kΩ (±15%) internal feedback resistors (RFB1):
The second-stage gain (A2) is controlled by feedback resistors RFB2, which have four possible values: 80kΩ, 160kΩ, 240kΩ, and
320kΩ. Because the gain is RF / 80kΩ, the gain setting can be 1, 2, 3, or 4.
2.2.1.2 Input Common Mode Range
The usable input common mode range of the weight-scale front-end depends on various parameters, including the maximum
differential input signal, supply voltage, and gain. The output of the first-stage amplifier must be within 250mV of the power
supply rails for linear operation. The allowed common-mode range is determined by the equation:
Where: = maximum differential input signal at the input of the first gain stage;
CM = Common-mode Range.
2.2.1.3 Input Differential Dynamic Range
The max differential (INP–INN) signal depends on the analog supply, reference used in the system. This range is shown in the
equation below:
The gain in equation above is the product of the gains of the INA and the second-stage gain. The full-scale input from the bridge
signal typically consists of a differential dc offset from the load cell plus the actual weight signal.
Having a high gain in the first stage helps minimize the effect of the noise addition from the subsequent stages. However, make
sure to choose a gain that does not saturate the first stage with the full-scale signal. Also, the common-mode of the signal must
fall within the range.
2.2.1.4 Offset Correction DAC
One way to increase the dynamic range of the signal chain is by calibrating the inherent offset of the load cell during the initial
calibration cycle. The offset correction is implemented in the second stage with a 6-bit differential DAC, where each output is a
mirror of the other and can source or sink up to 6.5µA. The effect at the output of the second stage is an addition of up to
±6.5µA×2× RFB2. This is equivalent to a voltage at the input of the second stage (A+ / A–) of up to ±6.5µA×2×80kΩ=±1V, when
RFB2 = 80kΩ. Notice that this has no effect in avoiding the first-stage saturation. Because the offset correction DAC is a 6-
bitDAC, the offset compensation step is 2V/= 31.2mV when referred to the input of the second stage.