Texas Instruments TMS320DM335 User manual

TMS320DM335
Digital Media System-on-Chip (DMSoC)ARM Subsystem
User's Guide
Literature Number: SPRUFX7
July 2008

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Contents
Preface ....................................................................................................................................... 13
1 Introduction ............................................................................................................. 161.1 Device Overview ................................................................................................................. 161.2 Block Diagram ................................................................................................................... 161.3 ARM Subsystem in DM335 ................................................................................................... 17
2 ARM Subsystem Overview ......................................................................................... 182.1 Purpose of the ARM Subsystem ........................................................................................... 182.2 Components of the ARM Subsystem .................................................................................... 182.3 References ........................................................................................................................ 19
3 ARM Core ................................................................................................................ 203.1 Introduction ....................................................................................................................... 203.2 Operating States/Modes ...................................................................................................... 213.3 Processor Status Registers ................................................................................................. 213.4 Exceptions and Exception Vectors ....................................................................................... 223.5 The 16-BIS/32-BIS Concept .................................................................................................. 223.5.1 16-BIS/32-BIS Advantages ............................................................................................. 223.6 Coprocessor 15 (CP15) ....................................................................................................... 233.6.1 Addresses in an ARM926EJ-S System ............................................................................... 233.6.2 Memory Management Unit ............................................................................................. 243.6.3 Caches and Write Buffer ............................................................................................... 243.7 Tightly Coupled Memory ..................................................................................................... 263.8 Embedded Trace Support .................................................................................................... 27
4 Memory Mapping ...................................................................................................... 294.1 Memory Map ...................................................................................................................... 294.1.1 ARM Internal Memories ................................................................................................. 304.1.2 External Memories....................................................................................................... 304.1.3 Peripherals ............................................................................................................... 304.2 Memory Interfaces Overview ................................................................................................ 334.2.1 DDR2 EMIF .............................................................................................................. 334.2.2 External Memory Interface ............................................................................................. 33
5 Device Clocking ....................................................................................................... 355.1 Overview ........................................................................................................................... 355.2 Peripheral Clocking Considerations ..................................................................................... 375.2.1 Video Processing Back End Clocking ................................................................................ 375.2.2 USB Clocking ............................................................................................................ 37
6 PLL Controllers (PLLCs) ............................................................................................ 386.1 PLL Controller Module ........................................................................................................ 386.2 PLLC1 ............................................................................................................................... 39
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6.3 PLLC2 ............................................................................................................................... 406.4 PLLC Functional Description ............................................................................................... 416.4.1 Multipliers and Dividers ................................................................................................. 416.4.2 Bypass Mode ............................................................................................................. 416.4.3 PLL Mode ................................................................................................................. 416.5 PLL Configuration .............................................................................................................. 426.5.1 PLL Mode and Bypass Mode .......................................................................................... 426.5.2 Changing Divider / Multiplier Ratios ................................................................................... 426.5.3 PLL Power Down and Wakeup ........................................................................................ 446.6 PLL Controller Register Map ................................................................................................ 446.6.1 Introduction ............................................................................................................... 446.6.2 Peripheral ID Register (PID) ........................................................................................... 466.6.3 PLL Control (PLLCTL) .................................................................................................. 476.6.4 PLL Multiplier Control Register (PLLM) ............................................................................... 486.6.5 PLL Pre-Divider Control Register (PREDIV) ......................................................................... 496.6.6 PLL Controller Divider 1 Register (PLLDIV1) ........................................................................ 506.6.7 PLL Controller Divider 2 Register (PLLDIV2) ........................................................................ 516.6.8 PLL Controller Divider 3 Register (PLLDIV3) ........................................................................ 526.6.9 PLL Post-Divider Control Register (POSTDIV) ...................................................................... 536.6.10 Bypass Divider Register (BPDIV) .................................................................................... 546.6.11 PLL Controller Command Register (PLLCMD) ..................................................................... 556.6.12 PLL Controller Status Register (PLLSTAT) ......................................................................... 566.6.13 PLL Controller Clock Align Control Register (ALNCTL) ........................................................... 576.6.14 PLLDIV Ratio Change Status Register (DCHANGE) .............................................................. 586.6.15 Clock Enable Control Register (CKEN) .............................................................................. 596.6.16 Clock Status Register (CKSTAT) ..................................................................................... 606.6.17 SYSCLK Status Register (SYSTAT) ................................................................................. 616.6.18 PLL Controller Divider 4 Register (PLLDIV4) ....................................................................... 62
7 Power and Sleep Controller ....................................................................................... 637.1 Introduction ....................................................................................................................... 637.2 Power Domain and Module Topology.................................................................................... 637.3 Power Domain and Module States Defined ............................................................................ 667.3.1 Power Domain States ................................................................................................... 667.3.2 Module States ............................................................................................................ 667.4 Executing State Transitions ................................................................................................. 677.4.1 Power Domain State Transitions ...................................................................................... 677.4.2 Module State Transitions ............................................................................................... 677.5 IcePick Emulation Support in the PSC .................................................................................. 677.6 PSC Interrupts ................................................................................................................... 687.6.1 Interrupt Events .......................................................................................................... 687.6.2 Interrupt Registers ....................................................................................................... 697.6.3 Interrupt Handling ........................................................................................................ 707.7 PSC Registers .................................................................................................................... 717.7.1 Peripheral Revision and Class Information (PID) ................................................................... 727.7.2 Interrupt Evaluation Register (INTEVAL) ............................................................................. 737.7.3 Module Error Pending Register 0 (mod 0 - 31) (MERRPR0) ...................................................... 747.7.4 Module Error Pending Register 1 (mod 32-41) (MERRPR1) ...................................................... 757.7.5 Module Error Clear Register 0 (mod 0-31) (MERRCR0) ........................................................... 76
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7.7.6 Module Error Clear Register 1 (mod 32-41) (MERRCR1) ......................................................... 777.7.7 Power Error Pending Register (PERRPR) ........................................................................... 787.7.8 Power Error Clear Register (PERRCR)............................................................................... 797.7.9 External Power Control Pending Register (EPCPR) ................................................................ 807.7.10 External Power Control Clear Register (EPCCR) .................................................................. 817.7.11 Power Domain Transition Command Register (PTCMD) ......................................................... 827.7.12 Power Domain Transition Status Register (PTSTAT) ............................................................. 837.7.13 Power Domain Status Register 0 (PDSTATn) ...................................................................... 847.7.14 Power Domain Control n Register 0 (PDCTLn) .................................................................... 857.7.15 Module Status n Register 0-32 (MDSTATn) ........................................................................ 867.7.16 Module Control n Register 0-51 (MDCTLn) ......................................................................... 87
8 Interrupt Controller ................................................................................................... 888.1 Introduction ....................................................................................................................... 888.2 Interrupt Mapping ............................................................................................................... 888.3 INTC Methodology .............................................................................................................. 898.3.1 Interrupt Mapping ........................................................................................................ 908.3.2 Interrupt Prioritization ................................................................................................... 908.3.3 Vector Table Entry Address Generation .............................................................................. 918.3.4 Clearing Interrupts ....................................................................................................... 918.3.5 Enabling and Disabling Interrupts ..................................................................................... 928.4 INTC Registers ................................................................................................................... 938.4.1 Fast Interrupt Request Status Register 0 (FIQ0) .................................................................... 948.4.2 Fast Interrupt Request Status Register 1 (FIQ1) .................................................................... 958.4.3 Interrupt Request Status Register 0 (IRQ0) .......................................................................... 968.4.4 Interrupt Request Status Register 1 (IRQ1) .......................................................................... 978.4.5 Fast Interrupt Request Entry Address Register (FIQENTRY) ..................................................... 988.4.6 Interrupt Request Entry Address Register (IRQENTRY) ........................................................... 998.4.7 Interrupt Enable Register 0 (EINT0) ................................................................................. 1008.4.8 Interrupt Enable Register 1 (EINT1) ................................................................................. 1018.4.9 Interrupt Operation Control Register (INTCTL) .................................................................... 1028.4.10 EABASE ................................................................................................................ 1038.4.11 Interrupt Priority Register 0 (INTPRI0) ............................................................................ 1048.4.12 Interrupt Priority Register 1 (INTPRI1) ............................................................................. 1058.4.13 Interrupt Priority Register 2 (INTPRI2) ............................................................................. 1068.4.14 Interrupt Priority Register 3 (INTPRI3) ............................................................................. 1078.4.15 Interrupt Priority Register 4 (INTPRI4) ............................................................................. 1088.4.16 Interrupt Priority Register 5 (INTPRI5) ............................................................................. 1098.4.17 Interrupt Priority Register 6 (INTPRI6) ............................................................................. 1108.4.18 Interrupt Priority Register 7 (INTPRI7) ............................................................................. 111
9 System Control Module ........................................................................................... 1129.1 Overview of the System Control Module .............................................................................. 1129.2 Device Identification .......................................................................................................... 1129.3 Device Configuration ......................................................................................................... 1129.3.1 Pin Multiplexing Control .............................................................................................. 1129.3.2 Device Boot Configuration Status .................................................................................... 1139.4 ARM Interrupt and EDMA Event Multiplexing Control ............................................................ 1139.5 Special Peripheral Status and Control ................................................................................. 113
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9.5.1 Timer64+ Control ....................................................................................................... 1139.5.2 USB PHY Control ...................................................................................................... 1149.5.3 VPSS Clock and DAC Control and Status .......................................................................... 1149.5.4 DDR I/O Timing Control and Status ................................................................................. 1149.6 Clock Out Configuration Status .......................................................................................... 1149.7 GIO De-Bounce Control ..................................................................................................... 1149.8 Power Management ........................................................................................................... 1149.8.1 Deep Sleep Control .................................................................................................... 1149.9 Bandwidth Management .................................................................................................... 1159.9.1 Bus Master DMA Priority Control .................................................................................... 1159.10 System Control Register Descriptions ................................................................................. 1179.10.1 Introduction ............................................................................................................ 1179.10.2 PINMUX0 - Pin Mux 0 (Video In) Pin Mux Register ............................................................. 1189.10.3 PINMUX1 - Pin Mux 1 (Video Out) Pin Mux Register ............................................................ 1209.10.4 PINMUX2 - Pin Mux 2 (AEMIF) Pin Mux Register ............................................................... 1229.10.5 PINMUX3 - Pin Mux 3 (GIO/Misc) Pin Mux Register ............................................................. 1249.10.6 PINMUX4 - Pin Mux 4 (Misc) Pin Mux Register .................................................................. 1279.10.7 BOOTCFG - Boot Configuration .................................................................................... 1289.10.8 ARM_INTMUX - ARM Interrupt Mux Control Register ........................................................... 1299.10.9 EDMA_EVTMUX - EDMA Event Mux Control Register ......................................................... 1309.10.10 DDR_SLEW - DDR Slew ........................................................................................... 1319.10.11 CLKOUT - CLKOUT Divisor / Output Control ................................................................... 1329.10.12 DEVICE_ID - Device ID ............................................................................................ 1339.10.13 VDAC_CONFIG - Video Dac Configuration ...................................................................... 1349.10.14 TIMER64_CTL - Timer64+ Input Control ........................................................................ 1359.10.15 USB_PHY_CTRL - USB PHY Control ........................................................................... 1369.10.16 MISC - Miscellaneous Control ..................................................................................... 1389.10.17 MSTPRI0 - Master Priorities 0 ..................................................................................... 1389.10.18 Master Priorities 1 (MSTPRI1) Register .......................................................................... 1399.10.19 VPSS_CLK_CTRL - VPSS Clock Mux Control ................................................................. 1409.10.20 Deep Sleep Mode Configuration (DEEPSLEEP) Register .................................................... 1419.10.21 DEBOUNCE[8] - De-bounce for GIO[n] Input ................................................................... 1429.10.22 VTPIOCR - VTP IO Control Register ............................................................................. 143
10 Reset ..................................................................................................................... 14410.1 Reset Overview ................................................................................................................ 14410.2 Reset Pins ....................................................................................................................... 14410.3 Types of Reset ................................................................................................................. 14510.3.1 Power-On Reset (POR) .............................................................................................. 14510.3.2 Warm Reset ........................................................................................................... 14510.3.3 Max Reset .............................................................................................................. 14610.3.4 System Reset .......................................................................................................... 14610.3.5 Module Reset .......................................................................................................... 14610.4 Default Device Configurations ............................................................................................ 14610.4.1 Device Configuration Pins ........................................................................................... 14610.4.2 PLL Configuration ..................................................................................................... 14710.4.3 Module Configuration ................................................................................................. 14710.4.4 ARM Boot Mode Configuration ...................................................................................... 14710.4.5 AEMIF Configuration ................................................................................................. 148
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11 Boot Modes ............................................................................................................ 14911.1 Boot Modes Overview ....................................................................................................... 14911.1.1 Features ................................................................................................................ 14911.1.2 Functional Block Diagram ............................................................................................ 15111.2 ARM ROM Boot Modes ...................................................................................................... 15111.2.1 NAND Boot Mode ..................................................................................................... 15111.2.2 MMC/SD Boot Mode .................................................................................................. 15911.2.3 UART Boot Mode ..................................................................................................... 164
12 Power Management ................................................................................................. 16812.1 Overview ......................................................................................................................... 16812.2 PSC and PLLC Overview ................................................................................................... 16812.3 Clock Management ........................................................................................................... 16912.3.1 Module Clock Disable ................................................................................................ 16912.3.2 Module Clock Frequency Scaling ................................................................................... 16912.3.3 PLL Bypass and Power Down ....................................................................................... 16912.4 ARM Sleep Mode Management ........................................................................................... 16912.4.1 ARM Wait-For-Interrupt Sleep Mode ............................................................................... 16912.5 System Sleep Modes ......................................................................................................... 17012.5.1 Deep Sleep Mode ..................................................................................................... 17012.6 I/O Management ................................................................................................................ 17012.6.1 USB Phy Power Down ............................................................................................... 17012.6.2 Video DAC Power Down ............................................................................................. 17112.6.3 DDR Self-Refresh and Power Down ............................................................................... 171
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List of Figures
1-1 Functional Block Diagram ................................................................................................. 172-1 ARM Subsystem Block Diagram ......................................................................................... 195-1 Clocking Architecture ...................................................................................................... 366-1 PLLC1 Configuration ....................................................................................................... 406-2 PLLC2 Configuration ....................................................................................................... 416-3 Clock Ratio Change and Alignment with Go Operation ............................................................... 436-4 Peripheral ID Register (PID) .............................................................................................. 466-5 PLL Control Register (PLLCTL) .......................................................................................... 476-6 PLL Multiplier Control Register (PLLM) ................................................................................. 486-7 PLL Pre-Divider Control Register (PREDIV) ............................................................................ 496-8 PLL Controller Divider 1 Register (PLLDIV1) ........................................................................... 506-9 PLL Controller Divider 2 Register (PLLDIV2) ........................................................................... 516-10 PLL Controller Divider 3 Register (PLLDIV3) ........................................................................... 526-11 PLL Post-Divider Control Register (POSTDIV) ......................................................................... 536-12 Bypass Divider Register (BPDIV) ........................................................................................ 546-13 PLL Controller Command Register (PLLCMD) ......................................................................... 556-14 PLL Controller Status Register (PLLSTAT) ............................................................................. 566-15 PLL Controller Clock Align Control Register (ALNCTL) ............................................................... 576-16 PLLDIV Ratio Change Status (DCHANGE) ............................................................................. 586-17 Clock Enable Control Register (CKEN) ................................................................................. 596-18 Clock Status Register (CKSTAT) ........................................................................................ 606-19 SYSCLK Status Register (SYSTAT) ..................................................................................... 616-20 PLL Controller Divider 4 Register (PLLDIV4) ........................................................................... 627-1 Power and Sleep Controller (PSC) ...................................................................................... 637-2 Power Domain and Module Topology ................................................................................... 647-3 Peripheral Revision and Class Information Register (PID) ........................................................... 727-4 Interrupt Evaluation Register (INTEVAL) ................................................................................ 737-5 Module Error Pending Register 0 (mod 0 - 31) (MERRPR0) ......................................................... 747-6 Module Error Pending Register 1 (mod 32-41) (MERRPR1) ......................................................... 757-7 Module Error Clear Register 0 (mod 0-31) (MERRCR0) .............................................................. 767-8 Module Error Clear Register 1 (mod 32-41) (MERRCR1) ............................................................ 777-9 Power Error Pending Register (PERRPR) .............................................................................. 787-10 Power Error Clear Register (PERRCR) ................................................................................. 797-11 External Power Control Pending Register (EPCPR) .................................................................. 807-12 External Power Control Clear Register (EPCCR) ...................................................................... 817-13 Power Domain Transition Command Register (PTCMD) ............................................................. 827-14 Power Domain Transition Status Register (PTSTAT) ................................................................. 837-15 Power Domain Status n Register (PDSTATn) .......................................................................... 847-16 Power Domain Control n Register (PDCTLn) .......................................................................... 857-17 Module Status n Register (MDSTATn) .................................................................................. 867-18 Module Control n Register 0-41 (MDCTLn) ............................................................................. 878-1 AINTC Functional Diagram ............................................................................................... 908-2 Interrupt Entry Table ...................................................................................................... 918-3 Immediate Interrupt Disable / Enable .................................................................................... 928-4 Delayed Interrupt Disable ................................................................................................. 928-5 Interrupt Status of INT[31:0] (if mapped to FIQ) ....................................................................... 948-6 Interrupt Status of INT[63:32] (if mapped to FIQ) ...................................................................... 958-7 Interrupt Status of INT[31:0] (if mapped to IRQ) ....................................................................... 968-8 Interrupt Status of INT[31:0] (if mapped to IRQ) ....................................................................... 978-9 Fast Interrupt Request Entry Address Register (FIQENTRY) ........................................................ 988-10 Interrupt Request Entry Address Register (IRQENTRY) .............................................................. 998-11 Interrupt Enable Register 0 (EINT0) .................................................................................... 100
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8-12 Interrupt Enable Register 1 (EINT1) .................................................................................... 1018-13 Interrupt Operation Control Register (INTCTL) ....................................................................... 1028-14 EABASE ................................................................................................................... 1038-15 Interrupt Priority Register 0 (INTPRI0) ................................................................................. 1048-16 Interrupt Priority Register 1 (INTPRI1) ................................................................................. 1058-17 Interrupt Priority Register 2 (INTPRI2) ................................................................................. 1068-18 Interrupt Priority Register 3 (INTPRI3) ................................................................................. 1078-19 Interrupt Priority Register 4 (INTPRI4) ................................................................................. 1088-20 Interrupt Priority Register 5 (INTPRI5) ................................................................................. 1098-21 Interrupt Priority Register 6 (INTPRI6) ................................................................................. 1108-22 Interrupt Priority Register 7 (INTPRI7) ................................................................................. 1119-1 PINMUX0 - Pin Mux 0 (Video In) Pin Mux Register .................................................................. 1189-2 PINMUX1 - Pin Mux 1 (Video Out) Pin Mux Register................................................................ 1209-3 PINMUX2 - Pin Mux 2 (AEMIF) Pin Mux Register ................................................................... 1229-4 PINMUX3 - Pin Mux 3 (GIO/Misc) Pin Mux Register ................................................................ 1249-5 PINMUX4 - Pin Mux 4 (Misc) Pin Mux Register ...................................................................... 1279-6 BOOTCFG - Boot Configuration ........................................................................................ 1289-7 ARM_INTMUX - ARM Interrupt Mux Control Register ............................................................... 1299-8 EDMA_EVTMUX - EDMA Event Mux Control Register ............................................................. 1309-9 DDR_SLEW - DDR Slew ................................................................................................ 1319-10 CLKOUT - CLKOUT div/out Control .................................................................................... 1329-11 DEVICE_ID - Device ID .................................................................................................. 1339-12 VDAC_CONFIG - Video Dac Configuration ........................................................................... 1349-13 TIMER64_CTL - Timer64+ Input Control ............................................................................. 1359-14 USB_PHY_CTRL - USB PHY Control ................................................................................ 1369-15 MISC - Miscellaneous Control .......................................................................................... 1389-16 MSTPRI0 - Master Priorities 0 .......................................................................................... 1389-17 Master Priorities 1(MSTPRI1) Register ................................................................................ 1399-18 VPSS_CLK_CTRL - VPSS Clock Mux Control ...................................................................... 1409-19 Deep Sleep Mode Configuration (DEEPSLEEP) Register .......................................................... 1419-20 DEBOUNCE[8] - De-bounce for GIO[n] Input ......................................................................... 1429-21 VTP IO Control Register (VTPIOCR) .................................................................................. 14311-1 Boot Modes Overview .................................................................................................... 15011-2 Boot Mode Functional Block Diagram ................................................................................. 15111-3 NAND Boot Flow .......................................................................................................... 15211-4 4-Bit ECC Format and Bit 10 to 8-Bit Compression Algorithm ..................................................... 15411-5 4-Bit ECC Format for 2048+64 Byte Page Size ...................................................................... 15511-6 NAND Boot Mode Flow Chart ........................................................................................... 15611-7 ARM NAND ROM Boot Loader Example .............................................................................. 15711-8 Descriptor Search for ARM NAND Boot Mode ....................................................................... 15811-9 MMC/SD Boot Mode Overview ......................................................................................... 16011-10 MMC/SD Boot Mode Flow Chart ....................................................................................... 16211-11 ARM MMC/SD ROM Boot Loader Example ........................................................................... 16311-12 Descriptor Search for ARM MMC/SD Boot Mode .................................................................... 16411-13 UART Boot Mode Handshake ........................................................................................... 16511-14 Host Utility Timing ........................................................................................................ 167
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List of Tables
3-1 Exception Vector Table for ARM ......................................................................................... 223-2 Different Address Types in ARM System ............................................................................... 233-3 ITCM/DTCM Memory Map ................................................................................................ 263-4 ITCM/DTCM Size Encoding............................................................................................... 273-5 ETM Part Descriptions ..................................................................................................... 274-1 Memory Map ................................................................................................................ 294-2 ARM Configuration Bus Access to Peripherals ........................................................................ 316-1 PLLC1 Output Clocks ...................................................................................................... 396-2 PLLC2 Output Clocks ...................................................................................................... 406-3 PLL and Reset Controller Module Instance Table ..................................................................... 446-4 PLLC Registers ............................................................................................................. 446-5 Peripheral ID Register (PID) Field Descriptions ........................................................................ 466-6 PLL Control Register (PLLCTL) Field Descriptions .................................................................... 476-7 PLL Multiplier Control Register (PLLM) Field Descriptions ........................................................... 486-8 PLL Pre-Divider Control (PREDIV) Field Descriptions ................................................................ 496-9 PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions .................................................... 506-10 PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions .................................................... 516-11 PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions .................................................... 526-12 PLL Post-Divider Control (POSTDIV) Field Descriptions ............................................................. 536-13 Bypass Divider Register (BPDIV) Field Descriptions .................................................................. 546-14 PLL Controller Command Register (PLLCMD) Field Descriptions................................................... 556-15 PLL Controller Status (PLLSTAT) Field Descriptions ................................................................. 566-16 PLL Controller Clock Align Control (ALNCTL) Field Descriptions ................................................... 576-17 PLLDIV Ratio Change Status (DCHANGE) Field Descriptions ...................................................... 586-18 Clock Enable Control Register (CKEN) Field Descriptions ........................................................... 596-19 Clock Status Register (CKSTAT) Field Descriptions .................................................................. 606-20 SYSCLK Status Register (SYSTAT) Field Descriptions .............................................................. 616-21 PLL Controller Divider 4 Register (PLLDIV4) Field Descriptions .................................................... 627-1 Module Configuration ...................................................................................................... 657-2 Module States .............................................................................................................. 667-3 IcePick Emulation Commands ............................................................................................ 677-4 PSC Interrupt Events ...................................................................................................... 687-5 PSC Registers .............................................................................................................. 717-6 Peripheral Revision and Class Information Register (PID) Field Descriptions ..................................... 727-7 Interrupt Evaluation Register (INTEVAL) Field Descriptions ......................................................... 737-8 Module Error Pending Register 0 (mod 0 - 31) (MERRPR0) Field Descriptions .................................. 747-9 Module Error Pending Register 1 (mod 32-41) (MERRPR1) Field Descriptions ................................... 757-10 Module Error Clear Register 0 (mod 0-31) (MERRCR0) Field Descriptions ....................................... 767-11 Module Error Clear Register 1 (mod 32-41) (MERRCR1) Field Descriptions ...................................... 777-12 Power Error Pending Register (PERRPR) Field Descriptions ........................................................ 787-13 Power Error Clear Register (PERRCR) Field Descriptions ........................................................... 797-14 External Power Control Pending Register (EPCPR) Field Descriptions ............................................ 807-15 External Power Control Clear Register (EPCCR) Field Descriptions ............................................... 817-16 Power Domain Transition Command Register (PTCMD) Field Descriptions ....................................... 827-17 Power Domain Transition Status Register (PTSTAT) Field Descriptions ........................................... 837-18 Power Domain Status n Register (PDSTATn) Field Descriptions ................................................... 847-19 Power Domain Control n Register (PDCTLn) Field Descriptions .................................................... 857-20 Module Status n Register 0-32 (MDSTATn) Field Descriptions ...................................................... 867-21 Module Control n Register 0-51 (MDCTLn) Field Descriptions ...................................................... 87
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