Texas Instruments TMS320DM36 Series User manual

TMS320DM36x Digital Media System-on-Chip
(DMSoC) Power Management and Real-Time
Clock Subsystem (PRTCSS)
User's Guide
Literature Number: SPRUFJ0A
May 2009–Revised March 2010

2SPRUFJ0A–May 2009–Revised March 2010
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Preface ....................................................................................................................................... 7
1 Purpose of the PRTC Subsystem ........................................................................................ 10
1.1 Features of the PRTCSS ............................................................................................. 10
1.2 Signal Descriptions .................................................................................................... 10
1.3 Configuration of PRTCSS and PRTCIF ............................................................................. 11
1.4 PRTCSS Reset and Configuration .................................................................................. 11
1.4.1 Normal Mode ............................................................................................... 11
1.4.1.1 PRTCSS Initialization Sequence in Normal Mode ................................................ 12
1.4.2 External Reset Mode ...................................................................................... 13
1.5 Industry Standards Compliance Statement ........................................................................ 13
1.6 Interrupt Support ....................................................................................................... 13
1.7 Clock Controller ........................................................................................................ 13
1.7.1 Clock Source Selection .................................................................................... 13
1.7.2 Clock Controller ............................................................................................ 14
1.8 EDMA Event Support .................................................................................................. 14
1.9 Emulation Considerations ............................................................................................. 14
2 PRTC Interface (PRTCIF) .................................................................................................... 14
2.1 Features of the PRTC Interface ...................................................................................... 14
2.2 PRTC Interface Functional Operation ............................................................................... 14
2.2.1 Flow of the PRTCIF Function ............................................................................. 15
2.3 Interrupt Status of PRTCSS Events ................................................................................. 16
2.4 Power Management ................................................................................................... 17
3 PRTCSS Modules .............................................................................................................. 17
3.1 General Purpose I/O (GIO) ........................................................................................... 17
3.1.1 Using the GIO Signal as an Output or Input ............................................................ 17
3.1.1.1 Configuring a GIO Output Signal .................................................................... 17
3.1.1.2 Configuring a GIO Input Signal ...................................................................... 17
3.1.2 Configuring GIO Interrupt Edge Triggering ............................................................. 18
3.1.2.1 GIO Interrupt Status ................................................................................... 18
3.1.3 Using the PWCTRO2 Signal as a Clock or PWM Output Function ................................. 18
3.1.3.1 Configuring PWCTRO2 Signal as Clock Output ................................................... 18
3.1.3.2 Configuring PWCTRO2 Signal as PWM Output Function ........................................ 18
3.2 PRTCSS INTC ......................................................................................................... 19
3.2.1 Configuring the INTC Interrupt ........................................................................... 20
3.2.2 INTC Interrupt Status ...................................................................................... 20
3.3 Real Time Clock (RTC) ............................................................................................... 20
3.3.1 RTC Functional Block Diagram .......................................................................... 20
3.3.2 RTC Initialization ........................................................................................... 21
3.3.2.1 Initializing the Timer ................................................................................... 21
3.3.2.2 Initializing the Watchdog Timer ...................................................................... 22
3.3.2.3 Initializing the Calendar with Alarm .................................................................. 22
3.4 Sequencer .............................................................................................................. 23
3.4.1 Sequencer Features ....................................................................................... 23
3.4.2 Initial Sequencer Flow in Normal Mode ................................................................. 24
3
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4 Registers .......................................................................................................................... 25
4.1 PRTC Interface (PRTCIF) Registers ................................................................................ 25
4.1.1 PRTCIF Peripheral ID (PID) Register ................................................................... 26
4.1.2 PRTCIF Control (PRTCIF_CTRL) Register ............................................................. 27
4.1.3 PRTCIF Access Lower Data (PRTCIF_LDATA) Register ............................................ 28
4.1.4 PRTCIF Access Upper Data (PRTCIF_UDATA) Register ............................................ 29
4.1.5 PRTCIF Interrupt Enable (PRTCIF_INTEN) Register ................................................. 30
4.1.6 PRTCIF Interrupt Flag (PRTCIF_INTFLG) Register ................................................... 31
4.2 Power Management and Real Time Clock Subsystem (PRTCSS) Registers ................................. 32
4.2.1 Global Output Pin Output Data (GO_OUT) Register .................................................. 33
4.2.2 Global Input/Output Pin Output Data (GIO_OUT) Register .......................................... 34
4.2.3 Global Input/Output Pin Direction (GIO_DIR) Register ............................................... 35
4.2.4 Global Input/Output Pin Input Data (GIO_IN) Register ................................................ 36
4.2.5 Global Input/Output Pin Function (GIO_FUNC) Register ............................................. 37
4.2.6 GIO Rise Interrupt Enable (GIO_RISE_INT_EN) Register ........................................... 38
4.2.7 GIO Fall Interrupt Enable (GIO_FALL_INT_EN) Register ............................................ 39
4.2.8 GIO Rise Interrupt Flag (GIO_RISE_INT_FLG) Register ............................................. 40
4.2.9 GIO Fall Interrupt Flag (GIO_FALL_INT_FLG) Register .............................................. 41
4.2.10 EXT Interrupt Enable 0 (INTC_EXTENA0) Register .................................................. 42
4.2.11 EXT Interrupt Enable 1 (INTC_EXTENA1) Register .................................................. 43
4.2.12 Event Interrupt Flag 0 (INTC_FLG0) Register .......................................................... 44
4.2.13 Event Interrupt Flag 1 (INTC_FLG1) Register .......................................................... 45
4.2.14 RTC Control (RTC_CTRL) Register ..................................................................... 46
4.2.15 Watchdog Timer Counter (RTC_WDT) Register ....................................................... 47
4.2.16 Timer Counter 0 (RTC_TMR0) Register ................................................................ 48
4.2.17 Timer Counter 1 (RTC_TMR1) Register ................................................................ 49
4.2.18 RTC Calendar Control (RTC_CCTRL) Register ....................................................... 50
4.2.19 RTC Seconds (RTC_SEC) Register ..................................................................... 51
4.2.20 RTC Minutes (RTC_MIN) Register ...................................................................... 52
4.2.21 RTC Hours (RTC_HOUR) Register ...................................................................... 53
4.2.22 RTC Days[7:0] (RTC_DAY0) Register .................................................................. 54
4.2.23 RTC Days[14:8] (RTC_DAY1) Register ................................................................. 55
4.2.24 RTC Minutes Alarm (RTC_AMIN) Register ............................................................. 56
4.2.25 RTC Hours Alarm (RTC_AHOUR) Register ............................................................ 57
4.2.26 RTC Days[7:0] Alarm (RTC_ADAY0) Register ......................................................... 58
4.2.27 RTC Days[14:8] Alarm (RTC_ADAY1) Register ....................................................... 59
4.2.28 Clock Control (CLKC_CNT) Register .................................................................... 60
4.2.29 Sequencer Loop Counter Value (SEQ_LOOP) Register .............................................. 61
Appendix A Revision History ...................................................................................................... 62
4Contents SPRUFJ0A–May 2009–Revised March 2010
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List of Figures
1 PRTC Subsystem Block Diagram....................................................................................... 11
2 PRTCSS Initialization Sequence - Normal Mode ..................................................................... 12
3 PRTCSS External Circuit Example for Normal Mode................................................................. 13
4 PRTCIF Functional Diagram............................................................................................. 14
5 PRTCIF Function Flow.................................................................................................... 16
6 GO2 PWM Output Period ................................................................................................ 19
7 RTC Functional Block Diagram.......................................................................................... 21
8 Alarm Interrupt Diagram.................................................................................................. 23
9 Sequencer Initial Program Flow in Normal mode ..................................................................... 24
10 PRTCIF Peripheral ID Register (PID)................................................................................... 26
11 PRTCIF Control (PRTCIF_CTRL) Register............................................................................ 27
12 PRTCIF Access Lower Data (PRTCIF_LDATA) Register ........................................................... 28
13 PRTCIF Access Upper Data (PRTCIF_UDATA) Register .......................................................... 29
14 PRTCIF Interrupt Enable (PRTCIF_INTEN) Register ................................................................ 30
15 PRTCIF Interrupt Enable (PRTCIF_INTFLG) Register............................................................... 31
16 Global Output Pin Output Data (GO_OUT) Register ................................................................ 33
17 Global Input/Output Pin Output Data (GIO_OUT) Register.......................................................... 34
18 Global Input/Output Pin Direction (GIO_DIR) Register .............................................................. 35
19 Global Input/Output Pin Input Data (GIO_IN) Register .............................................................. 36
20 Global Input/Output Pin Function (GIO_FUNC) Register ........................................................... 37
21 GIO Rise Interrupt Enable (GIO_RISE_INT_EN) Register .......................................................... 38
22 GIO Fall Interrupt Enable Register (GIO_FALL_INT_EN) ........................................................... 39
23 GIO Rise Interrupt Flag (GIO_RISE_INT_FLG) Register............................................................ 40
24 GIO Fall Interrupt Flag (GIO_FALL_INT_FLG) Register ............................................................ 41
25 EXT Interrupt Enable 0 (INTC_EXTENA0) Register.................................................................. 42
26 EXT Interrupt Enable 1 (INTC_EXTENA1) Register.................................................................. 43
27 Event Interrupt Flag 0 (INTC_FLG0) Register ........................................................................ 44
28 Event Interrupt Flag 1 (INTC_FLG1) Register ........................................................................ 45
29 RTC Control (RTC_CTRL) Register .................................................................................... 46
30 RTC Watchdog Timer Counter (RTC_WDT) Register................................................................ 47
31 Timer Counter 0 (RTC_TMR0) Register................................................................................ 48
32 Timer Counter 1 (RTC_TMR1) Register................................................................................ 49
33 RTC Calendar Control (RTC_CCTRL) Register....................................................................... 50
34 RTC Seconds (RTC_SEC) Register.................................................................................... 51
35 RTC Minutes (RTC_MIN) Register...................................................................................... 52
36 RTC Hours Register (RTC_HOUR)..................................................................................... 53
37 RTC Days[7:0] (RTC_DAY0) Register.................................................................................. 54
38 RTC Days[14:8] (RTC_DAY1) Register ............................................................................... 55
39 RTC Minutes Alarm (RTC_AMIN) Register............................................................................ 56
40 RTC Hours Alarm (RTC_AHOUR) Register .......................................................................... 57
41 RTC Days[7:0] Alarm (RTC_ADAY0) Register........................................................................ 58
42 RTC Days[14:8] Alarm (RTC_ADAY1) Register....................................................................... 59
43 Clock Control (CLKC_CNT) Register .................................................................................. 60
44 Sequencer Loop Counter Value (SEQ_LOOP) Register............................................................. 61
5
SPRUFJ0A–May 2009–Revised March 2010 List of Figures
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List of Tables
1 PRTCSS Signals .......................................................................................................... 10
2 PRTCSS Configuration Bus Masters and Slaves ..................................................................... 11
3 PWM Output Width........................................................................................................ 18
4 RTC Alarm Enable Bits................................................................................................... 23
5 PRTC Interface (PRTCIF) Registers.................................................................................... 25
6 PRTCIF Peripheral ID Register (PID) Field Descriptions ............................................................ 26
7 PRTCIF Control (PRTCIF_CTRL) Field Descriptions................................................................. 27
8 PRTCIF Access Lower Data (PRTCIF_LDATA) Field Descriptions ................................................ 28
9 PRTCIF Access Upper Data (PRTCIF_UDATA) Field Descriptions................................................ 29
10 PRTCIF Interrupt Enable (PRTCIF_INTEN) Field Descriptions..................................................... 30
11 PRTCIF Interrupt Flag (PRTCIF_INTFLG) Field Descriptions....................................................... 31
12 Power Management and Real Time Clock Subsystem (PRTCSS) Registers..................................... 32
13 Global Output Pin Output Data (GO_OUT) Field Descriptions...................................................... 33
14 Global Input/Output Pin Output Data (GIO_OUT) Field Descriptions .............................................. 34
15 Global Input/Output Pin Direction (GIO_DIR) Field Descriptions ................................................... 35
16 Global Input/Output Pin Input Data (GIO_IN) Field Descriptions ................................................... 36
17 Global Input/Output Pin Function (GIO_FUNC) Field Descriptions................................................. 37
18 GIO Rise Interrupt Enable (GIO_RISE_INT_EN) Field Descriptions............................................... 38
19 GIO Fall Interrupt Enable Register (GIO_FALL_INT_EN) Field Descriptions..................................... 39
20 GIO Rise Interrupt Flag (GIO_RISE_INT_FLG) Field Descriptions................................................. 40
21 GIO Fall Interrupt Flag (GIO_FALL_INT_FLG) Field Descriptions.................................................. 41
22 EXT Interrupt Enable 0 (INTC_EXTENA0) Field Descriptions ...................................................... 42
23 EXT Interrupt Enable 1 (INTC_EXTENA1) Field Descriptions ...................................................... 43
24 Event Interrupt Flag 0 (INTC_FLG0) Field Descriptions ............................................................. 44
25 Event Interrupt Flag 1 (INTC_FLG1) Field Descriptions ............................................................. 45
26 RTC Control (RTC_CTRL) Field Descriptions......................................................................... 46
27 RTC Watchdog Timer Counter (RTC_WDT) Field Descriptions .................................................... 47
28 Timer Counter 0 (RTC_TMR0) Field Descriptions.................................................................... 48
29 Timer Counter 1 (RTC_TMR1) Field Descriptions.................................................................... 49
30 RTC Calendar Control (RTC_CCTRL) Field Descriptions ........................................................... 50
31 RTC Seconds (RTC_SEC) Field Descriptions......................................................................... 51
32 RTC Minutes (RTC_MIN) Field Descriptions .......................................................................... 52
33 RTC Hours (RTC_HOUR) Field Descriptions.......................................................................... 53
34 RTC Days[7:0] (RTC_DAY0) Field Descriptions ...................................................................... 54
35 RTC Days[14:8] (RTC_DAY1) Field Descriptions..................................................................... 55
36 RTC Minutes Alarm (RTC_AMIN) Field Descriptions................................................................. 56
37 RTC Hours Alarm (RTC_AHOUR) Field Descriptions................................................................ 57
38 RTC Days[7:0] Alarm (RTC_ADAY0) Field Descriptions............................................................. 58
39 RTC Days[14:8] Alarm (RTC_ADAY1) Field Descriptions........................................................... 59
40 Clock Control (CLKC_CNT) Field Descriptions........................................................................ 60
41 Sequencer Loop Counter Value (SEQ_LOOP) Field Descriptions ................................................. 61
42 Changes Made in This Revision......................................................................................... 62
6List of Tables SPRUFJ0A–May 2009–Revised March 2010
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Preface
SPRUFJ0A–May 2009–Revised March 2010
Read This First
About this Manual
This document provides a functional description of the Power Management and Real-Time Clock
Subsystem (PRTCSS) in the TMS320DM36x Digital Media System-on-Chip (DMSoC) and PRTC interface
(PRTCIF).
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the TMS320DM36x Digital Media System-on-Chip (DMSoC). Copies of
these documents are available on the internet.
SPRUFG5 —TMS320DM365 Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference
Guide This document describes the ARM Subsystem in the TMS320DM36x Digital Media
System-on-Chip (DMSoC). The ARM subsystem is designed to give the ARM926EJ-S (ARM9)
master control of the device. In general, the ARM is responsible for configuration and control of the
device; including the components of the ARM Subsystem, the peripherals, and the external
memories.
SPRUFG8 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Video Processing Front End
(VPFE) Users Guide This document describes the Video Processing Front End (VPFE) in the
TMS320DM36x Digital Media System-on-Chip (DMSoC).
SPRUFG9 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Video Processing Back End
(VPBE) Users Guide This document describes the Video Processing Back End (VPBE) in the
TMS320DM36x Digital Media System-on-Chip (DMSoC).
SPRUFH0 —TMS320DM36x Digital Media System-on-Chip (DMSoC) 64-bit Timer Users Guide This
document describes the operation of the software-programmable 64-bit timers in the
TMS320DM36x Digital Media System-on-Chip (DMSoC).
SPRUFH1 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Serial Peripheral Interface
(SPI) Users Guide This document describes the serial peripheral interface (SPI) in the
TMS320DM36x Digital Media System-on-Chip (DMSoC). The SPI is a high-speed synchronous
serial input/output port that allows a serial bit stream of programmed length (1 to 16 bits) to be
shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used for
communication between the DMSoC and external peripherals. Typical applications include an
interface to external I/O or peripheral expansion via devices such as shift registers, display drivers,
SPI EPROMs and analog-to-digital converters.
7
SPRUFJ0A–May 2009–Revised March 2010 Preface
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Related Documentation From Texas Instruments www.ti.com
SPRUFH2 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Asynchronous
Receiver/Transmitter (UART) Users Guide This document describes the universal asynchronous
receiver/transmitter (UART) peripheral in the TMS320DM36x Digital Media System-on-Chip
(DMSoC). The UART peripheral performs serial-to-parallel conversion on data received from a
peripheral device, and parallel-to-serial conversion on data received from the CPU.
SPRUFH3 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Inter-Integrated Circuit (I2C)
Peripheral Users Guide This document describes the inter-integrated circuit (I2C) peripheral in the
TMS320DM36x Digital Media System-on-Chip (DMSoC). The I2C peripheral provides an interface
between the DMSoC and other devices compliant with the I2C-bus specification and connected by
way of an I2C-bus.
SPRUFH5 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Multimedia Card
(MMC)/Secure Digital (SD) Card Controller Users Guide This document describes the
multimedia card (MMC)/secure digital (SD) card controller in the TMS320DM36x Digital Media
System-on-Chip (DMSoC).
SPRUFH6 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Pulse-Width Modulator (PWM)
Users Guide This document describes the pulse-width modulator (PWM) peripheral in the
TMS320DM36x Digital Media System-on-Chip (DMSoC).
SPRUFH7 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Real-Time Out (RTO)
Controller Users Guide This document describes the Real Time Out (RTO) controller in the
TMS320DM36x Digital Media System-on-Chip (DMSoC).
SPRUFH8 —TMS320DM36x Digital Media System-on-Chip (DMSoC) General-Purpose Input/Output
(GPIO) Users Guide This document describes the general-purpose input/output (GPIO) peripheral
in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The GPIO peripheral provides
dedicated general-purpose pins that can be configured as either inputs or outputs.
SPRUFH9 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Serial Bus (USB)
Controller Users Guide This document describes the universal serial bus (USB) controller in the
TMS320DM36x Digital Media System-on-Chip (DMSoC). The USB controller supports data
throughput rates up to 480 Mbps. It provides a mechanism for data transfer between USB devices
and also supports host negotiation.
SPRUFI0 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Enhanced Direct Memory
Access (EDMA) Controller Users Guide This document describes the operation of the enhanced
direct memory access (EDMA3) controller in the TMS320DM36x Digital Media System-on-Chip
(DMSoC). The EDMA controller's primary purpose is to service user-programmed data transfers
between two memory-mapped slave endpoints on the DMSoC.
SPRUFI1 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Asynchronous External
Memory Interface (EMIF) Users Guide This document describes the asynchronous external
memory interface (EMIF) in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The EMIF
supports a glueless interface to a variety of external devices.
SPRUFI2 —TMS320DM36x Digital Media System-on-Chip (DMSoC) DDR2/Mobile DDR
(DDR2/mDDR) Memory Controller Users Guide This document describes the DDR2/mDDR
memory controller in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The
DDR2/mDDR memory controller is used to interface with JESD79D-2A standard compliant DDR2
SDRAM and mobile DDR devices.
SPRUFI3 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Multibuffered Serial Port
Interface (McBSP) User's Guide This document describes the operation of the multibuffered serial
host port interface in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The primary
audio modes that are supported by the McBSP are the AC97 and IIS modes. In addition to the
primary audio modes, the McBSP supports general serial port receive and transmit operation.
SPRUFI4 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Host Port Interface
(UHPI) User's Guide This document describes the operation of the universal host port interface in
the TMS320DM36x Digital Media System-on-Chip (DMSoC).
8Read This First SPRUFJ0A–May 2009–Revised March 2010
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www.ti.com Related Documentation From Texas Instruments
SPRUFI5 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Ethernet Media Access
Controller (EMAC) User's Guide This document describes the operation of the ethernet media
access controller interface in the TMS320DM36x Digital Media System-on-Chip (DMSoC).
SPRUFI7 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Analog to Digital Converter
(ADC) User's Guide This document describes the operation of the analog to digital conversion in
the TMS320DM36x Digital Media System-on-Chip (DMSoC).
SPRUFI8 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Key Scan User's Guide This
document describes the key scan peripheral in the TMS320DM36x Digital Media System-on-Chip
(DMSoC).
SPRUFI9 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Voice Codec User's Guide This
document describes the voice codec peripheral in the TMS320DM36x Digital Media
System-on-Chip (DMSoC). This module can access ADC/DAC data with internal FIFO (Read
FIFO/Write FIFO). The CPU communicates to the voice codec module using 32-bit-wide control
registers accessible via the internal peripheral bus.
SPRUFJ0 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Power Management and
Real-Time Clock Subsystem (PRTCSS) User's Guide This document provides a functional
description of the Power Management and Real-Time Clock Subsystem (PRTCSS) in the
TMS320DM36x Digital Media System-on-Chip (DMSoC) and PRTC interface (PRTCIF).
SPRUGG8 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Face Detection User's GuideThis
document describes the face detection capabilities for the TMS320DM36x Digital Media
System-on-Chip (DMSoC).
9
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User's Guide
SPRUFJ0A–May 2009–Revised March 2010
TMS320DM36x DMSoC Power Management and Real-Time
Clock Subsystem (PRTCSS)
1 Purpose of the PRTC Subsystem
The Power Management and Real Time Clock Subsystem (PRTCSS) is used for calendar applications
and to manage the DM36x power supply. The PRTCSS has an independent power supply, and hence can
remain ON even while the rest of the DM36x power supply is turned OFF. Therefore, the PRTCSS can be
operated without supplying the power supply of the entire device. The PRTCSS has a real-time clock,
timers, general-purpose I/Os, and a simple sequencer.
1.1 Features of the PRTCSS
The PRTCSS has the following features:
• General purpose I/O (GPIO) with anti-chattering 4-output pins (PWRCTRO[3:0]), and 7-Input/Output
pins (PWRCTRIO[6:0])
• Simple real-time clock (RTC) count, up to 89 years
• Alarm event generated to check the RTC count
• Watch-dog timer
• 16-bit simple timer
1.2 Signal Descriptions
The PRTCSS signal descriptions are shown in Table 1. Refer to the TMS320DM365 DMSoC Data Manual
(SPRS457) for more information on these pins.
Table 1. PRTCSS Signals
Signal name Signal Type Function
PWCTRIO0 Input/Output General Input / Output Signal 0
PWCTRIO1 Input/Output General Input / Output Signal 1
PWCTRIO2 Input/Output General Input / Output Signal 2
PWCTRIO3 Input/Output General Input / Output Signal 3
PWCTRIO4 Input/Output General Input / Output Signal 4
PWCTRIO5 Input/Output General Input / Output Signal 5
PWCTRIO6 Input/Output General Input / Output Signal 6
PWCTRO0 Output General Output Signal 0
PWCTRO1 Output General Output Signal 1
PWCTRO2 Output General Output Signal 2
PWCTRO3 Output General Output Signal 3
RTCXI Input Crystal Input for PRTCSS oscillator
RTCXO Output Crystal Output for PRTCSS oscillator
PWRST Input Reset signal for PRTCSS
PWRCNTON Input Reset pin for system power sequencing
10 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A–May 2009–Revised March 2010
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Sequencer
INTC
Bus
Interface
Clock
Controller
RTC With
Timer
GIO
PRTC
Interface
RTC XI RTC XO
PWRST PWRCNTON
PRTC Subsystem
32-bit
Peripheral
Bus
INT to CPU
PWCTRIO0
PWCTRIO1
PWCTRIO2
PWCTRIO3
PWCTRIO4
PWCTRIO5
PWCTRIO6
PWCTRO0
PWCTRO1
PWCTRO2
PWCTRO3
www.ti.com Purpose of the PRTC Subsystem
1.3 Configuration of PRTCSS and PRTCIF
A block diagram of the PRTC subsystem module is shown in Figure 1 .
Figure 1. PRTC Subsystem Block Diagram
The DM36x device can access the PRTCIF registers; however, it cannot directly access the PRTCSS
registers.
Table 2 shows the various PRTCSS configuration bus masters and slaves.
Table 2. PRTCSS Configuration Bus Masters and Slaves
PRTCSS Masters PRTCSS Slaves
PRTCIF CLKC, INTC, GIO, RTC with Timer
1.4 PRTCSS Reset and Configuration
The PWRST and PWRCNTON input pins control the reset of the module. PRTCSS can operate in either
normal mode or external reset mode.
For normal mode operation, see Section 1.4.1; for external reset mode operation, see Section 1.4.2.
1.4.1 Normal Mode
In the normal mode of operation, the PRTCSS submodules' reset is controlled by the state of PWCTRO0
pin. When the PWCTRO0 pin is in logic level 0, then the PRTCSS submodules will be in reset and the
DM36x device will not be able to access the PRTCSS registers.
When the PRTCSS module operates in normal mode, irrespective of the whether the PWCTRO0 is
connected to the RESET of the device or not, the DM36x device must reset the WDT of PRTCSS so that
the PWCTRO0 pin state will be retained at logic 1.
This normal mode of operation of PRTCSS will be the preferred mode of operation, where the PRTCSS is
powered with backup power and where the PRTCSS calendar/RTC contents will be retained even when
the DM36x is reset. In this case, the PRTCSS submodule must be battery-powered.
11
SPRUFJ0A–May 2009–Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem
(PRTCSS)
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PRTCSS Power
Under Sequencer Control
External control
PRTCSS
32.768 kHz
PWRST
PWRCNTON
PWCTRO1
PWCTRO0
SEQ Out
SEQ Start
D 36x Power on
by SEQ
MD 36x Power Off
by SEQ with WDT
M
Wait the stable time
for the D 36x OSCM
Wait the WDT event
D 36x has to Stop WDT.M
D 36x PowerM
D 36x ClockM
D 36x RESETzM
D 36x Reset Off
by SEQ
M
Purpose of the PRTC Subsystem www.ti.com
Figure 2 explains the recommended reset sequencing of PRTCSS using the PWRST and PWRCNTON
input pins. In this mode the sequencer and the PRTCSS block are powered ON. The sequencer executes
the initialization sequence as discussed in Section 3.4.2. In normal mode, the DM36x reset is controlled by
the PRTCSS (through PWCTRO0). The main device must reset the PRTCSS WDT using the PRTCIF to
complete the initialization sequence. Failure to reset the PRTCSS WDT will result in a RESET of the
DM36x device when the PRTCSS WDT expires. Figure 3 shows an example of the PRTCSS external
connections for the DM36x power lines and control signals in the normal mode. See Section 3 for an
overview of each major block of the PRTCSS.
1.4.1.1 PRTCSS Initialization Sequence in Normal Mode
The following section provides the procedure for initializing the PRTCSS in normal mode:
1. Ensure the PRTCSS module is in reset by clearing the PWRST and PWRCNTON signals to 0.
2. Provide the power for the PRTCSS block.
3. Set PWCTRIO0 pin to ‘0’.
4. Input ‘1’ to the reset signal for PRTCSS (PWRST) after the 32.768 kHz oscillator is stable.
5. Input ‘1’ to the reset pin for system power sequencing (PWRCNTON) to start the sequencer of the
power control block.
The Sequencer performs the following steps:
6. Outputs ‘1’ on the PWCTRO1 pin. This signal must be used to control the power IC that supplies
power to the DM36x device.
7. Outputs ‘1’ on the PWCTRO0 pin. This signal connects to the DM36x RESETz pin after the stable time
of the main clock oscillator.
8. Enables the PRTCSS WDT.
9. Outputs ‘0’s (after expiration of WDT (16 sec)) on the PWCTRO0/1 to control power off.
The DM36x device must stop the PRTCSS WDT by clearing the WEN bit in the RTC control register
(RTC_CTRL) within 16 sec after DM36x comes out of reset. Otherwise, the sequencer will execute the
power-off sequence for the device.
Figure 2. PRTCSS Initialization Sequence - Normal Mode
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PWCTRO0
PWCTRO1
PWCTRO2
PWCTRO3
PWCTRIO0
PRTC Subsystem
TPS65530
SW1
XSLEEP
SW3
ENAFE
VOUT2
1.2 V Main Power
1.8 V Main Power
3.3V Main Power
DM365
Level
RESET
GIOx
Shifter
PWR
CVDD
VDDS33
VDDS18x
SW
PWRCNTON
PWRST
TPS65510
VO1R8
VO1R2
XRESET
CS
1.2 V PRTCSS Power
1.8 V PRTCSS Power
VDD12_PRTCSS
VDD18_PRTCSS
Back-Up
Battery
Main
Power
Battery
PWCTRIO1
PWCTRIO2
PWCTRIO3
PWCTRIO4
PWCTRIO6
Main
Power
Battery
www.ti.com Purpose of the PRTC Subsystem
Figure 3. PRTCSS External Circuit Example for Normal Mode
1.4.2 External Reset Mode
The PRTCSS will work in this mode if the PWRCNTON input pin is held at 1 and the PWRST pin is held
at 0. Power on/off and reset for the DM36x device should be done externally, as the PRTCSS has no
control over them. The device reset signal (RESETz) will reset the PRTCSS. The SEQ cannot be used in
this mode.
1.5 Industry Standards Compliance Statement
The PRTCSS module does not conform to any recognized industry standards.
1.6 Interrupt Support
The PRTCIF combines an interrupt from the PRTCSS INTC and the PRTCIF and generates a single
interrupt to the DM36x. For further details on the PRTCSS INTC refer to Section 3.2, and for information
on the PRTCIF DMA completion interrupt, refer to Section 2.3.
Multiple interrupt sources can be assigned to the same CPU interrupt. To identify the interrupt source, the
CPU reads the PRTCIF interrupt flag register (PRTCIF_INTFLG). For more information on the System
Control Module and ARM Interrupt Controller, refer to theTMS320DM365 Digital Media System-on-Chip
(DMSoC) ARM Subsystem User's Guide (SPRUFG5).
1.7 Clock Controller
1.7.1 Clock Source Selection
The PRTCSS module can operate from two clock sources. Clock source selection for the PRTCSS
module is based on the configuration of the PRTCCLKS field of the PERI_CLKCTL register. For more
information on device clocking, refer to the TMS320DM365 Digital Media System-on-Chip (DMSoC) ARM
Subsystem User's Guide (SPRUFG5).
The CLKC_CNT register is used to set WDT and Peripheral Clocks divider values.
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PRTCIF Control Reg
Upper Data (4 Bytes)
Lower Data (4 Bytes)
INT Control Reg
Access MMR
Access
Control
32-bit Peripheral
bus
RTCINT
RTCSS_INT
RTC Bus
PRTCIF
PRTC Interface (PRTCIF) www.ti.com
1.7.2 Clock Controller
CLKC_CNT register is used to control the clock divider values for PERI_CLK and WDT clock. Divide
values range from 1 to 4096.
1.8 EDMA Event Support
The PRTCSS module does not generate an EDMA event.
1.9 Emulation Considerations
The PRTCSS module controller is not affected by emulation halt events, such as breakpoints.
2 PRTC Interface (PRTCIF)
The PRTC interface (PRTCIF) is the bridge to connect the 32-bit DM36x bus to the 8-bit PRTCSS bus.
The device can access the PRTCSS module through the PRTCIF.
2.1 Features of the PRTC Interface
The PRTCIF interface has the following features:
• PRTCSS memory map space is accessed through PRTCIF registers
• Busy bit that indicates the data access status
• Interrupt generated on the read/write complete
• Synchronizers for PRTCSS interrupt with the DM36x interrupt
Figure 4 shows the functional diagram for the PRTCIF interface.
Figure 4. PRTCIF Functional Diagram
2.2 PRTC Interface Functional Operation
The following steps provides the functional operation of the PRTC Interface:
• Wait until the BUSY bit in the PRTCIF control register (PRTCIF_CTRL) is "0"
• Configure the desired data format in the PRTCIF control register (PRTCIF_CTRL)
– Program the data access direction in the DIR bit
– Program the data access size in the SIZE bit
– Program the access byte enable for PRTCIF_UDATA in the BENU bits
– Program the access byte enable for PRTCIF_LDATA in the BENL bits
• Set the PRTCSS target memory address that the PRTCIF needs to access read/write by configuring
the ADRS bits in the PRTCIF control register (PRTCIF_CTRL)
• Enable the desired interrupts, if any, in the PRTCIF interrupt enable register (PRTCIF_INTEN)
• If DIR is 1, then:
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– Write the first 4 bytes of PRTCSS data through the PRTCIF access lower data (PRTCIF_LDATA)
register
– If SIZE is 1, then write the second 4 bytes of PRTCSS data through the PRTCIF access upper data
(PRTCIF_UDATA) register
• If DIR is 0, then
– Read the first 4 bytes of PRTCSS data through the PRTCIF access lower data (PRTCIF_LDATA)
register
– If SIZE is 1, then read the second 4 bytes of PRTCSS data through the PRTCIF access upper data
(PRTCIF_UDATA) register
• Wait until the BUSY bit in the PRTCIF control register (PRTCIF_CTRL) is "0" before updating the
PRTCIF_UDATA/PRTCIF_LDATA
• PRTCIF generates an interrupt once the DMA access to PRTCSS from PRTCIF is completed
2.2.1 Flow of the PRTCIF Function
Figure 5 shows the flow of the PRTCIF function.
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Idle
Write
Event to
PRTCIF_CTRL
No
Yes
PRTCIF_
CTRL[23:16] = 0
0
Not 0
PRTCIF_CTRL[23:20] Byte Enable for Upper 4 Bytes
PRTCIF_CTRL[19:16] Byte Enable for Lower 4 Bytes
PRTCIF_CTRL[31] = 1 PRTCIF_CTRL[31]: Status, 1:Busy
Yes
PRTCIF_
CTRL[24] = 0
Write Data to PRTCSS Read Data to PRTCSS
1
PRTCIF_CTRL[24] : DMA Direction, 0:Write 1:Read
Wait
Response from
PRTCSS
PRTCIF_CTRL[31] = 0
Generate Interrupt if
Enabled
PRTC Interface (PRTCIF) www.ti.com
Figure 5. PRTCIF Function Flow
A Must not update the PRTCIF_UDATA/PRTCIF_LDATA registers during PRTCIF_CTRL[31] == '1'(PRTCIF is Busy)
B There will be no response from the PRTCSS module if clocks are not supplied to PRTCSS
2.3 Interrupt Status of PRTCSS Events
The PRTCSS_INT_FLAG and PRTCIF_INT_FLAG bits in the PRTCIF interrupt flag register
(PRTCIF_INTFLG) indicate the interrupt for PRTCSS events and the access state of the PRTCIF
interface, respectively.
The PRTCIF interface generates the following interrupt events:
• PRTCSS_INT_FLAG: PRTCSS interrupt flag
PRTCSS_INT_FLAG = 1 in the PRTCIF interrupt flag register (PRTCIF_INTFLG) indicates there is a
PRTCSS interrupt to PRTCIF.
• PRTCIF_INT_FLAG: PRTCIF interrupt flag
PRTCIF_INT_FLAG = 1 in the PRTCIF Interrupt Flag Register (PRTCIF_INTFLG) indicates the end of
DMA access to PRTCSS from PRTCIF
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2.4 Power Management
The PRTCIF interface can be placed in reduced-power modes to conserve power during periods of low
activity. For detailed information on power management procedures using the PSC, see the
TMS320DM365 Digital Media System-on-Chip (DMSoC) ARM Subsystem Users Guide (SPRUFG5).
3 PRTCSS Modules
3.1 General Purpose I/O (GIO)
The GIO module provides dedicated pins that can be configured as either inputs or outputs. When
configured as an output, you can write to an internal register to control the state of the output pin. When
configured as an input, you can detect the state of the input by reading the state of an internal register.
NOTE: For detailed information on the GIO module and registers, see Section 4.2.
The GIO module supports the following features:
• Basic GIO function for each of the 11 pins
– PWCTRO[3:0] pins are used as output only
– PWCTRIO[6:0] pins are used as either input or output
• Anti-chattering for input pins
• PWCTRO2 can be configured to output 32.768 KHz Clock or PWM
• Two interrupt enable bits control the GIO functions
3.1.1 Using the GIO Signal as an Output or Input
GIO signals are configured to operate as input or output pins by clearing the value to the GO2_FUNC bit
of the general purpose in/out function register (GIO_FUNC).
3.1.1.1 Configuring a GIO Output Signal
To configure a given GIO signal as an output, clear the bit in GIO_DIR register that is associated with the
desired GIO signal.
The GIO output data register (GIO_OUT) contains the current state of the output signals. Reading
GIO_OUT returns the output state (not necessarily the actual signal state) since some signals may be
configured as inputs. The actual signal state is read using the GIO input data register (GIO_IN) associated
with the desired GIO signal. GIO_IN contains the actual logic state on the external signal.
To modify the bit in the GIO_OUT register associated with the desired GIO signal, use the
read-modify-write operation. The logic states driven on the GIO output signals match the logic values
written to all bits in the GIO_OUT register. For GIO signals configured as inputs, the values written to the
GIO_OUT bits have no effect.
3.1.1.2 Configuring a GIO Input Signal
To configure a given GIO signal as an input, set the bit in GIO_DIR that is associated with the desired
GIO signal.
The current state of the GIO signals is read using the GIO input data register (GIO_IN). For GIO signals
configured as inputs, reading GIO_IN returns the state of the input signal synchronized to the GIO
peripheral clock.
For GIO signals configured as outputs, reading GIO_IN returns the output value being driven by the
device.
Some signals may utilize open-drain output buffers for wired-logic operations. For open-drain GIO signals,
reading GIO_IN returns the wired-logic value on the signal (which will not be driven by the device alone).
Information on any signals using open-drain outputs is available in the device data manual.
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3.1.2 Configuring GIO Interrupt Edge Triggering
Each GIO interrupt source can be configured to generate an interrupt on the GIO signal rising edge, falling
edge, both edges, or neither edge (no event). The edge detection is synchronized to the GIO peripheral
module clock.
The following registers control the configuration of the GIO interrupt edge detection:
• The GIO rise interrupt enable register (GIO_RISE_INT_ENA) enables GIO interrupts on the occurrence
of a rising edge on the GIO signal.
• The GIO fall interrupt enable register (GIO_FALL_INT_ENA) enables GIO interrupts on the occurrence
of a falling edge on the GIO signal.
To configure a GIO interrupt to occur only on rising edges of the GIO signal:
• Write a logic 1 to the associated bit in GIO_RISE_INT_ENA
To configure a GIO interrupt to occur only on falling edges of the GIO signal:
• Write a logic 1 to the associated bit in GIO_FALL_INT_ENA
To configure a GIO interrupt to occur on both the rising and falling edges of the GIO signal:
• Write a logic 1 to the associated bit in GIO_RISE_INT_ENA
• Write a logic 1 to the associated bit in GIO_FALL_INT_ENA
To disable a specific GIO interrupt:
• Write a logic 0 to the associated bit in GIO_RISE_INT_ENA
• Write a logic 0 to the associated bit in GIO_FALL_INT_ENA
You must clear the GIO_RISE_INT_FLG and GIO_FALL_INT_FLG registers before configuring the
GIO_RISE_INT_ENA or GIO_FALL_INT_ENA register. These detectors for the GIO rise/fall edge are
active at the input direction. So, GIO_RISE_INT_FLG and GIO_FALL_INT_FLG registers keep the change
conditions of input pins. When the flag is '1' and the interrupt enable is set, the interrupt is generated.
3.1.2.1 GIO Interrupt Status
The status of GIO interrupt events can be monitored by reading the GIO interrupt flag register for the rise
edge (GIO_RISE_INT_FLG) and GIO interrupt flag register for fall edge (GIO_FALL_INT_FLG). Pending
GIO interrupts are indicated with a logic 1 in the associated bit position; interrupts that are not pending are
indicated with a logic 0. For individual GIO interrupts that are directly routed to the INTC. Pending GIO
interrupt flags can be cleared by writing a logic 1 to the associated bit position in GIO_RISE_INT_FLG and
GIO_FALL_INT_FLG.
3.1.3 Using the PWCTRO2 Signal as a Clock or PWM Output Function
3.1.3.1 Configuring PWCTRO2 Signal as Clock Output
To configure the PWCTRO2 signal as a clock output, write the appropriate value to the GO2_FUNC bit of
the general purpose in/out function register (GIO_FUNC). In this configuration, GIO will drive the
PWCTRO2 pin as a 32.768 KHz clock out function.
3.1.3.2 Configuring PWCTRO2 Signal as PWM Output Function
To configure the PWCTRO2 signal as PWM output, write the appropriate value to the GO2_FUNC bit of
general purpose in/out function register (GIO_FUNC). In this configuration, GIO will drive the PWCTRO2
pin as a PWM out function. The PWM width can be configured, as shown in Table 3, by writing to the
PWM_WIDTH bits of the general purpose in/out function register (GIO_FUNC).
Table 3. PWM Output Width
Clk_Peri = Frequency/CLKC_PERI PWM Width (mSec) = (2(PWM_WIDTH + 4) )/ Clk_Peri
Freqency CLKC_PERI Clk_Peri PWM_WI PWM_WI PWM_WI PWM_WI PWM_WI PWM_WI PWM_WI PWM_WI
(Hz) DTH = 00 DTH = 01 DTH = 02 DTH = 03 DTH = 04 DTH = 05 DTH = 06 DTH = 07
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G02 PWM Function 1:1
1:2
1:3
1:4
1:5
1:6
1:7
1:8
Polarity = 0
PWM_PERIOD = 0
Polarity = 0
PWM_PERIOD = 1
Polarity = 0
PWM_PERIOD = 2
Polarity = 0
PWM_PERIOD = 3
Polarity = 0
PWM_PERIOD = 4
Polarity = 0
PWM_PERIOD = 5
Polarity = 0
PWM_PERIOD = 6
Polarity = 0
PWM_PERIOD = 7
PWM Width
www.ti.com PRTCSS Modules
Table 3. PWM Output Width (continued)
Clk_Peri = Frequency/CLKC_PERI PWM Width (mSec) = (2(PWM_WIDTH + 4) )/ Clk_Peri
32,768 1 32,768 0.49 0.98 1.95 3.91 7.81 15.63 31.25 62.50
Hz 2 16,384 0.98 1.95 3.91 7.81 15.63 31.25 62.50 125
4 8,192 1.95 3.91 7.81 15.63 31.25 62.50 125 250
8 4,096 3.91 7.81 15.63 31.25 62.50 125 250 500
16 2,048 7.81 15.63 31.25 62.50 125 250 500 1,000
32 1,024 15.63 31.25 62.50 125 250 500 1,000 2,000
64 512 31.25 62.50 125 250 500 1,000 2,000 4,000
128 256 62.50 125 250 500 1,000 2,000 4,000 8,000
256 128 125 250 500 1,000 2,000 4,000 8,000 16,000
512 64 250 500 1,000 2,000 4,000 8,000 16,000 32,000
1024 32 500 1,000 2,000 4,000 8,000 16,000 32,000 64,000
2048 16 1,000 2,000 4,000 8,000 16,000 32,000 64,000 128,000
4096 8 2,000 4,000 8,000 16,000 32,000 64,000 128,000 256,000
You can configure the PWM period by writing PWM_PERIOD bits of the general purpose in/out function
register (GIO_FUNC) and the same has been shown in Figure 6 for a given PWM width.
Figure 6. GO2 PWM Output Period
3.2 PRTCSS INTC
The PRTCSS module outputs a single interrupt RTCINT that is routed to the DM36x interrupt controller.
The INTC supports interrupts from GIO signals and interrupts from RTC signals.
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The INTC module generates an interrupt to DM36x for GIO and RTC if enabled. Interrupt mapping from
the GIO and RTC to the DM36x is shown in Section 4.
3.2.1 Configuring the INTC Interrupt
The following registers control the configuration of the INTC interrupt to DM36x:
• The EXT Event Enable 0 register (INTC_EXTENA0) enables INTC interrupts to DM36x on the
occurrence of interrupts from the GIO signals and DM36x.
• The EXT Event Enable 1 register (INTC_EXTENA1) enables INTC interrupts to DM36x on the
occurrence of interrupts from the RTC signals.
3.2.2 INTC Interrupt Status
The status of INTC interrupt events can be monitored by reading the Interrupt flag 0 register (INTC_FLG0)
and Interrupt flag 1 register (INTC_FLG1). Pending INTC interrupts are indicated with a logic 1 in the
associated bit position; interrupts that are not pending are indicated with a logic 0.
PRTCSS individual INTC interrupts are not directly routed to the ARM device. ARM has to check the
individual interrupt status by reading the INTC_FLG0 and INTC_FLG1 registers using the PRTCIF.
Pending INTC interrupt flags can be cleared by writing a logic 1 to the associated module Flag bit.
For detailed information on INTC_FLG0 and INTC_FLG1, see Section 4.
3.3 Real Time Clock (RTC)
The RTC module supports the following features:
• Simple RTC is configured to count the following
– Sec : 0 - 59 : BCD count
– Min : 0 - 59 : BCD count
– Hour : 0 - 23 : BCD count
– Day : 0 - 0x7FFF(32767) : binary count (over 89 years)
• Alarm
– Generate event signal with RTC count value
• Free running watchdog timer
– 8-bit decrement counter with re-load control bit
– Initial load value is "FF." Initial period is 256 x 16Hz : 16sec
– When count value reaches 0, generate the event and reload a specified period value
• 16-bit decrement timer
– One-shot, free-run mode
– Generate event signal to INTC
3.3.1 RTC Functional Block Diagram
The RTC module functional block diagram is shown in Figure 7.
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