Titan ATOP3.5G Installation manual

ATOP3.5G Hardware User Guide
(OM12030)
80447ST10636A rev.15 - 2019-11-21

ATOP3.5G Hardware User Guide
80447ST10636A rev.15 – 2019-11-21
Reproduction forbidden without written authorization from Titan Automotive Solutions NV - All Rights
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APPLICABILITY TABLE
PRODUCT
REGIONS
W
(orld)
U
(SA)
A
(PAC)
ATOP 3.5G
√
√
√
+ SMX
√
√
√
+ SMX + NFC
√
√
√

ATOP3.5G Hardware User Guide
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SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE
Notice
While reasonable efforts have been made to assure the accuracy of this document, Titan assumes
no liability resulting from any inaccuracies or omissions in this document, or from use of the
information obtained herein. The information in this document has been carefully checked and is
believed to be entirely reliable. However, no responsibility is assumed for inaccuracies or omissions.
Titan reserves the right to make changes to any products described herein and reserves the right
to revise this document and to make changes from time to time in content hereof with no obligation
to notify any person of revisions or changes. Titan does not assume any liability arising out of the
application or use of any product, software, or circuit described herein; neither does it convey
license under its patent rights or the rights of others.
It is possible that this publication may contain references to, or information about Titan products
(machines and programs), programming, or services that are not announced in your country. Such
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rd
Party supplied Software (SW) products described in this instruction manual may
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rd
Party supplied computer programs stored in semiconductor
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rd
Party supplied SW certain exclusive rights for copyrighted computer programs, including the
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rd
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rd
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implication, estoppel or otherwise, any license under the copyrights, patents or patent applications
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rd
Party supplied SW, except for the normal non-exclusive, royalty free license to
use that arises by operation of law in the sale of a product.

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Usage and Disclosure Restrictions
License Agreements
The software described in this document is the property of Titan and its licensors. It is furnished by
express license agreement only and may be used only in accordance with the terms of such an
agreement.
Copyrighted Materials
Software and documentation are copyrighted materials. Making unauthorized copies is prohibited
by law. No part of the software or documentation may be reproduced, transmitted, transcribed,
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by any means, without prior written permission of Titan.
High Risk Materials
Components, units, or third-party products used in the product described herein are NOT fault-
tolerant and are NOT designed, manufactured, or intended for use as on-line control equipment in
the following hazardous environments requiring fail-safe controls: the operation of Nuclear
Facilities, Aircraft Navigation or Aircraft Communication Systems, Air Traffic Control, Life Support,
or Weapons Systems (“High Risk Activities”). Titan and its supplier(s) specifically disclaim any
expressed or implied warranty of fitness for such High Risk Activities.
Trademarks
The Titan Logo is a registered trademark. All other product or service names are the property of
their respective owners.
Copyright © Titan Automotive Solutions NV.

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ATOP 3.5G (OM12030)
Automotive telematics on-board unit platform 3.5G
1 Introduction
ATOP 3.5G (OM12030) is Titan’s platform for automotive telematics on-board units (OBU's) for
applications such as road pricing and eCall, based on the following technologies:
3G cellular for voice and data communication
GPS/GLONASS for positioning service
NFC for short range communication, e.g. configuration and law enforcement
SmartMX smartcard with Java card JCOP OS for security
J9 Virtual Machine for application portability and easy creation
Dedicated processor for Real-Time and connection to system via ADC, CAN, UART,
Ethernet, USB
Backward hardware compatibility with ATOP 2.5G EVO (OM12001)
Designed for automotive markets
1
Thanks to on-board ATOP 3.5G security resources, product developers and manufacturers can
offer products which guarantee fraud prevention and tamper evidence without extra effort for
additional security precautions. These products can be used in end-to-end transaction systems
requiring Common Criteria level 5+.
ATOP 3.5G can be used by itself as a complete solution for GNSS-3G based road pricing and
eCall applications. In this case, ATOP 3.5G just needs to be complemented with a power supply,
speaker, microphone, some knobs and an optional display. ATOP 3.5G provides the processing
power and software application environment resources on board to complement road pricing and
eCall with some other added value telematics services.
ATOP 3.5G can also be applied as a front end for more elaborate telematics products, by making
its resources, i.e. GNSS, mobile communication, security (ID authentication) available for use by
other resources in the OBU.
Three different 3G band configuration variants are defined for OM12030:
World market configuration
American market configuration
Pacific market configuration
For applications where security is not paramount, such as eCall, variants without NFC short
range communication and/or the SmartMX security processor are available.
1
In accordance with Titan’s Robustness Validation, using AEC-Q100-defined qualification tests.

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2 General description
Figure 1 represents ATOP 3.5G connections in a typical application, with its connection to
batteries, antennas and USIM. For communication with the external world, serial link, GPIOs, and
ADCs will connect to screen, keys, and sensors. UART, CAN, SDIO, Ethernet or USB can be used
to connect to an on-board computer.
Figure 1 ATOP 3.5G module connections
Figure 2 represents a more conceptual view of ATOP from a system point of view, showing three
main components:
Application processor: This processor will run code specific to the application (road
tolling, insurance ...) which is portable from one platform to another one in order to avoid
recertification. The application drives the three following conceptual co-processors:
oA Positioning Processor provides accurate location information to the
application;
oAn NFC Processor
2
provides connection to an external vignette, card reader, or
other NFC enabled device to increase application security;
oA Communication Processor allows the application to connect to servers and
receive update and notifications, receive or generate voice call or SMS.
2
Only for OM12030/1X0, with X as defined in Section 5.

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Security Processor
3
: This processor provides a root of trust for signing messages to
servers; authenticates the presence of an external vignette; and/or runs multiple security
applications.
Utility Processor: This processor takes care of all housekeeping tasks such as
connecting to external interfaces, displays, etc. but also handles power management,
waking-up and booting-up the system, i.e. all support tasks which are not part of the
high-level applications but are required to make the system work.
Figure 2 ATOP conceptual view
3 Features and benefits
Utility processor for interfacing with external world and house-keeping
oARM Cortex M3 microcontroller with Ethernet, CAN, USB Host, Device and
OTG, UART, SPI-bus, I
2
C-bus, ADCs, DAC, GPIOs, and PWMs
oInternal temperature sensor
Application processor to run customer application code
oVirtual Machine for customer application
oCommunication coprocessor with Quad-band 3.5G/EDGE/GPRS/GSM terminal
oGPS/GLONASS receiver
Near Field Communication (NFC) coprocessor to connect to external vignette, smart
card, mobile phone
2
Security processor for providing a source of trust
3
oSmartMX smartcard running JCOP 2.4.2
Mandatory and voluntary certification
oRED and FCC passed for safety, EMC, and RF
oCertification for GCF, including field test
oCertification for PTCRB
oCertification for AT&T
Designed and qualified for use in automotive applications
1
-40 °C to +85 °C / limited operating range as defined in Table 12
3
Only for OM12030/1X0 and OM12030/2X0, with X as defined in Section 5.

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4 Applications
ATOP 3.5G can be used for telematics applications where tamper-resistance, confidentiality,
integrity and authenticity of end-user information are required, e.g.:
Road pricing
Pay as you drive insurance
Stolen vehicles tracking
Emergency call
Internet connectivity
5 Ordering information
ATOP 3.5G is defined in multiple variants:
Table 1 Type names
Type number Package
Name Description
OM12030/X00
[1]
LGA350 Worldwide Quad-band UMTS 2100 (I), 1900 (II), 850 (V) including 800
(VI), 900 (VIII)
OM12030/X10
[1]
North American Quad-band UMTS 2100 (I), 1900 (II), 1700 (IV), 850 (V)
including 800 (VI)
OM12030/X20
[1]
Pacific Quad-band UMTS 2100 (I), 1800 (III) including 1700 (IX), 850 (V)
including 800 (VI), 900 (VIII)
[1] X = 1 Includes NFC short range communication and theSmartMX security element.
Feature combination nicknamed “Full”.
X = 0 Omits NFC short range communication and the SmartMX security element.
Feature combination nicknamed “Minus”.
X = 2 Omits NFC short range communication but retains the SmartMX security element.
Feature combination nicknamed “Auth”.
All variants support 2G bands 850, 900, 1800, and 1900.

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6 Block diagram
Figure 3 represents the data connections within the ATOP 3.5G module.
Two main groups of components can be distinguished:
The first group includes the cellular baseband, GPS/GLONASS and secure element
(SMX). They offer to the application running on a Virtual Machine all services required
for telematics applications.
The second group includes the microcontroller which takes care of interfacing with the
external world via its interfaces: Ethernet, USB, CAN, UARTs, SPIs, GPIOs, PWMs, and
ADCs.
Depending on which ATOP software features are used in the customer application, some of its
interfaces that are exported due to multiplexing may be used internally and thus may not be
usable by the application.
Figure 3 ATOP 3.5G internal connections

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7 Pinning information
7.1 Pinning
Figure 4 shows a transparent top view of ATOP 3.5G to identify all pins.
Figure 4 ATOP 3.5G pin configuration
7.2 Pin description
7.2.1 Module pinning list
Table 2 ATOP 3.5G pinning list
Symbol
[1]
Pin Level Description
[2]
Utility processor
UART0
MC_P002_TXD0_AD07 M15 3.0 transmitter output for UART0 [3]
MC_P003_RXD0_AD06 M19 3.0 receiver input for UART0 [3]
UART1
MC_P015_TXD1_SCK0_SCK V15 3.0 transmitter output for UART1 [4][5]
MC_P016_RXD1_SSEL0_SSEL T7 3.0 receiver input for UART1 [4][5]
MC_P022_RTS1_TD1 T9 3.0 ready to send [5]
MC_P017_CTS1_MISO0_MISO V13 3.0 clear to send [4][5]
MC_P021_RI1_RD1 R10 3.0 ring indicator [5]
MC_P018_DCD1_MOSI0_MOSI R11 3.0 data carrier detect [4][5]
UART2
MC_P010_TXD2_SDA2_MAT30 R13 3.0 transmitter output for UART2 [5]

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Symbol
[1]
Pin Level Description
[2]
MC_P011_RXD2_SCL2_MAT31 U10 3.0 receiver input for UART2 [5]
UART3
MC_P428_RXMCLK_MAT20_TXD3 V14 3.0 transmitter output for UART3 [5][6]
MC_P429_TXMCLK_MAT21_RXD3 N11 3.0 receiver input for UART3 [5][6]
I
2
C-bus 0
MC_P028_SCL0_USBSCL T12 3.0 I
2
C-bus clock input/output [7]
MC_P027_SDA0_USBSDA T11 3.0 I
2
C-bus data input/output [7]
SSI
MC_P007_I2STXCLK_SCK1_MAT21 T18 3.0 serial clock [5]
MC_P009_I2STXSDA_MOSI1_MAT23 V18 3.0 master out/slave in [5]
MC_P008_I2STXWS_MISO1_MAT22 V17 3.0 master in/slave out [5]
MC_P006_I2SRXSDA_SSEL1_MAT20 R18 3.0 slave select [5]
I
2
S-bus
MC_P023_AD00_I2SRXCLK_CAP30 P16 3.0 receive serial clock [3]
MC_P024_AD01_I2SRXWS_CAP31 M16 3.0 receive word select [3]
MC_P025_AD02_I2SRXSDA_TXD3 N16 3.0 receive data [3]
MC_P211_EINT1_I2STXCLK T13 3.0 transmit serial clock [8]
MC_P212_EINT2_I2STXWS R9 3.0 transmit word select [8]
MC_P213_EINT3_I2STXSDA T10 3.0 transmit data [8]
CAN1
MC_P000_RD1_TXD3_SDA1 T14 3.0 receive data [5]
MC_P001_TD1_RXD3_SCL1 R12 3.0 transmit data [5]
CAN2
MC_P004_I2SRXCLK_RD2_CAP20 P19 3.0 receive data [5]
MC_P005_I2SRXWS_TD2_CAP21 P15 3.0 transmit data [5]
Universal Serial Bus (USB)
MC_P029_USBDP N12 USB data P [9]
MC_P030_USBDN L13 USB data N [9]
MC_P130_VBUS_AD04 L12 USB V
bus
detect [3]
MC_P209_USBCNT_RXD2 R14 USB device connect [5]
Ethernet
MC_P115_ENETREFCLK T19 3.0 [5]
MC_P116_ENETMDC U18 3.0 [5]
MC_P100_ENETTXD0 R16 3.0 [5]
MC_P101_ENETTXD1 R15 3.0 [5]
MC_P104_ENETTXEN V19 3.0 [5]
MC_P109_ENETRXD0 T15 3.0 [5]
MC_P110_ENETRXD1 T16 3.0 [5]
MC_P114_ENETRXER T8 3.0 [5]

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Symbol
[1]
Pin Level Description
[2]
MC_P108_ENETCRS P14 3.0 [5]
MC_P117_ENETMDIO V16 3.0 [5]
Control
Analog IOs
MC_P026_AD03_AOUT_RXD3 N18 3.0 digital analog converter output [10]
GPIO/PWM
MC_P210_EINT0_NMI W14 3.0 external interrupt; internal pull up
MC_P119_MCOA0_CAP11 N13 3.0 PWM, event capture input, ... [5]
MC_P118_USBLD_PWM11_CAP10 N15 3.0
MC_P122_MCOB0_USBPWRD_MAT10 M10 3.0
MC_P129_MCOB2_PCAP11_MAT01 M11 3.0
Debug Interfaces
Microcontroller JTAG
MC_JTAG_TCK_SWDCLK K16 3.0 external pull down required; [11]
MC_JTAG_TDO_SWO K19 3.0 [5]
MC_JTAG_TDI L16 3.0 [12]
MC_JTAG_TMS_SWDIO L18 3.0 [12]
MC_JTAG_RTCK M18 3.0 [11]
MC_JTAG_TRST K18 3.0 [12]
Microcontroller PC trace 3.0
MC_P206_TRCLK_PCAP10_RI1 N10 3.0 [5]
MC_P205_TRDATA0_PWM16_DTR1 N9 3.0 [5]
MC_P204_TRDATA1_PWM15_DSR1 P18 3.0 [5]
MC_P203_TRDATA2_PWM14_DCD1 M12 3.0 [5]
MC_P202_TRDATA3_PWM13_CTS1 N8 3.0 [5]
Audio interfaces
Analog in
BB_AUDIO_IN1_N G12 microphone 1 (optionally digital)
BB_AUDIO_IN1_P H13
BB_AUDIO_IN1_BIAS G13
BB_AUDIO_IN2_N G16 microphone 2
BB_AUDIO_IN2_P F16
BB_AUDIO_IN2_BIAS G15
BB_AUDIO_IN_L H14 line in left
BB_AUDIO_IN_R J14 line in right
Analog out
BB_AUDIO_OUT1_LP J15 positive left out
BB_AUDIO_OUT1_LN H15 negative left out
BB_AUDIO_OUT1_2_RP K13 positive right out
BB_AUDIO_OUT1_2_RN K15 negative right out

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Symbol
[1]
Pin Level Description
[2]
BB_AUDIO_SPKL_P D17 positive speaker left out
BB_AUDIO_SPKL_N E17 negative speaker left out
BB_AUDIO_SPKR_P F17 positive speaker right out
BB_AUDIO_SPKR_N G17 negative speaker right out
Digital
BB_I2S_SCLK_PCM_CLK E14 1.8
BB_I2S_WS_PCM_SYNC D15 1.8
BB_I2S_DOUT_PCM_DATA_IN E12 1.8
BB_I2S_MCLK_PCM_DATA_OUT E13 1.8
BB_I2S_DIN G14 1.8
System interfaces
USB interface
BB_USBDN U12 USB data N
BB_USBDP U11 USB data P
BB_USBID U13 USB device connect
BB_USBVBUS U14 USB V
bus
detect
SDIO interface
BB_SDIOCMD P7 2.85
BB_SDIOCLK P8 2.85
BB_SDIO_PWR_EN_N P9 2.85
BB_SDIO_DET P11 1.8 active low, no pull up needed
BB_SDIOD0 U6 2.85
BB_SDIOD1 U7 2.85
BB_SDIOD2 U8 2.85
BB_SDIOD3 U9 2.85
USIM interface ISO7316-3 class B/C I/O levels
BB_SIM_DATA E16
BB_SIM_CLK D14
BB_SIM_RST D13
BB_USIM_DETEC_N L14 active low, no pull up needed
Battery and power management
VBAT_RTC_SNK J18 power supply for microcontroller
RTC battery
VBAT_SNK J2;J4 power supply for whole system
except RF power amplifier and
Utility Processor [13]
VBAT_PA_SNK J1;K1;K2 power supply for RF power
amplifier [13]
VBAT_MC_SNK K4 main power supply for Utility
Processor
VDD_SPKR H17 power supply for class D amplifier

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Symbol
[1]
Pin Level Description
[2]
VCHG_SNK G10;H10 charger supply connection
VBAT_SENSE E10 battery voltage sense
BB_ICHG H11 charger output
BB_BATT_FET_N E11 external charge FET control
BB_BATT_THERM H18 battery thermistor
VIO_REF P5 voltage (1.8 V) reference for
baseband digital interface
VADC_REF W16 voltage reference for MC_ADC
VADC_GND W17 ground reference for MC_ADC
VUSIM_SRC J13 USIM power supply
VDD_3V0_SRC N19 microcontroller current source and
voltage reference
VDD_3V0_SRC_ENA W18 enables VDD_3V0_SRC (active
HIGH, internal pull up)
Clock generation
BB_EXT_CLK D10 2.6 clock source
MC_XTAL1 M13 optional quartz for microcontroller
MC_XTAL2 N7
GPS_1PPS R4 1.8 one pulse per second (output)
System reset
MC_RESET L15 3.0 reset ATOP; internal pull up; [14]
Antennas
NFC antenna
NFC_ANT1 W10 TX1
NFC_ANT2 W11 TX2
NFC_ANT3 V12 RX
Cellular antenna
CELL_ANT1 C1 [15]
CELL_ANT2 A3 [15]
GPS antenna
GPS_PAS_ANT V1 passive GPS antenna input
GPS_ACT_ANT W3 active antenna input
GPS_ACT_ANT_BIAS T4 active antenna bias (1 V PIN diode
drop inside ATOP 3.5G) [16]
GPS_PAS_ANT_DIS T2 passive antenna disable:
3-state: internal LNA enabled;
active LOW: internal LNA disabled
Industrial test
Baseband JTAG
BB_JTAG_NTRST E9 1.8
BB_JTAG_TCK G7 1.8

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Symbol
[1]
Pin Level Description
[2]
BB_JTAG_TDI G8 1.8
BB_JTAG_RTCK G9 1.8
BB_JTAG_TDO H7 1.8
BB_JTAG_TMS J7 1.8
Other baseband debug
BB_BOOTMODE J8 1.8 internal pull up; high = normal boot;
low = flash mode
BB_BOOT_SCUR P12 1.8 used for debug of Secure Boot
BB_PS_HOLD H8 used for JTAG debug of
Application
Processor
BB_PON_RESETN D12
Reserved for future use – Do not connect
F15;H9;H12;H16;J16;
J17;K12;L17;M2;M4;M5;
M14;M17;N2;N4;N17;
P2;P4;P13;P17;R5;R7;
R8;R17;T17;U4;U5;U15;
U16;V5;V7;V8
Ground
GND A1;A4;A5;A6;A7;A8;A9;
A10;A11;A12;A13;A14;
A15;A16;A17;A18;A19;
B1;B2;B3;B4;B5;B6;B7;
B8;B9;B10;B11;B12;
B13;B14;B15;B16;B17;
B18;B19;C2;C3;C4;C5;
C6;C7;C8;C9;C10;C11;
C12;C13;C14;C15;C16;
C17;C18;C19;D1;D2;
D3;D4;D5;D6;D7;D8;
D9;D11;D16;D18;D19;
E1;E2;E3;E4;E5;E6;E7;
E8;E15;E18;E19;F1;F2;
F3;F4;F5;F6;F7;F8;F9;
F10;F11;F12;F13;F14;
F18;F19;G1;G2;G3;G4;
G5;G6;G11;G18;G19;
H1;H2;H3;H4;H5;H6;
H19;J3;J5;J6;J12;J19;
K3;K5;K6;K7;K8;K14;
K17;L1;L2;L3;L4;L5;L6;
L7;L8;L19;M1;M3;M6;
M7;M8;M9;N1;N3;N5;
N6;N14;P1;P3;P6;P10;
R1;R2;R3;R6;R19;T1;
T3;T5;T6;U1;U2;U3;
U17;U19;V2;V3;V4;V6;
V9;V10;V11;W1;W2;
W4;W5;W6;W7;W8;W9;
W12;W15;W19

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Symbol
[1]
Pin Level Description
[2]
Unused
A2;W13
[1] Pin names are encoded as follows: MC_Pxyy_iii_jjj_kkk indicates a microcontroller pin. Each pin can
be configured between several functions (typically 4), all mentioned in the pin name:
Pxyy: GPIO yy of GPIO port x;
AD0x: ADC input x;
EINTx: external interrupt x;
MATxy: match output for timer x, channel y;
PCAPxy: capture input for PWM x, channel y;
PWMxy: PWM x, channel y;
RDx/TDx: CAN port x;
SDx/SCLx: I
2
C-bus x;
TXx/RXy: UART x;
BB_xxx indicates a pin connected respectively to baseband;
GPS_xxx indicates a pin connected respectively to GPS/GLONASS;
NFC_xxx: indicates a pin connected respectively to NFC;
Vxxx_REF indicates a voltage reference – no current should be drawn from this pin;
Vxxx_SNK indicates a voltage sink – current is drawn by this pin;
Vxxx_SRC indicates a current source – current can be drawn from this pin.
[2] Only the main function is described for microcontroller pins, but all functions available for a given pin
can be found in its name.
[3] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input.
When configured as an ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant.
[4] SSP0 is used internally and therefore is not available for customer application.
[5] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
[6] V14 and N11 optionally connected to BB_UART_RX/BB_UART_TX for debugging.
[7] Open-drain 5 V tolerant digital I/O pad, compatible with I
2
C-bus 400 kHz specification. This pad
requires an external pull up to provide output functionality. When power is switched off, this pin is
connected to the I
2
C-bus and does not disturb the I
2
C-bus lines. Open-drain configuration applies to
all functions on this pin.
[8] 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
[9] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification,
revision 2.0 (Full-speed and Low-speed mode only). This pad is not 5 V tolerant.
[10] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When
configured as the DAC output, digital section of the pad is disabled.
[11] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. Internal pull up and pull
down resistors disabled.
[12] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and internal pull up
resistor.
[13] The VBAT_SNK and VBAT_PA_SNK pins should be supplied only whenever VBAT_MC_SNK is
supplied.
[14] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
[15] Cellular antennas switchable under control of the Utility Processor.
[16] A minimum current of 1 mA is required to minimize insertion loss. Maximum rating pin diode 100 mA.

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7.2.2 Internal pins list
Table 3 lists a number of internal pins controlled by the Utility Processor thatareof interest to
ATOP 3.5G application programmers. Most of these pins are controlled by low-level software
drivers provided by Titan and so should not be controlled directly. They are there described only
for reference.
Table 3 Internal microcontroller pins, controlled by Titan-provided libraries
All these pins are controlled via Titan-provided libraries and should not be used/controlled directly in any way.
Pin name GPIO number Description
BB_RESETN P1.25 0 = reset Application Processor, otherwise should be left floating
BB_POK P1.28 0 = enable Application Processor
BB_SSI[3:0] P1.20 serial communication channel
P1.21
P1.23
P1.24
BB_SDB[4:0] P2.0 internal communication channel
P2.1
P2.7
P2.8
P3.26
ANT_SW P3.25 antenna switch
BB_UART_RX P4.28 BB UART internally connected to MC UART3 by means of level
shifter
BB_UART_TX P4.29
INT_TEMP P1.31 ADC input to internal temperature sensor. A Titan-provided
function call converts value to °C. For more information see
section 12.1.
I2C_SDA P0.19 [1] I
2
C bus to SmartMX security processor bridge
I2C_SCL P0.20 [1]
I2C_GATE P2.1 [1] SmartMX security processor bridge control line. This is used to
switch the SmartMX data communication channel between the
base band and the Utility Processor (see Figure 3). This is shared
with one of the BB_SDB pins. For detailed usage instructions, see
Ref 12.
SMX_NRESET P1.26 [1] SmartMX security processor reset line
RFU P1.27 32KHz tree distribution
[1] Only for OM1230/1X0 and OM12030/2X0, with X as defined in Section 5. On all other ATOP 3.5G
variants this pin is RFU.

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8 Functional description
8.1 Utility Processor
The LPC1768 Utility Processor is responsible for tasks such as:
booting the system
handling RTC and regular wake-up
interfacing with external sensors, display, buttons via I
2
C-bus, SPI-bus, UART, ...
communicating with others car’s units via CAN, UART, Ethernet, ...
controlling operator access for firmware upgrade, data retrieval via USB, UART, ...
managing eCall access through the lower layers of the Application Processor. Due to
license restrictions, only service calls are allowed from the J9 VM, no eCalls.
monitoring internal thermal sensor
Except for a few services provided by Titan to handle communication between the
applications running on the Virtual Machine and virtualized external devices, the Utility
Processor is completely available to the application developer.
8.1.1 General features
ARM Cortex-M3 microcontroller, running up to 100 MHz
512 KB on-chip Flash Program Memory with In-System Programming (ISP) and In-
Application Programming (IAP) capabilities. Single Flash sector or full-chip erase in 100
ms and 256 bytes programming in 1 ms. Flash program memory is on the ARM local bus
for high performance CPU access
o10000 erase cycles
4
o10 years retention powered on; 20 years powered off
oFirst 16 erase block are 4 KB large, others are 32 KB large
64 KB RAM memory:
o32 KB Static RAM with local code/data bus for high-performance CPU access
o2 * 16 KB Static RAM blocks with separate access paths for higher throughput,
for Ethernet, USB, DMA memory as well as for CPU code and data
oThese SRAM blocks may be used for Ethernet, USB, and DMA memory, as well
as for general-purpose CPU instruction and data storage for general-purpose
SRAM
Multilayer AHB matrix interconnect with separate bus for each AHB master, providing
simultaneous DMA and program execution from on-chip flash with no contention
between these functions
Nested Vectored Interrupt Controller (NVIC), supporting up to 33 vectored interrupts
8 channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that
can be used with the SSP, serial interfaces, the I2S-bus port, as well as for memory-to-
memory transfers
4
If data needs to be saved regularly by Utility Processor, it is advised to use an external EEPROM connected to I
2
C-bus or
SPI-bus.

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Serial interfaces available externally:
o3 UARTs with fractional baud rate generation, one with modem control I/O, and
one with IrDA support, all with FIFO. These reside on the APB-bus
o1 SSP controller with FIFO and multi-protocol capabilities, as well as a SPI port,
sharing its interrupt. The SSP controller can be used with the GPDMA controller
and reside on the APB-bus
o2 I
2
C-bus interfaces reside on the APB-bus. The I
2
C-bus interfaces are
expansion I
2
C-bus interfaces with standard port pins
oI
2
S-bus (Inter-IC Sound) interface for digital audio input or output, residing on the
APB bus. The I
2
S-bus interface can be used with the GPDMA
o2 channels with Acceptance Filter/FullCAN mode residing on the APB-bus
High-speed serial interfaces
oUSB 2.0 Full-speed Device/Host/OTG controller with on-chip PHY and
associated DMA controller
oEthernet MAC with RMII interface and dedicated DMA controller
o2 CAN channels
Other APB peripherals
o12-bit A/D converter with input multiplexing among 7 external pins
o10-bit D/A converter with DMA support
o4 general-purpose timers with a total of 8 capture inputs and ten compare output
pins each. Each timer block has an external count input
o1 PWM/Timer block with support for three-phase motor control
oReal-Time Clock (RTC) with separate power pin; clock source can be the RTC
oscillator or the APB clock oscillator
oWatchdog Timer: the watchdog timer can be clocked from the internal RC
oscillator, the RTC oscillator or the APB clock
Standard ARM Test/Debug interface for compatibility with existing tools
4 reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode and Deep
Power-down mode
4 external interrupt inputs. In addition every PORT0/2 pin can be configured as an edge
sensing interrupt
Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt)
Brownout detection with separate thresholds for interrupt and forced reset
On-chip Power-On Reset
On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz
oFor CAN and USB, a clock generated internally to ATOP 3.5G is provided or an
external crystal can be used
On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the main oscillator, the internal RC oscillator or
the RTC oscillator
Versatile pin function selections allow more possibilities for using on-chip peripheral
functions

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8.1.2 Utility Processor block diagram
Figure 5 LPC1768 block diagram
Remark: Some interfaces, such as 1 UART, 1 I
2
C-bus, 1 SSP are not available externally, as they
are used within ATOP 3.5G. For more details, refer to Section 7.2.2.