Toradex Apalis Series Guide

Apalis Computer Module
Carrier Board Design Guide

Apalis Carrier Board Design Guide
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
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Issued by:
Toradex
Document Type:
Carrier Board Design Guide
Purpose:
This document is a guideline for developing a carrier board that conforms to the specifications
for the Apalis®Computer Module
Document
Version:
1.7
Revision History
Date
Version
Remarks
8 April 2013
V1.0
Initial Release: Preliminary Version
27 August 2013
V1.1
Correction in section 4.3
26 November 2013
V1.2
Correction in Figure 23
Correction in Table 10, Table 11, Table 12, and Table 13: signals
USBH_OC# and USBH_EN pin numbers
Correction in Table 16: Description of the pins 282-302
13 April 2015
V1.3
Remove layout guide section (available in a separate document), add
descriptions of low-speed interfaces, minor corrections
Correction of mSATA schematics (Figure 15)
9 June 2016
V1.4
Section 3.5: add information about current consumption budget
16 June 2016
V1.5
Section 2.1.1: update information about preferred interfaces
Section 2.12: add recommendation using MMC1 instead of SD1 as
preferred interface
Section 0: add suitable spacer
Add information about CSI, DSI, and recovery mode
29 June 2016
V1.6
Section 2.5.2.1: Add information about incompatible USB 3.0 OTG
cables
09 October 2018
V1.7
Add missing WAKE1_MICO# pull up resistors in examples
Section 2.4: Add recommendation for TVS diodes in PoE designs
Section 2.4.2: Update recommendation for center tap voltage
Section 2.8.2.2: Correct locations of pull resistors in description
Section 2.13: Clarify 1.8V bus voltage of SD cards
Section 2.13: Add recommendation for SD card power switching
Section 2.19: Clarify and correct Audio AGND recommendations
Section 2.23.2: Update recommendation for unused touch signals
Section 3.2: Correct of POWER_ENABLE_MOCI pull down resistor
Section 3.5: Clarify POWER_ENABLE_MOCI pull down resistor
Section 4.1: Add information regarding alternate module connectors
Section 4.3: Clarify operating temperature range

Apalis Carrier Board Design Guide
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1Introduction ....................................................................................................................... 6
1.1 Overview............................................................................................................................. 6
1.2 Additional Documents .......................................................................................................... 6
1.2.1Layout Design Guide.................................................................................................6
1.2.2 Apalis Module Datasheets .........................................................................................6
1.2.3 Apalis Module Definition ............................................................................................6
1.2.4 Toradex Developer Centre.........................................................................................6
1.2.5 Apalis Evaluation Board Schematics...........................................................................7
1.2.6 Pinout Designer ........................................................................................................7
1.3 Abbreviations....................................................................................................................... 7
2Interfaces......................................................................................................................... 10
2.1 Architecture....................................................................................................................... 10
2.1.1 Standard Interfaces.................................................................................................11
2.1.2 Type-specific Interfaces...........................................................................................12
2.1.3 Pin Numbering ........................................................................................................12
2.2 PCI Express ...................................................................................................................... 13
2.2.1 PCIe Signals...........................................................................................................13
2.2.2 Reference Schematics.............................................................................................14
2.2.3 Unused PCIe Signals Termination............................................................................19
2.3 SATA................................................................................................................................ 19
2.3.1 SATA Signals..........................................................................................................19
2.3.2 Reference Schematics.............................................................................................19
2.3.3 Unused SATA Signals Termination...........................................................................22
2.4 Ethernet............................................................................................................................ 22
2.4.1 Ethernet Signals......................................................................................................22
2.4.2 Reference Schematics.............................................................................................22
2.4.3 Unused Ethernet Signals Termination.......................................................................25
2.5 USB.................................................................................................................................. 25
2.5.1 USB Signals ...........................................................................................................25
2.5.2 Reference Schematics.............................................................................................27
2.5.3 Unused USB Signal Termination ..............................................................................32
2.6 Parallel RGB LCD Interface................................................................................................ 33
2.6.1 Parallel RGB LCD Signals .......................................................................................33
2.6.2 Color Mapping.........................................................................................................34
2.6.3 Reference Schematics.............................................................................................35
2.6.4 Unused Parallel RGB Interface Signal Termination....................................................37
2.7 LVDS LCD Interface........................................................................................................... 38
2.7.1 LVDS Signals..........................................................................................................38
2.7.2 Compatibility between LVDS Configurations..............................................................38
2.7.3 Reference Schematics.............................................................................................41
2.7.4 Unused LVDS Interface Signal Termination ..............................................................41
2.8 HDMI/DVI.......................................................................................................................... 41
2.8.1 HDMI/DVI Signals ...................................................................................................42
2.8.2 Reference Schematics.............................................................................................42
2.8.3 Unused HDMI/DVI Signal Termination......................................................................44
2.9 Analogue VGA................................................................................................................... 44
2.9.1 VGA Signals ...........................................................................................................44
2.9.2 Reference Schematics.............................................................................................45
2.9.3 Unused VGA Interface Signal Termination ................................................................45
2.10 Display Serial Interface (MIPI/DSI)...................................................................................... 45
2.11 Parallel Camera Interface................................................................................................... 46
2.11.1 Parallel Camera Signals .......................................................................................46
2.11.2 Unused Parallel Camera Interface Signal Termination............................................46
2.12 Camera Serial Interface (MIPI/CSI-2).................................................................................. 46
2.13 SD/MMC/SDIO .................................................................................................................. 46
2.13.1 SD/MMC/SDIO Signals ........................................................................................47

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2.13.2 Reference Schematics .........................................................................................48
2.13.3 Unused SD/MMC/SDIO Interface Signal Termination .............................................49
2.14 I2C.................................................................................................................................... 49
2.14.1 I2C Signals ..........................................................................................................49
2.14.2 Real-Team Clock (RTC) recommendation .............................................................49
2.14.3 Unused I2C Signal Termination .............................................................................50
2.15 UART................................................................................................................................ 50
2.15.1 UART Signals......................................................................................................50
2.15.2 Reference Schematics .........................................................................................51
2.15.3 Unused UART Signal Termination.........................................................................53
2.16 SPI ................................................................................................................................... 53
2.16.1 SPI Signals..........................................................................................................54
2.16.2 Unused SPI Signal Termination ............................................................................54
2.17 CAN.................................................................................................................................. 54
2.17.1 CAN Signals........................................................................................................54
2.17.2 Reference Schematics .........................................................................................54
2.17.3 Unused CAN Interface Signal Termination.............................................................55
2.18 PWM................................................................................................................................. 55
2.18.1 PWM Signals.......................................................................................................55
2.18.2 Reference Schematics .........................................................................................55
2.18.3 Unused PWM Signal Termination..........................................................................56
2.19 Analogue Audio ................................................................................................................. 56
2.19.1 Analogue Audio Signals .......................................................................................56
2.19.2 Reference Schematics .........................................................................................56
2.19.3 Unused Analogue Audio Signal Termination ..........................................................57
2.20 Digital Audio...................................................................................................................... 57
2.20.1 Digital Audio Signals ............................................................................................57
2.20.2 Reference Schematics .........................................................................................57
2.20.3 Unused Digital Audio Interface Signal Termination .................................................58
2.21 S/PDIF (Sony-Philips Digital Interface I/O)........................................................................... 58
2.21.1 S/PDIF Signals ....................................................................................................58
2.21.2 Reference Schematics .........................................................................................58
2.21.3 Unused S/PDIF Interface Signal Termination.........................................................59
2.22 Touch Panel Interface ........................................................................................................ 59
2.22.1 Resistive Touch Signals .......................................................................................59
2.22.2 Reference Schematics .........................................................................................59
2.22.3 Unused Touch Panel Interface Signal Termination .................................................60
2.23 Analogue Inputs................................................................................................................. 60
2.23.1 Analogue Input Signals.........................................................................................60
2.23.2 Unused Analogue Inputs Signal Termination..........................................................60
2.24 Clock Output ..................................................................................................................... 60
2.24.1 Clock Output Signals............................................................................................60
2.24.2 Schematic and Layout Considerations...................................................................60
2.24.3 Unused Clock Output Signal Termination ..............................................................61
2.25 GPIO ................................................................................................................................ 61
2.25.1 GPIO Signals.......................................................................................................61
2.25.2 Unused GPIO Termination....................................................................................61
2.26 Module Recovery............................................................................................................... 62
3Power Management........................................................................................................... 63
3.1 Power Signals ................................................................................................................... 63
3.1.1 Digital Supply Signals..............................................................................................63
3.1.2 Analogue Supply Signals .........................................................................................63
3.1.3 Power Management Signals ....................................................................................63
3.2 Power Block Diagram......................................................................................................... 64
3.3 Power States..................................................................................................................... 64
3.4 Power Sequences.............................................................................................................. 66

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3.5 Reference Schematics ....................................................................................................... 69
4Mechanical and Thermal Consideration............................................................................... 71
4.1 Module Connector.............................................................................................................. 71
4.2 Fixation of the Module........................................................................................................ 71
4.3 Thermal Solution................................................................................................................ 73
4.4 Module Size ...................................................................................................................... 74
4.5 Connector and MXM SnapLock Land Pattern Requirements................................................. 75
4.6 Carrier Board Space Requirements..................................................................................... 76
5Appendix A –Physical Pin Definition and Location............................................................... 79

Apalis Carrier Board Design Guide
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1 Introduction
1.1 Overview
This document is designed to guide users through the development of a customized carrier board
for the Apalis Computer module. It describes the different interfaces and contains reference
schematics. This document reflects only the standardized primary function of the Apalis modules.
The type-specific interfaces and secondary functions are not guaranteed to be compatible between
different Apalis modules. These interfaces are described in the datasheet of each computer
module. Some Apalis modules do not feature the full set of standard interfaces. Therefore, it is
strongly recommended to read the datasheets of the modules that are intended to be used with
the carrier board.
The Apalis Computer module features new high-speed interfaces such as PCI Express, SATA, HDMI
and LVDS which require special layout considerations regarding trace impedance and length
matching. Please read carefully the Toradex Layout Design Guide for additional information to the
routing of these interfaces.
1.2 Additional Documents
1.2.1 Layout Design Guide
This document contains layout requirement specifications for the high-speed signals and helps to
avoid problems related with the layout.
http://developer.toradex.com/hardware-resources/arm-family/carrier-board-design
1.2.2 Apalis Module Datasheets
For every Apalis Module, there is a datasheet available. Among other things, this document
describes the type-specific interfaces and the secondary function of the pins. Before starting the
development of a customized carrier board, please check in this document whether the required
interfaces are really available on the selected modules.
https://www.toradex.com/products/apalis-arm-computer-modules
1.2.3 Apalis Module Definition
This document describes the Apalis Module standard. It provides additional information about the
interfaces.
http://docs.toradex.com/100240-apalis-module-specification.pdf
1.2.4 Toradex Developer Centre
You can find a lot of additional information in the Toradex Developer Centre, which is updated
with the latest product support information on a regular basis.
Please note that the Developer Centre is common for all Toradex products. You should always
check to ensure if information is valid or relevant for the Apalis modules.
http://www.developer.toradex.com

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1.2.5 Apalis Evaluation Board Schematics
We provide the completed schematics plus the Altium project file for the Apalis Evaluation Board
for free. This is a great help when designing your own Carrier Board.
http://developer.toradex.com/hardware-resources/arm-family/carrier-board-design
1.2.6 Pinout Designer
This is an interactive and useful tool for configuring the pin muxing of the Colibri and Apalis
modules. It can be really helpful in custom carrier board development on Toradex modules and
checking compatibility of existing carrier boards with our modules.
http://developer.toradex.com/knowledge-base/pinout-designer
1.3 Abbreviations
Abbreviation
Explanation
ADC
Analogue to Digital Converter
AGND
Analogue Ground, separate ground for analogue signals
Auto-MDIX
Automatically Medium Dependent Interface Crossing, a PHY with Auto-MDIX f is able to detect whether
RX and TX need to be crossed (MDI or MDIX)
CAD
Computer-Aided Design, in this document is referred to PCB Layout tools
CAN
Controller Area Network, a bus that is manly used in automotive and industrial environment
CDMA
Code Division Multiplex Access, abbreviation often used for a mobile phone standard for data
communication
CEC
Consumer Electronic Control, HDMI feature that allows to control CEC compatible devices
CPU
Central Processor Unit
CSI
Camera Serial Interface
DAC
Digital to Analogue Converter
DDC
Display Data Channel, interface for reading out the capability of a monitor, in this document DDC2B
(based on I2C) is always meant
DRC
Design Rule Check, a tool for checking whether all design rules are satisfied in a CAD tool
DSI
Display Serial Interface
DVI
Digital Visual Interface, digital signals are electrical compatible with HDMI
DVI-A
Digital Visual Interface Analogue only, signals are compatible with VGA
DVI-D
Digital Visual Interface Digital only, signals are electrical compatible with HDMI
DVI-I
Digital Visual Interface Integrated, combines digital and analogue video signals in one connector
EDA
Electronic Design Automation, software for schematic capture and PCB layout (CAD or ECAD)
EDID
Extended Display Identification Data, timing setting information provided by the display in a PROM
EMI
Electromagnetic Interference, high frequency disturbances
eMMC
Embedded Multi Media Card, flash memory combined with MMC interface controller in a BGA package,
used as internal flash memory
ESD
Electrostatic Discharge, high voltage spike or spark that can damage electrostatic- sensitive devices
FPD-Link
Flat Panel Display Link, high-speed serial interface for liquid crystal displays. In this document also called
LVDS interface.
GBE
Gigabit Ethernet, Ethernet interface with a maximum data rate of 1000Mbit/s
GND
Ground
GPIO
General Purpose Input/Output, pin that can be configured being an input or output
GSM
Global System for Mobile Communications
HDA
High Definition Audio (HD Audio), digital audio interface between CPU and audio codec
HDCP
High-Bandwidth Digital content Protection, copy protection system that is used by HDMI beside others
HDMI
High-Definition Multimedia Interface, combines audio and video signal for connecting monitors, TV sets or
Projectors, electrical compatible with DVI-D
I2C
Inter-Integrated Circuit, two wire interface for connecting low-speed peripherals

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Abbreviation
Explanation
I2S
Integrated Interchip Sound, serial bus for connecting PCM audio data between two devices
IrDA
Infrared Data Association, infrared interface for connecting peripherals
JTAG
Joint Test Action Group, widely used debug interface
LCD
Liquid Crystal Display
LSB
Least Significant Bit
LVDS
Low-Voltage Differential Signaling, electrical interface standard that can transport very high-speed signals
over twisted-pair cables. Many interfaces like PCIe or SATA use this interface. Since the first successful
application was the Flat Panel Display Link, LVDS became a synonymous for this interface. In this
document, the term LVDS is used for the FPD-Link interface.
MIPI
Mobile Industry Processor Interface Alliance
MDI
Medium Dependent Interface, physical interface between Ethernet PHY and cable connector
MDIX
Medium Dependent Interface Crossed, an MDI interface with crossed RX and TX interfaces
mini PCIe
PCI Express Mini Card, card form factor for internal peripherals. The interface features PCIe and USB 2.0
connectivity
MMC
MultiMediaCard, flash memory card
MSB
Most Significant Bit
mSATA
Mini-SATA, a standardized form factor for small solid state drive, similar dimensions as mini PCIe
MXM3
Mobile PCI Express Module (second generation), graphic card standard for mobile device, the Apalis form
factor uses the physical connector but not the pin-out and the PCB dimensions of the MXM3 standard.
N/A
Not Available
N/C
Not Connected
OD
Open Drain
OTG
USB On-The-Go, a USB host interface that can also act as USB client when connected to another host
interface
OWR
One Wire (1-Wire), low-speed interface which needs just one data wire plus ground
PCB
Printed Circuit Board
PCI
Peripheral Component Interconnect, parallel computer expansion bus for connecting peripherals
PCIe
PCI Express, high-speed serial computer expansion bus, replaces the PCI bus
PCM
Pulse-Code Modulation, digitally representation of analogue signals, standard interface for digital audio
PD
Pull-Down Resistor
PHY
Physical Layer of the OSI model
PMIC
Power Management IC, integrated circuit that manages amongst others the power sequence of a system
PU
Pull-up Resistor
PWM
Pulse-Width Modulation
RGB
Red Green Blue, color channels in common display interfaces
RJ45
Registered Jack, common name for the 8P8C modular connector that is used for Ethernet wiring
RS232
Single ended serial port interface
RS422
Differential signaling serial port interface, full duplex
RS485
Differential signaling serial port interface, half duplex, multi drop configuration possible
R-UIM
Removable User Identity Module, identifications card for CDMA phones and networks, an extension of the
GSM SIM card
S/PDIF
Sony/Philips Digital Interconnect Format, optical or coaxial interface for audio signals
SATA
Serial ATA, high-speed differential signaling interface for hard drives and SSD
SD
Secure Digital, flash memory card
SDIO
Secure Digital Input Output, an external bus for peripherals that uses the SD interface
SIM
Subscriber Identification Module, identification card for GSM phones
SMBus
System Management Bus (SMB), two wire bus based on the I2C specifications, used specially in x86
design for system management.
SoC
System on a Chip, IC which integrates the main component of a computer on a single chip
SPI
Serial Peripheral Interface Bus, synchronous four wire full duplex bus for peripherals
TIM
Thermal Interface Material, thermal conductive material between CPU and heat spreader or heat sink
TMDS
Transition-Minimized Differential Signaling, serial high-speed transmitting technology that is used by DVI
and HDMI
TVS Diode
Transient-Voltage-Suppression Diode, diode that is used to protect interfaces against voltage spikes

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Abbreviation
Explanation
UART
Universal Asynchronous Receiver/Transmitter, serial interface, in combination with a transceiver a RS232,
RS422, RS485, IrDA or similar interface can be achieved
USB
Universal Serial Bus, serial interface for internal and external peripherals
VCC
Positive supply voltage
VGA
Video Graphics Array, analogue video interface for monitors
Table 1: Abbreviations

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2 Interfaces
2.1 Architecture
The block diagram in Figure 1 shows the basic architecture of the Apalis module, depicting the
standard interfaces and some examples of type-specific interfaces.
Standard interfaces are interfaces that are compatible between different Apalis modules. The pins
are reserved for this specific function and are not used for other purpose. This guarantees electrical
compatibility between carrier board designs which only uses the standard interfaces. This helps to
ensure longevity of carrier board designs and provides support for future modules. Some modules
may not feature all the standard interfaces. In this case, for the GPIO compatible interfaces, GPIO
functionality is provided. Other interfaces on the module might be left disconnected.
Type-specific interfaces are interfaces which are not guaranteed to be functionally or electrically
compatible between modules. If a carrier board design uses such interfaces, then it is possible that
other modules in the Apalis module family do not provide these interfaces and instead provide
another interface on the associated pins. These interfaces might be electrically incompatible. In this
case, the carrier board will be restricted for use only with certain Apalis modules.
Analogue and Resistive
Touch
24 Bit Parallel LCD
Parallel Camera
Digital Audio
I2C (x3)
SPI (x2)
SATA (x1)
PCI Express (x1)
Analogue Audio
PWM (x4)
CAN (x2)
Gigabit Ethernet
USB
(2 x USB3.0)
(2 x USB2.0)
(1x USB client shared)
MMC (8 bit) SDIO (4 bit)
UART (x4)
SPDIFVGA
HDMI/DVI
Dual Channel LVDS
Display Serial Interface
(DSI)
Camera Serial Interface
(CSI)
PCI Express (x4)
Apalis Module
Function is standard: Reserved on every module (however, not necessarily
implemented on every module). Will only be used for this purpose or GPIO.
Function is type specific: May only be present on specific modules and is
not guaranteed to be electrically or functionality compatible on different
modules; the pins may be used for as yet undefined interfaces
GPIO (x8)
(dedicated, many more
available)
Figure 1: Apalis Module Architecture

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2.1.1 Standard Interfaces
The standard interfaces on the Apalis module family guarantees electrical and functional
compatibility between the module family members. The table below shows an overview of the
standard interfaces that are provided by an Apalis module. The “GPIO Capable” column indicates
whether the assigned pins can be used as GPIOs. “Yes”and “No”are self-Explanatory. “Optional”
indicates that it may be possible for some modules, but not all.
The “Standard” column indicates the number of interfaces that the specification allows for in the
standard pin-out. Customers should consult the datasheet for specific Apalis module variants to
check which interfaces are available for that module. If a module does not feature the complete
number of interfaces that is specified by the Apalis standard, the provided interfaces are tried to be
filled in the ascending order from low to high. For example, the Apalis standard features 4 UART
ports (port 1 to port 4). If a module only provides 3 UART interfaces, they are provided at port 1, 2
and 3 of the module edge connector. Port 4 will be left unconnected in this case. If a custom
carrier board only uses 2 UART interfaces, port 1 and 2 should be used. This guarantees better
compatibility with Apalis modules that do not feature all UART ports.
Special attention should be taken to the USB ports. Since only USBO1 and USBH4 are SuperSpeed
capable, The Apalis TK1 provides USBO1, USBH2, and USBH4 while USBH3 is left unconnected.
On the other hand, Apalis T30 provides USBO1, USBH2, and USBH3 while USBH4 is unconnected.
Carrier board designs which require 3 USB interfaces may need assembly option for using USBH4
instead of USBH3.
The Apalis standard features two SD/MMC interfaces. Due to the different maximum available bit
width, the interfaces are called MMC1 (up to 8-bit) and SD1 (up to 4-bit). The MMC1 interface is
the preferred one if only one SD/MMC interface is required on a carrier board. A module that
features only one SD/MMC interface will first implement the MMC1.
Description
Standard
Note
GPIO
Capable
4/5 Wire Resistive Touch
1
Touch wiper shared with analogue input 4
No
Analogue Inputs
4
Minimum 8-bit resolution, 0-3.3V nominal range
No
Analogue Audio
1
Line in L&R, Microphone in, Headphone out L&R
No
CAN
2
Optional
Digital Audio
1
HDA
Yes
Dual Channel LVDS Display
1
1x or 2x single channel or 1x dual channel mode
No
Gigabit Ethernet
1
No
GPIO
8
Yes
HDMI (TDMS)
1
No
I2C
3
Including DDC
Yes
Parallel Camera
1
8-bit YUV
Optional
Parallel LCD
1
24-bit resolution
Optional
PCI-Express (lane count)
1
Single lane and clock
No
PWM
4
Yes
SATA
1
No
SDIO
1
4-bit
Yes
SDMMC
1
8-bit
Yes
S/PDIF
1
1 input, 1 output
Optional
SPI
2
Yes
UART
4
1 Full Function, 1 CTS/RTS, 2 RXD/TXD only
Yes
USB
4
2 x USB 3.0, 2 x USB 2.0, 1 x shared host/client USB 2.0
No
VGA
1
No
Table 2: Standard Interfaces

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2.1.2 Type-specific Interfaces
Type-specific interfaces allow for the possibility of including interfaces which may not exist yet or
are yet to be widely adopted, or interfaces which may be specific to a particular device or groups of
devices. They also offer a mechanism for extending features which are present on the standard
interfaces, such as providing additional PCI-Express lanes. This provides the Apalis module with the
flexibility of being able to reconfigure a subset of pins for different uses between different modules.
It should be noted that wherever possible, type-specific interfaces will be kept common across
modules that share such interfaces. For example, if both module A and module B have three
additional PCI-Express lanes which are available in the same configurations as a type-specific
interface, then they shall be assigned to the same pins in the type-specific area of the connector.
Hence, both module A and module B shall share compatibility between these parts of the type-
specific interface.
The signal routing and need for external components for the type-specific interfaces are not
reflected in this document. Please consult the applicable Apalis module datasheet for more
information on these interfaces.
2.1.3 Pin Numbering
The diagrams below show the pin numbering schema on both sides of the module. The schema
deviates from the unrelated MXM3 standard pin numbering schema.
Pins on the top side of the module have even numbering and pins on the bottom side have odd
numbering.
The pin number increases linearly as a multiple of the pitch –that is, pins which are not assembled
in the connector (between pins 18 and 23) are also accounted for in the numbering (pins 19
through 22 do not exist). Similarly, pins which do not exist due to the connector notch are also
accounted for (pins 166 through 172).
Figure 2: Pin numbering schema on the top side of the module
0.50 1.25
1.25
1.50
Pin2
Pin4
Pin18
Pin24
Pin164Pin174Pin320
Top Side

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Figure 3: Pin numbering schema on the bottom side of the module
Figure 4: Pin numbering schema on the module connector land pattern
2.2 PCI Express
The Apalis module form factor only features one PCIe lane as standard interface. Depending on
the module, there may be additional lanes available in the type-specific area.
2.2.1 PCIe Signals
Apalis
Pin
Apalis
Signal Name
I/O
Type
Power
Rail
Description
55
PCIE1_CLK+
O
PCIe
PCIe 100MHz reference clock output positive
53
PCIE1_CLK-
O
PCIe
PCIe 100MHz reference clock output negative
49
PCIE1_TX+
O
PCIe
PCIe transmit data positive
47
PCIE1_TX-
O
PCIe
PCIe transmit data negative
43
PCIE1_RX+
I
PCIe
PCIe receive data positive
41
PCIE1_RX-
I
PCIe
PCIe receive data negative
37
WAKE1_MICO
I
CMOS
3.3V
General purpose wake signal
26
RESET_MOCI#
O
CMOS
3.3V
General reset output of the module
209
I2C1_SDA
I/O
OD
3.3V
I2C interface data, some PICe device need SMB interface for special
configuration
211
I2C1_SCL
O
OD
3.3V
I2C interface clock, some PICe device need SMB interface for special
configuration
Table 3: PCIe signals
The PCIe interface supports polarity inversion. This means that the positive and negative signal pins
can be inverted in order to simplify the layout by avoiding crossing of the signals. Some PCIe
devices support additional lane reversal for multi-lane interfaces. As the standard interfaces on
Apalis provide only a single lane PCIe interface, the lane reversal feature is not relevant to the
Apalis specification. Some Apalis modules provide additional multi-lane PCIe interfaces as type-
specific interfaces. Please consult the datasheets of such modules to determine if lane reversal is
applicable and supported.
Bottom Side
Pin1Pin23
Pin2Pin24
Pin173
Pin164Pin174
Pin321
Pin320
Pin165 Pin17
Pin18
Module Insertion Edge

Apalis Carrier Board Design Guide
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
Page | 14
2.2.2 Reference Schematics
The PCIe schematic differs depending on whether the PCIe device is soldered directly to the carrier
board (device-down) or is located on a PCIe card. Special care needs to be taken to determine as
to whether or not AC coupling capacitors are required. The maximum trace length of the lanes
depends on whether the design is for an external card or a device-down.
Every PCIe lane consists of a pair of transmitting (TX) and receiving (RX) traces. Unfortunately, the
names RX and TX can be confusing as the host transmitter needs to be connected to the receiver of
the device and vice versa. Normally, the signals are named from the host’s perspective until they
reach the pins of the PCIe device. Therefore, the transmitting pins of the Apalis modules should be
called TX at the carrier board while the receiving pins of the module should be called RX. Please
read carefully the datasheet of the PCIe device in order to make sure that RX and TX are not
inadvertently swapped.
Every PCIe device needs a 100MHz reference clock. It is not permitted to connect a reference clock
to two device loads. The Apalis module provides one reference clock output as a standard
interface. There may be additional PCIe reference clocks outputs in the type-specific area. If there
are not enough PCIe reference clocks available (e.g. if a PCIe switch is used or the PCIe interfaces
in the type-specific area do not provide additional clock outputs), a zero-delay PCIe clock buffer is
required on the baseboard. Some PCIe switches features an internal PCIe clock buffer, which can
avoid the necessity of a dedicated clock buffer.
Figure 5: PCIe reference clock buffer example
2.2.2.1 PCIe x1 Slot Schematic Example
The PCIe card slot design defines that the decoupling capacitors for the TX lanes should be placed
on the module and the RX lanes on the card. Therefore, no additional decoupling capacitors are
permitted to be placed on the carrier board in the RX, TX and reference clock lines.
MM70-314-310B1
PCIE1_RX- 41
Apalis - PCI-Express
18 of 25
PCIE1_RX+ 43
PCIE1_TX- 47
PCIE1_TX+ 49
PCIE1_CLK- 53
PCIE1_CLK+ 55
X1R
PCIE1_CLK_N
PCIE1_CLK_P PCIE1_CLK_N
PCIE1_CLK_P
PCIE1[0..1]
PCIE1A_CLK_N
PCIE1A_CLK_P
PCIE1B_CLK_N
PCIE1B_CLK_P
PCIE1C_CLK_N
PCIE1C_CLK_P
PCIE1A-C_CLK[0..5]
PCIE1A-C_CLK[0..5]
0R
R4
0R
R2 PCIE1_SDA
PCIE1_SCL
I2C1_SDA
I2C1_SCL
I2C1[0..1]
100nF
C2 100nF C3 100nF
C4 100nF C5
R1 33R
R3 33R
R5 33R
R6 33R
R7 33R
R8 33R
R10
R11
R12
R13
R14
R15 GND
1%
R16
475R
GND
GND
R9
1K
120R@100MHz
3A
L1
3.3V_PCIE_CLK_BUF3.3V_SW
3.3V_PCIE_CLK_BUF
C1
2.2uF
GND
100nF
C6
120R@100MHz
3A
L2
3.3V_PCIE_CLK_BUF 3.3V_PCIE_CLK_BUF_A
3.3V_PCIE_CLK_BUF_A
GND
3.3V_PCIE_CLK_BUF
3.3V_PCIE_CLK_BUF
3.3V_PCIE_CLK_BUF
SRC_IN
2
SRC_IN#
3OE_INV 25
DIF_1 6
SRC_STOP
16
BYPASS#/PLL
12
HIGH_BW
17
PD
13
SCLK
13
SDATA
14
OE6# 21
OE1# 8
DIF_1# 7
DIF_2 9
DIF_2# 10
DIF_5 20
DIF_5# 19
DIF_6 23
DIF_6# 22
IREF 26
VDD1
1
VDD2
5
VDD3
11
VDD4
18
VDD5
24
GND
4
ICS9DB401CGLF
GNDA 27
VDDA 28
IC1
MM70-314-310B1
Apalis - I2C
7 of 25
I2C1_SDA 209
I2C1_SCL 211
X1G
I2C1_SDA
I2C1_SCL
6X
49.9R
Optional

Apalis Carrier Board Design Guide
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
Page | 15
Figure 6: PCIe x1 Slot Block Diagram
The Apalis module standard does not feature a dedicated PCIe reset output as it does not provide
the PCIe hot-plug functionality. Therefore, the PCIe reset input (PERST#, pin A11) of the slot should
be served by the general module reset output (RESET_MOCI#). Some Apalis modules may provide
the additional hot-plug signals such as reset and hot-plug detect as secondary functions or as type-
specific interfaces. Nevertheless, as the compatibility between different Apalis modules cannot be
guaranteed using these hot-plug signals, it is recommended that the RESET_MOCI# signal is used
as reset.
The PCIe x1 slot uses two card present signals (PRSNT1#, pin A1 and PRSNT2#, pin B18) which are
shorted to the ground by the card (if it is inserted). Again, as the Apalis module standard does not
feature the PCIe hot-plug feature, these pins can be left unconnected.
The wake output of the PCIe slot (WAKE#, pin B11) can be connected to the general wake input of
the Apalis module (WAKE1_MICO#). Wake-up-capable PCIe cards such as Ethernet cards can use
this signal to wake up the module from its suspend state.
The JTAG interface on the PCIe slot can be left unconnected. This interface is only used for
debugging purposes. No termination on the carrier board is needed.
The PCIe slot pin-out features an SMB interface for additional power management control. As the
SMB and I2C buses are compatible, it is recommended that the I2C1 interface on the Apalis
module is used if the SMB interface is needed. Most PCIe cards do not make use of the SMB
interface. Therefore, these pins can be left unconnected for most applications.
In addition to the 3.3V input, the PCIe slot features an additional +3.3V aux (pin B10) and +12V
(pin A2, A3, B1 and B2). The +3.3V aux is a standby rail for cards that feature the wake up
functionality. If the card does not need to be powered in standby, it is recommended that this pin is
connected to the normal +3.3V supply. Do not leave this pin unconnected.
Not all PCIe cards need the +12V supply. For a battery powered system or a carrier board with a
wide voltage input range, it might be difficult to generate a regulated 12V rail. In this case, we
recommend checking with the PCIe card(s) manufacturer to determine if the +12V supply is
required.
PCIe
Device
PCIe
Host
PCIe Slot
Connector
Module
Connector
Apalis Module Carrier Board PCIe Card
TX
RX
RX
TX
PCIE1_TX+
PCIE1_TX-
PCIE1_RX+
PCIE1_RX-
PCIE1_TX+
PCIE1_TX-
PCIE1_RX+
PCIE1_RX-
HSOp(0)
HSOn(0)
HSIp(0)
HSIn(0)
2x 100nF
2x 100nF

Apalis Carrier Board Design Guide
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
Page | 16
Figure 7: PCIe x1 slot reference schematic
2.2.2.2 Mini PCIe Card Schematic Example
The Mini PCIe Card (also called PCI Express Mini Card, Mini PCI Express or Mini PCIe) also features
a USB 2.0 high-speed interface. In order to be compliant, the carrier board needs to provide both
interfaces, the PCIe and USB. As most of the Mini PCIe Cards use only one of its interfaces for an
embedded carrier board which is developed for a restricted set of compatible cards, it might be
sufficient to implement only the required interface. Check with the Mini PCIe Card vendor whether
the USB, PCIe or both interfaces are used by the card.
The Mini PCIe Card features the decoupling capacitors for the RX lines on the card. Therefore, no
additional decoupling capacitors should to be placed on the carrier board in either the RX, TX or
reference clock lines.
Figure 8: Mini PCIe Card Block Diagram
The Apalis module standard does not feature a dedicated PCIe reset output as it does not provide
the PCIe hot-plug functionality. Therefore, the PCIe reset input (PERST#, pin 22) of the card should
be served by the general module reset output (RESET_MOCI#). Some Apalis modules might
provide the additional hot-plug signals such as reset and hot-plug detect as secondary functions or
as type-specific interfaces. Nevertheless, as compatibility between different Apalis modules could
PRSNT1#
A1 +12V B1
+12V
A2 +12V B2
+12V
A3 RSVD B3
GND
A4 GND B4
TCK
A5 SMCLK B5
TDI
A6 SMDAT B6
TDO
A7 GND B7
TMS
A8 +3.3V B8
+3.3V
A9 TRST# B9
+3.3V
A10 +3.3VAux B10
PERST#
A11 WAKE# B11
GND
A12 RSVD B12
REFCLK+
A13 GND B13
REFCLK-
A14 PET0+ B14
GND
A15 PET0- B15
PER0+
A16 GND B16
PER0-
A17 PRSNT2# B17
GND
A18 GND B18
X2
GND GND
GND
GND
GND GND
GND
GND
GND
RESET_MOCI# WAKE1_MICO#
I2C1_SDA
I2C1_SCL
GND
PCIE1_PRSNT2# TP1
R1
4.7K
22uF
16V
+
C2
GND
22uF
10V
+
C1
GND
I2C1[0..1]
3.3V_SW
3.3V_STB3.3V_SW
3.3V
3.3V_SW12V_SW
SYSTEM_CTRL[0..1]
PCIE1_RX_N
PCIE1_RX_P PCIE1_TX_N
PCIE1_TX_PPCIE1_CLK_N
PCIE1_CLK_P
12V_SW
12V_SW
3.3V_SW
12V_SW
12V_SW
MM70-314-310B1
PCIE1_RX- 41
Apalis - PCI-Express
18 of 25
PCIE1_RX+ 43
PCIE1_TX- 47
PCIE1_TX+ 49
PCIE1_CLK- 53
PCIE1_CLK+ 55
X1R PCIE1_RX_N
PCIE1_RX_P
PCIE1_TX_N
PCIE1_TX_P
PCIE1_CLK_N
PCIE1_CLK_P
PCIE1[0..5]
MM70-314-310B1
Apalis - I2C
7 of 25
I2C1_SDA 209
I2C1_SCL 211
X1G
I2C1_SDA
I2C1_SCL
MM70-314-310B1
POWER_ENABLE_MOCI 24
Apalis - System Control
4 of 25
RESET_MOCI# 26
RESET_MICO# 28
WAKE1_MICO# 37
X1D
RESET_MOCI#
WAKE1_MICO#
PCIE1_SMDAT
PCIE1_SMCLK 0RR2 0RR3
Optional
R4
4.7K
3.3V_SW
PCIe
Device
PCIe
Host
Apalis Module Carrier Board PCIe Mini Card
TX
RX
RX
TX
PCIE1_TX+
PCIE1_TX-
PCIE1_RX+
PCIE1_RX-
PCIE1_TX+
PCIE1_TX-
PCIE1_RX+
PCIE1_RX-
PET0+
PET0-
PER0+
PER0-
2x 100nF
2x 100nF
USBHn_D+
USBHn_D-
USBHn_D+
USBHn_D-
USB_D+
USB_D-
PCIe Mini Card
Connector
Module
Connector
USB
Device
USB
Host

Apalis Carrier Board Design Guide
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
Page | 17
not be guaranteed by using these hot-plug signals, it is recommended that the RESET_MOCI#
signal is used as reset.
The clock request output of the card (CLKREQ#, Pin 7) can be left unconnected. It might also be
connected to a free GPIO on the Apalis module. In this case, the clock request functionality needs
to be implemented in software.
The wake output of the Mini PCIe Card (WAKE#, pin 1) can be connected to the general wake
input of the Apalis module (WAKE1_MICO#). Wake-up-capable Mini PCIe Cards such as Wi-Fi
cards can use this signal to wake up the module from its suspend state.
The R-UIM interface of the Mini PCIe Card (UIM, pin 8, 10, 12, 14 and 16) are only needed for
mobile broadband modem cards such as 3G cards. If the card interface needs to support such
modems, an additional SIM card holder needs to be attached to this interface.
The Mini PCIe Card pin-out features an SMB interface for additional power management control.
As the SMB and I2C buses are compatible, it is recommended that the I2C1 interface on the Apalis
module is used if the SMB interface is needed. Most PCIe cards do not make use of the SMB
interface. Therefore, these pins can be left unconnected for most applications.
Figure 9: Mini PCIe card reference schematic
Mini PCIe Latch
MECH1
67910-5700
WAKE#
1
3V3 2
COEX1
3
GND 4
COEX2
5
1V5 6
CLKREQ#
7
UIM_PWR 8
GND 9
UIM_DATA 10
REF_CLK-
11
REF_CLK+
13
GND 15
SIM_C8/RSVD 17
SIM_C4/RSVD 19
GND 21
PCIe_RX-
23
PCIe_RX+
25
GND 27
GND 29
PCIe_TX-
31
PCIe_TX+
33
GND 35
GND 37
RSVD
39
RSVD
41
GND 43
RSVD
45
RSVD
47
RSVD
49
RSVD
51
UIM_CLOCK 12
UIM_RESET 14
UIM_VPP 16
GND 18
W_DISABLE#
20
PERST#
22
3V3_AUX 24
GND 26
1V5 28
SMB_CLK
30
SMB_DAT
32
GND 34
USB_D-
36
USB_D+
38
GND 40
LED_WWAN# 42
LED_WLAN# 44
LED_WPAN# 46
1V5 48
GND 50
3V3 52
X2
7111S2015X02LF
VCC
1
RESET
2
CLOCK
3
GND
5
VPP
6
I/O
7
X3
SC4215A
NC
1
EN
2V_IN
3
NC
4
NC
5
V_OUT 6
FB 7
GND 8
GND_PAD 9
IC1
GND
10uF
10V
C2
GND
R10
20K
R9
40.2K
10uF
10V
C3 100nF
16V
C1
GND
1.5V
10uF
10V
C4
GND
33R@100MHz
3A
L1
10uF
10V
C5
GND
PCIE[0..5]
PCIE1_UIM_PWR
PCIE1_UIM_RESET
PCIE1_UIM_CLK
PCIE1_UIM_VPP
PCIE1_UIM_DATA
GND
RESET_MOCI#
WAKE1_MICO#
PCIE1_SMDAT
PCIE1_SMCLK0RR2 0RR3I2C1_SDA I2C1_SCL
GND PCIE1_WDISABLE#
3.3V_PCIE 1.5V
I2C1[0..1]
LED1
LED2
LED3
150R
R6
150R
R7
150R
R8
3.3V_PCIE
PCIE1_WWLAN#
PCIE1_WLAN#
PCIE1_WPAN#
USBH_D_P
USBH_D_N
USBH[0..1]
3.3V_PCIE
3.3V_SW3.3V_SW
PCIE1_RX_N
PCIE1_RX_P
PCIE1_CLK_N
PCIE1_CLK_P
PCIE1_TX_N
PCIE1_TX_P
PCIE_FB
R1
47K
3.3V_STB
3.3V_PCIE
3.3V_PCIE
Power
1.5V
1.5V
MM70-314-310B1
PCIE1_RX- 41
Apalis - PCI-Express
18 of 25
PCIE1_RX+ 43
PCIE1_TX- 47
PCIE1_TX+ 49
PCIE1_CLK- 53
PCIE1_CLK+ 55
X1R PCIE1_RX_N
PCIE1_RX_P
PCIE1_TX_N
PCIE1_TX_P
PCIE1_CLK_N
PCIE1_CLK_P
MM70-314-310B1
Apalis - I2C
7 of 25
I2C1_SDA 209
I2C1_SCL 211
X1G
I2C1_SDA
I2C1_SCL
MM70-314-310B1
POWER_ENABLE_MOCI 24
Apalis - System Control
4 of 25
RESET_MOCI# 26
RESET_MICO# 28
WAKE1_MICO# 37
X1D
RESET_MOCI#
WAKE1_MICO#
3.3V_PCIE
3.3V_PCIE
MM70-314-310B1
USBO1_VBUS 60
Apalis - USB
3 of 25
USBH2_D- 82
USBH2_D+ 80
USBO1_SSTX- 70
USBO1_SSTX+ 68
USBO1_ID 72
USBO1_SSRX- 64
USBO1_SSRX+ 62
USBH_EN 84
USBH3_D- 88
USBH3_D+ 86
USBH4_D- 100
USBH4_D+ 98
USBO1_D- 76
USBO1_D+ 74
USBH_OC# 96
USBH4_SSTX- 104
USBH4_SSTX+ 106
USBH4_SSRX- 92
USBH4_SSRX+ 94
USBO1_OC# 262
USBO1_EN 274
X1C
USBH_D_P
USBH_D_N
Optional
JP1
R4
4.7K
3.3V

Apalis Carrier Board Design Guide
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
Page | 18
2.2.2.3 PCIe x1 Device-Down Schematic Example
Device-Down means that the PCIe device is soldered directly to the carrier board. The decoupling
capacitors for the RX lanes (TX from the device) need to be placed on the carrier board. As the
capacitors for the TX lanes are located on the Apalis module, no additional capacitors should be
place on the TX lines. The reference clock lines do not need decoupling capacitors.
Figure 10: PCIe Device-Down block diagram
The schematic diagram shown below is an example of a device-down design of a gigabit Ethernet
controller. Please be aware that the TX lane from the module needs to be connected to the RX
input of the controller. The RX lane from the module needs to be connected to the TX output of the
controller. Check your device carefully to determine whether it needs this crossing or not.
Figure 11: PCIe Device-Down example schematic
PCIe
Device
(down)
PCIe
Host
Module
Connector
Apalis Module Carrier Board
TX
RX
RX
TX
PCIE1_TX+
PCIE1_TX-
PCIE1_RX+
PCIE1_RX-
PCIE1_TX+
PCIE1_TX-
PCIE1_RX+
PCIE1_RX-
PCIE_RX+
PCIE_RX-
PCIE_TX+
PCIE_TX-
2x 100nF
2x 100nF
MM70-314-310B1
PCIE1_RX- 41
Apalis - PCI-Express
18 of 25
PCIE1_RX+ 43
PCIE1_TX- 47
PCIE1_TX+ 49
PCIE1_CLK- 53
PCIE1_CLK+ 55
X1R ETH1[0..9]
0RR4 0RR3 ETH1_SDA
ETH1_SCL
I2C1_SDA
I2C1_SCL
I2C1[0..1]
MM70-314-310B1
Apalis - I2C
7 of 25
I2C1_SDA 209
I2C1_SCL 211
X1G
I2C1_SDA
I2C1_SCL
I210
VDD3P3_1
10
VDD3P3_2
27
VDD3P3_3
41
VDD3P3_4
51
VDD3P3_5
64
VDD1P5_1
47
VDD1P5_2
56
VDD0P9_1
11
VDD0P9_2
32
VDD0P9_3
42
VDD0P9_4
59
RSVD_22_NC
22
VDD1P5_OUT 39
VDD0P9_OUT 40
CTOP 40
CBOT 37
GND HS
IC1B
PCIE1_RX_N
PCIE1_RX_P
PCIE1_TX_N
PCIE1_TX_P
PCIE1_CLK_N
PCIE1_CLK_P
PCIE1_RX_S_N
PCIE1_RX_S_P
PCIE1_TX_N
PCIE1_TX_P
PCIE1_CLK_N
PCIE1_CLK_P
PCIE1[0..5]
100nF
C1
100nF
C2
PCIE1_RX_N
PCIE1_RX_P
SYSTEM_CTRL[0..1]
MM70-314-310B1
POWER_ENABLE_MOCI 24
Apalis - System Control
4 of 25
RESET_MOCI# 26
RESET_MICO# 28
WAKE1_MICO# 37
X1D
RESET_MOCI#
WAKE1_MICO# Optional
RESET_MOCI#
WAKE1_MICO#
I210
PE_RX_P
24
PE_CLK_P
26
PE_CLK_N
25
JTAG_TCK
19
JTAG_TDO
4
JTAG_TMS
18
JTAG_TDI
29
SMB_DATA
36 SMB_CLK
34
PE_TX_P
21
PE_TX_N
20
SDP0
63
XTAL_1
46
MDI_0_P 58
PE_RX_N
23
PE_RST#
17
PE_WAKE#
16
DEV_OFF#
28
LAN_PWR_GOOD
1
SMB_ALERT#
35
SDP1/PCIE_DIS
61
SDP2
62
SDP3
60
XTAL_2
45
MDI_0_N 57
MDI_1_N 54
MDI_1_P 55
MDI_2_N 52
MDI_2_P 53
MDI_3_N 49
MDI_3_P 50
NVM_CS# 15
NVM_SK 13
NVM_SI 12
NVM_SO 14
LED0 31
LED1 30
LED2 33
NC_SI_TXD0 9
NC_SI_TXD1 8
NC_SI_RXD0 6
NC_SI_RXD1 5
NC_SI_ARB_IN 43
NC_SI_ARB_OUT 44
NC_SI_CLK_IN 2
NC_SI_CRS_DV 3
NC_SI_TX_EN 7
RSET 48
IC1A
R1 10K
R2 10K
R5 10K
3.3V_SW
R7 10K
GND
R14 10R
25.0000 MHz - 22pF -50ESR
1 2
OSC1 33pF 25V
C433pF
25V
C3
GNDGND
R13 10K
R12 10K
R11 10K
R15 4.99K
GND
R10 10K
R9 10K
R8 10K
R6 10K
3.3V_SW
ETH1_MDI0_N
ETH1_MDI1_P
ETH1_MDI1_N
ETH1_MDI2_P
ETH1_MDI2_N
ETH1_MDI3_P
ETH1_MDI3_N
ETH1_MDI0_P
ETH1_ACT
ETH1_LINK
10uF
C6 100nF C7 100nF C8 100nF C9 100nF C10
47uF
C5
3.3V_SW
3.3V_SW
3.3V_SW
GND
10uF
C13 100nF C14 100nF C15 100nF C16 100nF C17
GND
1.5V_LAN
10uF
C18 100nF C19 100nF C20 100nF C21 100nF C22
GND
0.9V_LAN
100nF
C24
GND
NA
39nF
25V
C23
10uF
C12
GND
1.5V_LAN
0.9V_LAN
10uF
C11
GND
GND
ETH1[0..9]
R16
4.7K
3.3V

Apalis Carrier Board Design Guide
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
Page | 19
2.2.3 Unused PCIe Signals Termination
Apalis
Pin
Apalis
Signal Name
Recommended Termination
55
PCIE1_CLK+
Leave NC if not used
53
PCIE1_CLK-
Leave NC if not used
49
PCIE1_TX+
Leave NC if not used
47
PCIE1_TX-
Leave NC if not used
43
PCIE1_RX+
Preferable connect to GND if not used or leave NC
41
PCIE1_RX-
Preferable connect to GND if not used or leave NC
37
WAKE1_MICO
Add pull-up resistor or disable the wake function in software
26
RESET_MOCI#
Leave NC if not used
209
I2C1_SDA
Add pull-up resistor or disable the I2C function in software
211
I2C1_SCL
Add pull-up resistor or disable the I2C function in software
Table 4: Unused PCIe Signals Termination
2.3 SATA
The Apalis module form factor features one SATA interface as standard interface. Depending on
the module, there are maybe additional interfaces type-specific SATA interfaces available.
2.3.1 SATA Signals
Apalis
Pin
Apalis
Signal Name
I/O
Type
Power
Rail
Description
33
SATA1_TX+
O
SATA
SATA transmit data positive
31
SATA1_TX-
O
SATA
SATA transmit data negative
25
SATA1_RX+
I
SATA
SATA receive data positive
27
SATA1_RX-
I
SATA
SATA receive data negative
35
SATA1_ACT#
O
OD
3.3V
Activity indication LED output, active low
Table 5: SATA Signals
The SATA interface does not support polarity inversion. This means the positive and negative signal
pins cannot be swapped for layout simplification.
2.3.2 Reference Schematics
Every SATA interface consists of a pair of transmitting (TX) and receiving (RX) traces. Unfortunately,
the names RX and TX can be confusing, as at the end, the transmitter of the host needs to be
connected to the receiver of the device and vice versa. Normally, the signals are named after the
host until they reach the pins of the SATA device. Therefore, the transmitting pins of the Apalis
modules should be called TX on the carrier board while the receiving input pins of the Apalis
module should be called RX.
2.3.2.1 SATA Connector Schematic Example
The AC coupling capacitors for the RX and TX lines are placed on the Apalis module. Therefore, no
additional serial capacitors are needed nor permitted on the carrier board.

Apalis Carrier Board Design Guide
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Figure 12: SATA connector block diagram
Additionally, to the RX and TX pairs, the SATA interface on the Apalis module features a LED output
signal for signaling activity at the SATA interface (SATA1_ACT#). This information is provided by
the host driver. The signal type is open drain. Therefore, a pull-up resistor is required on the carrier
board. As the signal is used as signal reference for the SATA1_TX+ signal in the MXM3 connector,
a strapping capacitor of 1nF should be placed from SATA1_ACT# to GND close to the MXM3
connector.
Figure 13: SATA connector reference schematic
2.3.2.2 mSATA Card Schematic Example
Mini-SATA is a standard for solid state drive cards that uses the Mini PCIe Card connector and clip.
Please do not confuse mSATA with Mini PCIe Cards solid state drives. These cards feature an on
module flash controller with PCIe interface. The pin-out is electrical compatible, but Mini PCIe Card
uses the PCIe interface while the mSATA uses the SATA interface instead.
Even though the pin-out of the mSATA seems to be similar to the Mini PCIe Card, there is an
important pitfall to remark. Officially, the Mini PCIe Card features the RX+ signal on pin 25 and
RX- on pin 23. The mSATA interface specifies the RX+ signal on pin 23 and RX- signal on 25. The
PCIe interface supports polarity reversal, but not the SATA interface. This means that additional
care needs to be taken to connect the SATA signals correctly to the mSATA card.
Since the AC coupling capacitors for both RX and TX lines are placed on the Apalis Module, no
extra serial capacitors are required on the carrier board.
SATA
Device
SATA
Host
Module
Connector
Apalis Module Carrier Board SATA Drive
TX
RX
RX
TX
SATA1_TX+
SATA1_TX-
SATA1_RX+
SATA1_RX-
SATA1_TX+
SATA1_TX-
SATA1_RX+
SATA1_RX-
A+ (TX+)
A- (TX-)
B+ (RX+)
B- (RX-)
2x 10nF
2x 10nF
SATA
Connector
SATA
Connector
SATA Cable
MM70-314-310B1
Apalis - SATA
19 of 25
SATA1_RX- 27
SATA1_RX+ 25
SATA1_TX- 31
SATA1_TX+ 33
SATA1_ACT# 35
X1S
SATA1_RX_P
SATA1_TX_N
SATA1_TX_P
SATA1_RX_N
MXM3_35_M GND
1A+ (TX+)
2A- (TX-)
3GND
4B- (RX-)
5B+ (RX+)
6GND
7X2
0470804005
SATA1_RX_P
SATA1_TX_N
SATA1_TX_P
SATA1_RX_N
GREEN
LED1
R2
120R
SI-1024-X
2
16
T1A
GND
GND
SI-1024-X
3
5
4
T1B
R4
100K
GND
GND
GND
SATA1[0..3]
R3
470K
3.3V_SW
3.3V_SW
3.3V_SW
1nF
50V
C1
GND
SATA1_ACT
SATA1_ACT#
22R
R1