Toradex Colibri T30 Guide

Colibri Computer Module
Carrier Board Design Guide

Colibri Carrier Board Design Guide
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Issued by:
Toradex
Document Type:
Carrier Board Design Guide
Purpose:
This document is a guideline for developing a carrier board that confirms to the specifications
for the Colibri Computer Module
Document
Version:
1.3
Revision History
Date
Version
Remarks
13 April 2015
V1.0
Initial Release: Preliminary Version
28 Sept 2015
V1.1
Correct figure 3 and figure 4 in section 2.3.2 (positive and negative USB
signals where swapped in schematics)
22 October 2015
V1.2
Corrections in figure 4 in section 2.3.2 (pull up resistor of USB_OC# and
pull down of USBH_EN where swapped)
Correction in typical pull up value for I2C in section 2.9
15 June 2016
V1.3
Add section 2.1.4 “Pin Reset State”
Section 2.16: Update information to input voltage range
Section 2.17: Add note to the usage of PXA270
Section 3.1.3: insert information to nVDD_FAULT, nGPIO_RESET, and
nBATT_SENSE
Section 3.5: Add information to bulk capacitors.

Colibri Carrier Board Design Guide
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1Introduction ....................................................................................................................... 5
1.1 Overview............................................................................................................................. 5
1.2 Additional Documents .......................................................................................................... 5
1.2.1 Layout Design Guide.................................................................................................5
1.2.2 Colibri Module Datasheets.........................................................................................5
1.2.3 Toradex Developer Centre.........................................................................................5
1.2.4 Colibri Evaluation Board Schematics ..........................................................................5
1.2.5 Pinout Designer ........................................................................................................6
1.3 Abbreviations....................................................................................................................... 6
2Interfaces........................................................................................................................... 8
2.1 Architecture......................................................................................................................... 8
2.1.1 Standard Interfaces...................................................................................................8
2.1.2 Interfaces on Alternative Functions.............................................................................8
2.1.3 Pin Numbering ..........................................................................................................9
2.2 Ethernet............................................................................................................................ 10
2.2.1 Ethernet Signals......................................................................................................10
2.2.2 Reference Schematics.............................................................................................10
2.2.3 Unused Ethernet Signals Termination.......................................................................11
2.3 USB.................................................................................................................................. 11
2.3.1 USB Signals ...........................................................................................................11
2.3.2 Reference Schematics.............................................................................................12
2.3.3 Unused USB Signal Termination ..............................................................................13
2.4 Parallel RGB LCD Interface................................................................................................ 13
2.4.1 Parallel RGB LCD Signals .......................................................................................13
2.4.2 Reference Schematics.............................................................................................14
2.4.3 Unused Parallel RGB Interface Signal Termination....................................................16
2.5 HDMI/DVI.......................................................................................................................... 17
2.5.1 HDMI/DVI Signals ...................................................................................................17
2.5.2 Reference Schematics.............................................................................................17
2.5.3 Unused HDMI/DVI Signal Termination......................................................................19
2.6 Analogue VGA................................................................................................................... 20
2.6.1 VGA Signals ...........................................................................................................20
2.6.2 Reference Schematics.............................................................................................20
2.6.3 Unused VGA Interface Signal Termination ................................................................21
2.7 Parallel Camera Interface................................................................................................... 21
2.7.1 Parallel Camera Signals ..........................................................................................21
2.7.2 Unused Parallel Camera Interface Signal Termination ...............................................22
2.8 SD/MMC/SDIO .................................................................................................................. 22
2.8.1 SD/MMC/SDIO Signals............................................................................................22
2.8.2 Reference Schematics.............................................................................................23
2.8.3 Unused SD/MMC/SDIO Interface Signal Termination.................................................23
2.9 I2C.................................................................................................................................... 23
2.9.1 I2C Signals..............................................................................................................23
2.9.2 Real-Team Clock (RTC) recommendation.................................................................23
2.9.3 Unused I2C Signal Termination.................................................................................24
2.10 UART................................................................................................................................ 24
2.10.1 UART Signals......................................................................................................25
2.10.2 Reference Schematics .........................................................................................25
2.10.3 Unused UART Signal Termination.........................................................................27
2.11 SPI ................................................................................................................................... 27
2.11.1 SPI Signals..........................................................................................................28
2.11.2 Unused SPI Signal Termination ............................................................................28
2.12 CAN.................................................................................................................................. 28
2.12.1 Reference Schematics .........................................................................................28
2.13 PWM................................................................................................................................. 28
2.13.1 PWM Signals.......................................................................................................29

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2.13.2 Reference Schematics .........................................................................................29
2.13.3 Unused PWM Signal Termination..........................................................................29
2.14 Analogue Audio ................................................................................................................. 29
2.14.1 Analogue Audio Signals .......................................................................................29
2.14.2 Reference Schematics .........................................................................................30
2.14.3 Unused Analogue Audio Signal Termination ..........................................................31
2.15 Touch Panel Interface ........................................................................................................ 31
2.15.1 Resistive Touch Signals .......................................................................................31
2.15.2 Reference Schematics .........................................................................................32
2.15.3 Unused Touch Panel Interface Signal Termination .................................................32
2.16 Analogue Inputs................................................................................................................. 32
2.16.1 Analogue Input Signals.........................................................................................32
2.16.2 Unused Analogue Inputs Signal Termination..........................................................32
2.17 Parallel Memory Bus (External Memory Bus)....................................................................... 33
2.17.1 Memory Bus Signals ............................................................................................33
2.17.2 Unused Memory Bus Signals Termination .............................................................34
2.18 GPIO ................................................................................................................................ 35
2.18.1 Preferred GPIO Signals........................................................................................35
2.18.2 Unused GPIO Termination....................................................................................35
3Power Management........................................................................................................... 36
3.1 Power Signals ................................................................................................................... 36
3.1.1 Digital Supply Signals..............................................................................................36
3.1.2 Analogue Supply Signals .........................................................................................36
3.1.3 Power Management Signals ....................................................................................36
3.2 Power Block Diagram......................................................................................................... 37
3.3 Power States..................................................................................................................... 39
3.4 Power-Up Sequence.......................................................................................................... 39
3.5 Reference Schematics ....................................................................................................... 40
4Mechanical and Thermal Consideration............................................................................... 42
4.1 Module Connector.............................................................................................................. 42
4.2 Fixation of the Module........................................................................................................ 42
4.3 Thermal Solution................................................................................................................ 44
4.4 Module Size ...................................................................................................................... 44
5Appendix A –Physical Pin Definition and Location............................................................... 45

Colibri Carrier Board Design Guide
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1 Introduction
1.1 Overview
This document guides the development of a customized carrier board for the Colibri computer
module. It describes the different interfaces and contains reference schematics. This document
reflects only the standardized primary function of the Colibri modules. The alternative functions are
not guaranteed to be compatible between different Colibri modules. These interfaces are described
in the datasheet of each computer module. Some Colibri modules do not feature the full set of
standard interfaces. Therefore, it is strongly recommended to read the datasheets of the modules
that are intended to be used with the carrier board.
Some of the Colibri computer module interfaces such as High-Speed USB, Ethernet, etc. require
special layout considerations regarding trace impedance and length matching. Please carefully
read the Toradex Layout Design Guide for additional information related to the routing of these
interfaces.
1.2 Additional Documents
1.2.1 Layout Design Guide
This document contains layout requirement specifications for the high-speed signals and helps in
avoiding problems related to the layout.
http://developer.toradex.com/hardware-resources/arm-family/carrier-board-design
1.2.2 Colibri Module Datasheets
There is a datasheet available for every Colibri module. Amongst other things, this document
describes the type-specific interfaces and the alternative function of the pins. Before starting the
development of a customized carrier board, please check this document to find out whether the
required interfaces are really available on the selected modules.
https://www.toradex.com/products/apalis-arm-computer-modules
1.2.3 Toradex Developer Centre
You can find a lot of additional information at the Toradex Developer Centre, which is updated
with the latest product support information on a regular basis.
Please note that the Developer Centre is common for all Toradex products. You should always
check to ensure if the information is valid or relevant for the specific Colibri modules.
http://www.developer.toradex.com
1.2.4 Colibri Evaluation Board Schematics
We provide the complete schematics plus the Altium project file for the Colibri Evaluation Board for
free. This is a great help when designing your own Carrier Board.
http://developer.toradex.com/hardware-resources/arm-family/carrier-board-design

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1.2.5 Pinout Designer
This is an interactive and useful tool for configuring the pin muxing of the Colibri and Apalis
modules. It can be really helpful in custom carrier board development on Toradex modules and for
checking the compatibility of existing carrier boards with our modules.
http://developer.toradex.com/knowledge-base/pinout-designer
1.3 Abbreviations
Abbreviation
Explanation
ADC
Analogue to Digital Converter
AGND
Analogue Ground - separate ground for analogue signals
Auto-MDIX
Automatically Medium Dependent Interface Crossing - a PHY with Auto-MDIX f is able to detect whether
RX and TX need to be crossed (MDI or MDIX)
CAD
Computer-Aided Design - in this document is referred to PCB Layout tools
CAN
Controller Area Network - a bus that is manly used in automotive and industrial environment
CDMA
Code Division Multiplex Access - abbreviation often used for a mobile phone standard for data
communication
CEC
Consumer Electronic Control - HDMI feature that allows to control CEC compatible devices
CPU
Central Processor Unit
CSI
Camera Serial Interface
DAC
Digital to Analogue Converter
DDC
Display Data Channel - interface for reading out the capability of a monitor, in this document DDC2B
(based on I2C) is always meant
DRC
Design Rule Check - a tool for checking whether all design rules are satisfied in a CAD tool
DSI
Display Serial Interface
DVI
Digital Visual Interface - digital signals are electrical compatible with HDMI
DVI-A
Digital Visual Interface Analogue only - signals are compatible with VGA
DVI-D
Digital Visual Interface Digital only - signals are electrical compatible with HDMI
DVI-I
Digital Visual Interface Integrated - combines digital and analogue video signals in one connector
EDA
Electronic Design Automation - software for schematic capture and PCB layout (CAD or ECAD)
EDID
Extended Display Identification Data - timing setting information provided by the display in a PROM
EMI
Electromagnetic Interference - high frequency disturbances
eMMC
Embedded Multi Media Card - flash memory combined with MMC interface controller in a BGA package,
used as internal flash memory
ESD
Electrostatic Discharge - high voltage spike or spark that can damage electrostatic- sensitive devices
FPD-Link
Flat Panel Display Link - high-speed serial interface for liquid crystal displays. In this document also called
LVDS interface.
GBE
Gigabit Ethernet - Ethernet interface with a maximum data rate of 1000Mbit/s
GND
Ground
GPIO
General Purpose Input/Output pin that can be configured to be either an input or output
GSM
Global System for Mobile Communications
HDA
High Definition Audio (HD Audio) - digital audio interface between CPU and audio codec
HDCP
High-Bandwidth Digital Content Protection - copy protection system that is used by HDMI beside others
HDMI
High-Definition Multimedia Interface - combines audio and video signal for connecting monitors, TV sets
or Projectors, electrical compatible with DVI-D
I2C
Inter-Integrated Circuit - two wire interface for connecting low speed peripherals
I2S
Integrated Interchip Sound - serial bus for connecting PCM audio data between two devices
IrDA
Infrared Data Association - infrared interface for connecting peripherals
JTAG
Joint Test Action Group - widely used debug interface
LCD
Liquid Crystal Display
LSB
Least Significant Bit
LVDS
Low-Voltage Differential Signaling - electrical interface standard that can transport very high-speed
signals over twisted-pair cables. Many standard interfaces like PCIe or SATA use this interface standard.

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Abbreviation
Explanation
Since the first successful application was the Flat Panel Display Link, LVDS has become synonymous for
this interface. In this document, the term LVDS is used for the FPD-Link interface.
MIPI
Mobile Industry Processor Interface Alliance
MDI
Medium Dependent Interface - physical interface between Ethernet PHY and cable connector
MDIX
Medium Dependent Interface Crossed - an MDI interface with crossed RX and TX interfaces
mini PCIe
PCI Express Mini Card - card form factor for internal peripherals. The interface features PCIe and USB
2.0 connectivity
MMC
MultiMediaCard - flash memory card
MSB
Most Significant Bit
mSATA
Mini-SATA - a standardized form factor for small solid state drive, similar dimensions as mini PCIe
N/A
Not Available
N/C
Not Connected
OD
Open Drain
OTG
USB On-The-Go - a USB host interface that can also act as USB client when connected to another host
interface
OWR
One Wire (1-Wire) - low speed interface which needs just one data wire plus ground
PCB
Printed Circuit Board
PCI
Peripheral Component Interconnect - parallel computer expansion bus for connecting peripherals
PCIe
PCI Express - high-speed serial computer expansion bus, replaces the PCI bus
PCM
Pulse-Code Modulation - digital representation of analogue signals and a standard interface for digital
audio
PD
Pull Down Resistor
PHY
Physical Layer of the OSI model
PMIC
Power Management IC - integrated circuit that manages amongst others the power sequence of a system
PU
Pull-up Resistor
PWM
Pulse-Width Modulation
RGB
Red Green Blue - color channels in common display interfaces
RJ45
Registered Jack - common name for the 8P8C modular connector that is used for Ethernet wiring
RS232
Single ended serial port interface
RS422
Differential signaling serial port interface - full duplex
RS485
Differential signaling serial port interface - half duplex, multi drop configuration possible
R-UIM
Removable User Identity Module - identifications card for CDMA phones and networks, an extension of
the GSM SIM card
S/PDIF
Sony/Philips Digital Interconnect Format - optical or coaxial interface for audio signals
SATA
Serial ATA, high-speed differential signaling interface for hard drives and SSD
SD
Secure Digital - flash memory card
SDIO
Secure Digital Input Output - an external bus for peripherals that uses the SD interface
SIM
Subscriber Identification Module - identification card for GSM phones
SMBus
System Management Bus (SMB) - two wire bus based on the I2C specifications, used specially in x86
design for system management.
SoC
System on a Chip - IC which integrates the main component of a computer on a single chip
SO-DIMM
Small Outline Dual Inline Memory Module - form factor for mobile RAM modules, the Colibri module uses
the SO-DIMM (DDR, 2.5V variant) connector as main interface
SPI
Serial Peripheral Interface Bus - synchronous four wire full duplex bus for peripherals
TIM
Thermal Interface Material - thermal conductive material between CPU and heat spreader or heat sink
TMDS
Transition-Minimized Differential Signaling - serial high-speed transmitting technology that is used by DVI
and HDMI
TVS Diode
Transient-Voltage-Suppression Diode - diode that is used to protect interfaces against voltage spikes
UART
Universal Asynchronous Receiver/Transmitter - serial interface, in combination with a transceiver a
RS232, RS422, RS485, IrDA or similar interface can be achieved
USB
Universal Serial Bus - serial interface for internal and external peripherals
VCC
Positive supply voltage
VGA
Video Graphics Array - analogue video interface for monitors
Table 1: Abbreviations

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2 Interfaces
2.1 Architecture
2.1.1 Standard Interfaces
The standard interfaces on the Colibri module family intent to provide electrical and functional
compatibility between module family members. The table below shows an overview of the
standard interfaces that are provided by a Colibri module. The “GPIO Capable” column indicates
whether the assigned pins are intent to be also used as GPIOs. “Yes”and “No”are self-
Explanatory. “Optional”indicates that it may be possible for some modules, but not all.
The “Standard” column indicates the number of interfaces that the specification allows for in the
standard pin-out. Customers should consult the datasheet for specific Colibri module variants to
check which of the interfaces are available for that module.
Description
Standard
Note
GPIO
Capable
4/5 Wire Resistive Touch
1
Touch wiper shared with analogue input 4
No
Analogue Inputs
4
Minimum 8 bit resolution, 0-3.3V nominal range
No
Analogue Audio
1
Line in L&R, Microphone in, Headphone out L&R
No
Fast Ethernet
1
No
HDMI (TDMS)
1
Located on dedicated FFC connector
(availability depending on Module)
No
I2C
1
Additional dedicated DDC available on FFC connector
Yes
Parallel Camera
1
8 bit BT.656 (other modes may available)
Yes
Parallel LCD
1
18 bit resolution (additional bits may available)
Yes
Parallel Memory Bus
1
Supported bus width depends on Module
Optional
PWM
4
Yes
SDIO
1
4 bit
Yes
SPI
1
Yes
UART
3
1x Full Featured, 1x CTS/RTS, 1x RXD/TXD only
Yes
USB
2
1x shared host/client, 1x host only
No
VGA
1
Located on dedicated FFC connector
(availability depending on Module)
No
Table 2: Standard Interfaces
2.1.2 Interfaces on Alternative Functions
Many SoC pins can be used for more than one function. This allows the modules provide many
additional interfaces to the standard set. For example, in the Colibri standard there is only one SPI
interface listed. Nevertheless, some modules can provide up to 6 SPI interfaces.
Please note that there are a few restrictions of using the interfaces that are provided as alternative
functions of the pins. There is limited compatibility between their availability at different modules.
For a design to be compatible with a wide range of Colibri modules, it is recommended to mainly
use the standard interfaces. The various pins can be used for only one function each
simultaneously.
The configuration of the alternative function interfaces can be quite complex. Toradex provides a
powerful tool which helps the development engineer to resolve pin muxing conflicts. The tool is
called Pinout Designer. It reduces the complexity of this important task. More information including
its download link can be found here: http://developer.toradex.com/knowledge-base/pinout-
designer.

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The interfaces on the alternative functions are not described in this document since they differ
between the modules. Information related to these functions can be found in the datasheets of the
modules.
2.1.3 Pin Numbering
The diagrams in the figures below show the pin numbering schema on both sides of the module.
The schema is equals to the JEDEC MO-224 DDR SO-DIMM standard. The odd pin numbers are
located on the top side of the module.
Figure 1: Colibri Module Pin Numbering Schema
2.1.4 Pin Reset State
The datasheets of the Colibri module provide information about the default reset status of the IO
pins. Please be aware, the pin reset status is only guaranteed during the release of the reset
signal. Some of the modules switches the IO bank voltages in order to follow the power up
sequence of the SoC. This means, the IO pins can have an undefined state between applying the
main power to the module until the nRESET_OUT is released. For carrier board designs that do not
allow undefined pin states, it is recommended to make sure that the peripheral devices are not
getting powered before the nRESET_OUT is released. Another solution can be gating the according
IO signals with the nRESET_OUT signal.
Pin1 Pin47Pin39 Pin199
Pin2 Pin42Pin40 Pin200

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2.2 Ethernet
The Colibri module standard features a fast 10/100Mbit Ethernet (10/100Base-TX) interface port.
The required center tap circuit can differ between the modules. Different assembly options might
be needed for supporting the complete Colibri module family. Some modules support Auto MDIX,
which means they can swap the transmitting with the receiving lanes. Read the corresponding
datasheet of the module for more information about the availability of the Auto MDIX function.
2.2.1 Ethernet Signals
Colibri
Pin
Colibri
Signal Name
I/O
Type
Power
Rail
Description
189
ETH_1_TXO+
I
Analogue
100BASE-TX: Transmit + (Auto MDIX: Receive +)
187
ETH_1_TXO-
I
Analogue
100BASE-TX: Transmit - (Auto MDIX: Receive -)
195
ETH_1_RXI+
O
Analogue
100BASE-TX: Receive + (Auto MDIX: Transmit +)
193
ETH_1_RXI-
O
Analogue
100BASE-TX: Receive - (Auto MDIX: Transmit -)
191
AGND_LAN
Ethernet ground, on some modules connected to common GND
183
ETH_1_LINK_AKT
O
CMOS
3.3V
LED indication output for link activity on the Ethernet port
185
ETH_1_SPEED100
O
CMOS
3.3V
LED indication output for 100Mbit/s
Table 3: Ethernet Signals
2.2.2 Reference Schematics
Ethernet connectors with integrated magnetics are preferable. If a design with external magnetics
is chosen, additional care has to be taken to route the signals between the magnetics and Ethernet
connector.
The LED output signals ETH_1_LINK_AKT and ETH_1_SPEED100 can be connected directly to the
LED of the Ethernet jack with suitable serial resistors. There is no need for additional buffering if
the current drawn does not exceeds 10mA.
The Fast Ethernet interface uses the ETH_1_TXO as transmitting lanes and the ETH_1_RXI as
receiving lane. If the Ethernet PHY features Auto-MDIX, the signal lanes RX and TX could be
swapped. We strongly recommend not swapping the RX and TX lanes in order to keep the
compatibility with all Colibri modules.
The required center tap circuit depends on the supported modules. Currently, the Ethernet
controller on the PXA270 module is the only one which requires a different center tap circuit since
it does not support Auto-MDIX. All the other currently available modules feature a current control
PHY which requires 3.3V supply at the center tap of the RX and TX lanes. Since all the Ethernet PHY
manufacturer are tending to change from current mode to voltage mode which requires leaving
the center tab pins of the magnetics unconnected, we recommend to add additional 0R resistors
into the center tab lines. This ensures that the carrier board design is ready for any future Colibri
module with voltage mode PHY.

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Figure 2: Fast Ethernet with Integrated Magnetics Reference Schematic
2.2.3 Unused Ethernet Signals Termination
All unused Ethernet signals can be left unconnected.
2.3 USB
The Colibri modules feature two USB interfaces. One of the two USB interfaces can be configured
to be used as either the host or client. The other interface can only be used as host. Some of the
Colibri modules use the USB client port for debugging and recovery purpose. Therefore, it is
recommended to have the interface accessible even for carrier board designs which do not need
any USB ports.
2.3.1 USB Signals
Colibri
Pin
Colibri
Signal Name
I/O
Type
Power
Rail
Description
139
USB_H_DP
I/O
USB
3.3V
Positive Differential Signal for USB Host port
141
USB_H_DM
I/O
USB
3.3V
Negative Differential Signal for USB Host port
143
USB_C_DP
I/O
USB
3.3V
Positive Differential Signal for the shared USB Host / Client port
145
USB_C_DM
I/O
USB
3.3V
Negative Differential Signal for the shared USB Host / Client port
Table 4: USB Data Signals
If you use the USB Host function you need to generate the 5V USB supply voltage on your carrier
board. The Colibri modules provide two optional signals for USB power supply control (PWR_EN
and OC). We recommend using the following pins to ensure the best possible compatibility.
However, use of these signals is not mandatory and other GPIOs may be used instead.
In the USB client mode, an additional signal is required that detects whether the client is connected
to a host interface (VBUS_DETECT). Please note that this pin is only 3.3V tolerant. Therefore, an
additional logic level shifter (simplest solution is a voltage divider) is required.
Colibri
Pin
Colibri
Signal Name
I/O
Type
Power
Rail
Description
129
USB_H_PWR_EN
O
CMOS
3.3V
This pin enables the external USB voltage supply
131
USB_H_OC
I
CMOS
3.3V
USB overcurrent, this pin can signal an over current condition in
the USB supply
137
USB_C_VBUS_DETECT
I
CMOS
3.3V
Use this pin to detect if VBUS is present (5V USB supply). Please
note that this pin is only 3.3V tolerant
Table 5: USB Control Signals
ETH_LINK_ACT
ETH_SPEED
ETH_TX0_N
ETH_TX0_P
ETHERNET[0..5]
50R
R20
50R
R21
100nF
16VC45
GND
50R
R22
50R
R23
100nF
16VC46
GND
ETH_RXI_P
ETH_RXI_N
100nF
16V
C44
GND
ETH_AVCC
3.3V
3.3V
2A
220R@100MHz
L10
47uF
6.3V
+
C48
47uF
6.3V
+
C49
3.3V ETH_AVCC
GND
150RR25
150RR24
J00-0065NL
TD+
1
TD-
2
CT_TXD
4
CT_RXD
5
RD+
3
RD-
6
LED_Left_A
9
LED_Left_C
10
LED_Right_C
11 LED_Right_A
12 SHIELD S1
SHIELD S2
NC 7
CHS GND 8
X17
ETH_LINK_ACT
ETH_SPEED
ETH_TX0_N
ETH_TX0_P
ETH_RXI_N
ETH_RXI_P
1473005-1
ETH_LINK_ACT 183
ETH_SPEED 185
ETH_TX0- 187
ETH_TX0+ 189
ETH_RXI- 193
ETH_RXI+ 195
ETH_GND 191
Colibri -Ethernet
2 of 16
X1B
SHIELD
Ethernet Connector
ETH_CT_TX
ETH_CT_RX
GND
GND
0R
R10
100nF
16V
C47
GND
0R
R11
0R
R12
NA
PXA2700RNA0R
ModuleR13R12R11
AllexceptPXA2700RNA 0R
Reserved for future modulesNA NANA (Integrated Magnetics)

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2.3.2 Reference Schematics
2.3.2.1 USB 2.0 Client Schematic Example
The differential USB data signals require a common mode choke to be placed. Make sure that the
selected choke is certified for USB 2.0 High Speed. The same is also required for the TVS diodes.
The VBUS_DETECT signal is only 3.3V tolerant on the Colibri module. The simplest solution is to
use a voltage divider.
Figure 3: USB 2.0 Client Reference Schematic
2.3.2.2 USB 2.0 Host Connector Schematic Example
The carrier board needs to provide 5V USB bus power on the USB host jacks. According to the USB
2.0 specifications, the maximum current drawn per port is limited by 500mA. The bus power needs
to be in the range of 4.75V to 5.25V measured at the USB host jack for any load current from 0mA
to 500mA. In order to ensure that an out of spec device or a defective device is not damaging the
5V power rail on the carrier board, it is recommended adding a current limiting IC. This device
detects overcurrent situation and switches off the corresponding USB bus power. The overcurrent
signal (USB_H_OC) is used to notify the host controller about the occurrence of an overcurrent shut
down event.
The inrush current needs to be taken into account while designing the USB bus power. USB devices
are allowed to have a maximum input capacitor at the bus power of 10µF. The maximum inrush
charge is limited to 50µC. This means that the power rail at the USB host jack needs to be tolerant
of this inrush current. A good approach is to place a large capacitor (e.g. 100µF) at the rail.
Figure 4: USB 2.0 Host Reference Schematic
GND
2A
220R@100MHz
L1
90R@100MHz
1
2 3
4
L2
USBO1_D_N
USBO1_D_P USBO1_D_CON_N
USBO1_D_CON_P
330R
R3
GND
GREEN
LED1
SHIELD
VCC_USBO1
VCC_USBO1
GND_USBO1
Optional
USBO1_VBUS
RCLAMP0504S
1
2
3 4
5
6
D1
4A
39R@100MHz
L3
100nF
C1
SHIELD
5V_ESD
SHIELD
5V
VCC
1
D-
2
D+
3
GND
4S1
S2
61729-0010BLF
X2
1473005-1
USBH_P 139
USBH_N 141
USBC_P 143
USBC_N 145
PIN_131/USB_OC 131
PIN_137/USBC_CABLEDET 137
PIN_129/USB_P_EN 129
Colibri - USB
3 of 16
X1C
R69
15K
R68
15K
GND
560R
R73
R74
1K
GND
GND
2A
220R@100MHz
L3 1nF
50V
C3
GND_USBH
100nF
16V
C1
GND
100uF
10V
+
C2
GND
TPS2052BD
V_IN
2
EN_1
3OUT_1 7
OC_1#
8
IC1A
GND
2A
220R@100MHz
L2
90R@100MHz
1
2 3
4
L1
USBH2_D_N
USBH2_D_P USBH2_D_CON_N USBH2_D_CON_P
330R
R1
GND
GREEN
LED1
TPD2EUSB30DRTR
12 D+D-
D2
GND
SHIELD
VCC_USBH VCC_USBH
USBH_OC#
USBH_EN
GND_USBH
Optional
USBH_OC#
USBH_EN TPS2052BD
GND
1
EN_2
4
OC_2#
5OUT_2 6
IC1B
GND
5V
VCC
1
D-
2
D+
3
GND
4
292303-1
S1
S2
S3
S4
X2
R2
100K
3.3V
R3
100K
GND
1473005-1
USBH_P 139
USBH_N 141
USBC_P 143
USBC_N 145
PIN_131/USB_OC 131
PIN_137/USBC_CABLEDET 137
PIN_129/USB_P_EN 129
Colibri -USB
3 of 16
X1C
R69
15K
R68
15K
GND

Colibri Carrier Board Design Guide
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
Page | 13
2.3.3 Unused USB Signal Termination
Colibri
Pin
Colibri
Signal Name
Recommended Termination
139
USB_H_DP
Leave NC if not used
141
USB_H_DM
Leave NC if not used
143
USB_C_DP
Leave NC if not used
145
USB_C_DM
Leave NC if not used
129
USB_H_PWR_EN
Leave NC if not used
131
USB_H_OC
Add pull-up resistor or disable the overcurrent function in software
137
USB_C_VBUS_DETECT
Leave NC if not used
Table 6: Unused USB Signals Termination
2.4 Parallel RGB LCD Interface
The Colibri modules feature one parallel RGB LCD interface as main display interface. As standard,
the Colibri modules feature the interface with 18-bit color depth. Some modules support color
depth of 16-bit or 24-bit. Unfortunately, the color mapping of these modes can be different
between the modules. Therefore, Toradex recommends using the interface in the 18-bit color
mode for the best compatibility between all Colibri modules. Dithering can help reducing the
visible color banding of gradients in lower color depth systems. Consider using 18-bit color
mapping with enabled dithering instead of 24-bit mapping. Carefully check which modules support
color dithering.
2.4.1 Parallel RGB LCD Signals
Colibri
Pin
Colibri
Signal Name
I/O
Type
Power
Rail
Description
52
LCD_1_18bit_R0
O
CMOS
3.3V
Red LCD data signals (LSB: 0, MSB: 5)
54
LCD_1_18bit_R1
O
CMOS
3.3V
66
LCD_1_18bit_R2
O
CMOS
3.3V
64
LCD_1_18bit_R3
O
CMOS
3.3V
57
LCD_1_18bit_R4
O
CMOS
3.3V
61
LCD_1_18bit_R5
O
CMOS
3.3V
80
LCD_1_18bit_G0
O
CMOS
3.3V
Green LCD data signals (LSB: 0, MSB: 5)
46
LCD_1_18bit_G1
O
CMOS
3.3V
62
LCD_1_18bit_G2
O
CMOS
3.3V
48
LCD_1_18bit_G3
O
CMOS
3.3V
74
LCD_1_18bit_G4
O
CMOS
3.3V
50
LCD_1_18bit_G5
O
CMOS
3.3V
76
LCD_1_18bit_B0
O
CMOS
3.3V
Blue LCD data signals (LSB: 0, MSB: 5)
70
LCD_1_18bit_B1
O
CMOS
3.3V
60
LCD_1_18bit_B2
O
CMOS
3.3V
58
LCD_1_18bit_B3
O
CMOS
3.3V
78
LCD_1_18bit_B4
O
CMOS
3.3V
72
LCD_1_18bit_B5
O
CMOS
3.3V
44
LCD_1_18bit_DE
O
CMOS
3.3V
Data Enable (other names: Output Enable)
56
LCD_1_18bit_PCLK
O
CMOS
3.3V
Pixel Clock (other names: Dot Clock, L_PCLK_WR)
68
LCD_1_18bit_HSYNC
O
CMOS
3.3V
Horizontal Sync (other names: Line Clock, L_LCKL_A0)
82
LCD_1_18bit_VSYNC
O
CMOS
3.3V
Vertical Sync (other names: Frame Clock, L_FCLK)
Table 7: Parallel RGB LCD Signals

Colibri Carrier Board Design Guide
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
Page | 14
2.4.2 Reference Schematics
2.4.2.1 18-bit Display Schematic Example
The parallel RGB interface can cause problems in passing the electromagnetic radiation tests when
used with high pixel clocks frequency. Especially if a display is connected over long flat flex cables.
The reduction of the radiation needs to be taken in account. Keep the flat flex cables as short as
possible. Series resistors in the data lines reduce the slew rate of the signals which reduces the
radiation problem but can introduce signal quality and timing problems. The serial resistor value is
a trade-off between electromagnetic radiation reduction and signal quality. A good starting value
is 22Ω.
Figure 5: 18bit Parallel RGB Display Reference Schematic
2.4.2.2 VGA DAC Schematic Example
A few Colibri modules feature a dedicated VGA interface on an FFC connector. Nevertheless, it is
recommended adding a parallel RGB to VGA converter if a VGA interface is needed which is
compatible with all modules. Since only the 18-bit color depth is compatible between the different
modules, it is recommended to use this mode even if the DAC is capable of 24-bit.
LCD_BIAS
3.3V
GND
PWM_A
LCD_D_6
LCD_D_4
LCD_D_0
LCD_D_10
LCD_D_1
LCD_D_14
LCD_D_15
LCD_D_8
LCD_D_2
LCD_D_3
LCD_D_13
LCD_D_12
LCD_D_11
LCD_D_9
LCD_D_7
LCD_D_16
LCD_D_17
LCD_LCLK_A0
LCD_FCLK_RD
LCD_PCLK_WR
LCD_D_5
TOUCH_TSPX
TOUCH_TSMX
TOUCH_TSPY
TOUCH_TSMY
3.3V
RESET_OUT#
TOUCH[0..3]
BL_ON
0RR110
0R
R100
0R
R89
GND
GND
GND
GND
GND
0R
R101
0R
R90
3.3V 3.3V
GND
GND
Share pads
LCD[0..28]
FH12-40S-0.5SV(55)
9
13
8
1
2
3
5
6
7
10
11
12
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
4
X34
Unified Interface DisplayConnector
1473005-1
PIN_14/TOUCH_TSPX 14
PIN_16/TOUCH_TSMX 16
PIN_18/TOUCH_TSPY 18
PIN_20/TOUCH_TSMY 20
Colibri -Touch
9 of 16
X1I
1473005-1
PIN_71/BL_ON 71
PIN_57/LDD_D_16 57
PIN_61/LDD_D_17 61
PIN_44/LDD_BIAS 44
PIN_46/LDD_D_7 46
PIN_48/LDD_D_9 48
PIN_50/LDD_D_11 50
PIN_52/LDD_D_12 52
PIN_54/LDD_D_13 54
PIN_56/LDD_PCLK_WR 56
PIN_58/LDD_D_3 58
PIN_60/LDD_D_2 60
PIN_62/LDD_D_8 62
PIN_64/LDD_D_15 64
PIN_66/LDD_D_14 66
PIN_68/LDD_LCLK_A0 68
PIN_70/LDD_D_1 70
PIN_72/LDD_D_5 72
PIN_74/LDD_D_10 74
PIN_76/LDD_D_0 76
PIN_78/LDD_D_4 78
PIN_80/LDD_D_6 80
PIN_82/LDD_FCLK_RD 82
Colibri -LDD
12 of 16
PIN_136/LDD_D_18/ADDR24 136
PIN_138/LDD_D_19/ADDR23 138
PIN_140/LDD_D_20/ADDR22 140
PIN_142/LDD_D_21/ADDR21 142
PIN_144/LDD_D_22/ADDR20 144
PIN_146/LDD_D_23/ADDR19 146
X1L SODIMM_44_S
SODIMM_46_S
SODIMM_48_S
SODIMM_50_S
SODIMM_52_S
SODIMM_54_S
SODIMM_56_S
SODIMM_58_S
SODIMM_60_S
SODIMM_62_S
SODIMM_64_S
SODIMM_66_S
SODIMM_68_S
SODIMM_70_S
SODIMM_72_S
SODIMM_74_S
SODIMM_76_S
SODIMM_78_S
SODIMM_80_S
SODIMM_82_S
SODIMM_57_S
SODIMM_61_S
SODIMM_71_S
22RRA5A 22RRA5B 22RRA5C 22RRA5D 22RRA6A 22RRA6B 22RRA6C 22RRA6D 22RRA7A 22RRA7B 22RRA7C 22RRA7D 22RRA8A 22RRA8B 22RRA8C 22RRA8D 22RRA9A 22RRA9B
22RRA4C 22RRA4D
22RRA30D 22RRA29C 22RRA1A
1473005-1
PIN_59/PWM_A 59
PIN_67 67
PIN_28/PWM_B 28
PIN_30/PWM_C 30
Colibri -PWM
5 of 16
X1E SODIMM_59_S 22RRA29D
1473005-1
VDD_FAULT# 22
BATT_FAULT# 24
RESET_EXT# 26
RESET_OUT# 87
Colibri -Reset
4 of 16
X1D
BL_ON
LCD_BIAS
LCD_D_4
LCD_D_0
LCD_D_1
LCD_D_2
LCD_D_3
LCD_D_5
LCD_D_6
LCD_D_10
LCD_D_8
LCD_D_11
LCD_D_9
LCD_D_7
LCD_D_14
LCD_D_15
LCD_D_13
LCD_D_12
LCD_D_16
LCD_D_17
LCD_PCLK_WR
LCD_LCLK_A0
LCD_FCLK_RD
TOUCH_TSPX
TOUCH_TSMX
TOUCH_TSPY
TOUCH_TSMY

Colibri Carrier Board Design Guide
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
Page | 15
Figure 6: VGA DAC Reference Schematic
2.4.2.3 LVDS Transmitter Schematic Example
Since the electromagnetic radiation of the parallel RGB interface is not easy to handle, it is
recommended to attach liquid crystal displays with high resolutions by using an LVDS interface.
LVDS also reduces problems associated with long cables. The Colibri standard does not feature a
dedicated LVDS LCD interface. Nevertheless, a parallel RGB to LVDS transmitter can be placed on
the carrier board in order to get an LVDS interface.
Since there are different LVDS color mapping available, check with your display vendor how the
RGB signals need to be connected to the transmitter in order to be compatible.
Figure 7: LVDS Transmitter Reference Schematic
3.3V VGA_AVCC
0RR16
0RR15
5V
Power Options
22uF
10V
+
C25
EXT_VSYNC
EXT_HSYNC
EXT_BLUE
EXT_GREEN
EXT_RED
GND
SHIELD2
LCD_BIAS
LCD_D_6
LCD_D_4
LCD_D_0
LCD_D_10
LCD_D_1
LCD_D_8
LCD_D_2
LCD_D_3
LCD_D_11
LCD_D_9
LCD_D_7
LCD_PCLK_WR
LCD_D_5
LCD_D_14
LCD_D_15
LCD_D_13
LCD_D_12
LCD_D_16
LCD_D_17
GND
100nF
16V
C17
VGA_AVCC
560R
R11
100nF
16V
C16
10nF
25V
C26
One pair 1 0n/100n for eac h VAAgr oup on pin 13, 29, 30 ofthe DAC
100nF
16V
C27 10nF
25V
C28 100nF
16V
C29 10nF
25V
C30 100nF
16V
C31
VGA_AVCC
VGA_BLUE
VGA_GREEN
VGA_RED
GND
GND
GND
GND
GND
ADV7125KSTZ140
GND
1
GND
2
GND
14
GND
15
GND
25
GND
26
GND
39
GND
40
G0
3G1
4G2
5G3
6G4
7G5
8G6
9G7
10
B0
16 B1
17 B2
18 B3
19 B4
20 B5
21 B6
22 B7
23
R0
41 R1
42 R2
43 R3
44 R4
45 R5
46 R6
47 R7
48
BLANK#
11 SYNC#
12
VAA 13
VAA 29
VAA 30
CLOCK
24
IOR- 33
IOR+ 34
IOG- 31
IOG+ 32
IOB- 27
IOB+ 28
COMP 35
RSET 37
PSAVE#
38
VREF 36
IC3
GND
BL_ON
3.3V
0RR12
R14 100K
LCD_LCLK_A0
LCD_FCLK_RD
PLACE D15, D16 NEAR THE VGA CONNECTOR
1
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
HDR15SN-H
10
11
12
13
14
15
10
11
12
13
14
15
X24A
47pF
50V
C180
GND
500mA
220R@100MHz
L48
SN74LVC1G17
NC 1
A
2
GND
3
Y4
VCC
5
IC25
5V
33R
R175
100nF
16V
C181
GND
47pF
50V
C182
GND
500mA
220R@100MHz
L49
SN74LVC1G17
NC 1
A
2
GND
3
Y4
VCC
5
IC26
5V
33R
R176
100nF
16V
C183
RCLAMP0504S
1 2
34
5 6
D15
SHIELD2
RCLAMP0504S
1 2
3
4 5
6
D16
10pF
50V
C188 10pF
50V
C189
GND
600mA
40R@100MHzL52
10pF
50V
C186 10pF
50V
C187
GND
600mA
40R@100MHzL51
10pF
50V
C184 10pF
50V
C185
GND
600mA
40R@100MHzL50
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
0RR185
GND
75R
R6
75R
R7
75R
R8
VGA Connector
1473005-1
PIN_71/BL_ON 71
PIN_57/LDD_D_16 57
PIN_61/LDD_D_17 61
PIN_44/LDD_BIAS 44
PIN_46/LDD_D_7 46
PIN_48/LDD_D_9 48
PIN_50/LDD_D_11 50
PIN_52/LDD_D_12 52
PIN_54/LDD_D_13 54
PIN_56/LDD_PCLK_WR 56
PIN_58/LDD_D_3 58
PIN_60/LDD_D_2 60
PIN_62/LDD_D_8 62
PIN_64/LDD_D_15 64
PIN_66/LDD_D_14 66
PIN_68/LDD_LCLK_A0 68
PIN_70/LDD_D_1 70
PIN_72/LDD_D_5 72
PIN_74/LDD_D_10 74
PIN_76/LDD_D_0 76
PIN_78/LDD_D_4 78
PIN_80/LDD_D_6 80
PIN_82/LDD_FCLK_RD 82
Colibri - LDD
12 of 16
PIN_136/LDD_D_18/ADDR24 136
PIN_138/LDD_D_19/ADDR23 138
PIN_140/LDD_D_20/ADDR22 140
PIN_142/LDD_D_21/ADDR21 142
PIN_144/LDD_D_22/ADDR20 144
PIN_146/LDD_D_23/ADDR19 146
X1L SODIMM_44_S
SODIMM_46_S
SODIMM_48_S
SODIMM_50_S
SODIMM_52_S
SODIMM_54_S
SODIMM_56_S
SODIMM_58_S
SODIMM_60_S
SODIMM_62_S
SODIMM_64_S
SODIMM_66_S
SODIMM_68_S
SODIMM_70_S
SODIMM_72_S
SODIMM_74_S
SODIMM_76_S
SODIMM_78_S
SODIMM_80_S
SODIMM_82_S
SODIMM_57_S
SODIMM_61_S
SODIMM_71_S
22RRA5A 22RRA5B 22RRA5C 22RRA5D 22RRA6A 22RRA6B 22RRA6C 22RRA6D 22RRA7A 22RRA7B 22RRA7C 22RRA7D 22RRA8A 22RRA8B 22RRA8C 22RRA8D 22RRA9A 22RRA9B
22RRA4C 22RRA4D
22RRA30D 22RRA29C 22RRA1A
BL_ON
LCD_BIAS
LCD_D_4
LCD_D_0
LCD_D_1
LCD_D_2
LCD_D_3
LCD_D_5
LCD_D_6
LCD_D_10
LCD_D_8
LCD_D_11
LCD_D_9
LCD_D_7
LCD_D_14
LCD_D_15
LCD_D_13
LCD_D_12
LCD_D_16
LCD_D_17
LCD_PCLK_WR
LCD_LCLK_A0
LCD_FCLK_RD
HDR15SN-H
SHIELD
X24B
SHIELD2SHIELD2
NA
NA
NA
LCD_BIAS
LCD_D_6
LCD_D_4
LCD_D_0
LCD_D_10
LCD_D_1
LCD_D_14
LCD_D_15
LCD_D_8
LCD_D_2
LCD_D_3
LCD_D_13
LCD_D_12
LCD_D_11
LCD_D_9
LCD_D_7
LCD_D_16
LCD_D_17
LCD_LCLK_A0
LCD_FCLK_RD
LCD_PCLK_WR
LCD_D_5
GND
GND_PLL
GNDGND_LVDS
10nF
25V
C55 10nF
25V
C56
GND_LVDSGND_PLL
3.3V
0R
R27
GND
10nF
25V
C52 10nF
25V
C54
10nF
25V
C53
GND
3.3V
2A
220R@100MHzL17
2A
220R@100MHzL16 2A
220R@100MHz
L15
2A
220R@100MHz
L14
BL_ON
DS90C363BMT
TxIN13/BLUE1
15 TxIN12/BLUE0
13 TxIN11/GREEN5
12 TxIN10/GREEN4
10 TxIN9/GREEN3
9TxIN8/GREEN2
7TxIN7/GREEN1
6
TxIN20/DE
25 TxIN19/VSYINK
23 TxIN18/HSYNK
22 TxIN17/BLUE5
20 TxIN16/BLUE4
19 TxIN15/BLUE3
18 TxIN14/BLUE2
16
TxIN6/GREEN0
4TxIN5/RED5
3TxIN4/RED4
1TxIN3/RED3
48 TxIN2/RED2
47 TxIN1/RED1
45 TxIN0/RED0
44
TxCLKIN
26
TxOUT0+ 40
TxOUT0- 41
TxOUT1+ 38
TxOUT1- 39
TxOUT2+ 34
TxOUT2- 35
TxCLKOUT+ 32
TxCLKOUT- 33
1 of 2
IC4A
DS90C363BMT
VCC4
21 VCC2
8VCC1
2
R_FB
14
PWRDWN#
27
VCC-LVDS
37 VCC-PLL
29
NC
43
GND4 24
GND5 46
GND-PLL2 28
GND1 5
GND-LVDS1 42
GND2 11
GND3 17
GND-PLL1 30
GND-LVDS2 36
GND-LVDS3 31
2 of 2
IC4B
R28 1K
VCC_LVDS
VCC_PLL
LVDS_3.3V
100nF
16V
C51
GND
2A
220R@100MHz
L13
3.3V
100nF
16V
C50
2A
220R@100MHz
L12
GND
LVDS_5V5V
BL_ON
Power
LVDS1_CLK_N
LVDS1_CLK_P
LVDS1_OUT0_N
LVDS1_OUT0_P
LVDS1_OUT1_N
LVDS1_OUT1_P
LVDS1_OUT2_N
LVDS1_OUT2_P
GND
LVDS1[0..7]
DF13A-20DP-1.25v(56)
VCC_5V
1
VCC_LVDS
2
3
6
LVDS_OUT0-
5
LVDS_OUT0+
7
18
LVDS_OUT1-
8
LVDS_OUT1+
10
9
LVDS_OUT2-
11
LVDS_OUT2+
13
12
LVDS_CLK-
14
LVDS_CLK+
16
15
BL ON
17 BL CTRL
4
SEL1
19
SEL2
20
X18
LVDS1_CLK_N
LVDS1_CLK_P
LVDS1_OUT0_N
LVDS1_OUT0_P
LVDS1_OUT1_N
LVDS1_OUT1_P
LVDS1_OUT2_N
LVDS1_OUT2_P
PWM_BKL1
12
3
JP1
GND
12
3
JP2
R3
100K
GND
R4
100K
3.3V_LVDS1
5V_LVDS1
3.3V_LVDS1
5V_LVDS1
3.3V_LVDS1
5V_LVDS1
BKL1_ON
1473005-1
PIN_71/BL_ON 71
PIN_57/LDD_D_16 57
PIN_61/LDD_D_17 61
PIN_44/LDD_BIAS 44
PIN_46/LDD_D_7 46
PIN_48/LDD_D_9 48
PIN_50/LDD_D_11 50
PIN_52/LDD_D_12 52
PIN_54/LDD_D_13 54
PIN_56/LDD_PCLK_WR 56
PIN_58/LDD_D_3 58
PIN_60/LDD_D_2 60
PIN_62/LDD_D_8 62
PIN_64/LDD_D_15 64
PIN_66/LDD_D_14 66
PIN_68/LDD_LCLK_A0 68
PIN_70/LDD_D_1 70
PIN_72/LDD_D_5 72
PIN_74/LDD_D_10 74
PIN_76/LDD_D_0 76
PIN_78/LDD_D_4 78
PIN_80/LDD_D_6 80
PIN_82/LDD_FCLK_RD 82
Colibri -LDD
12 of 16
PIN_136/LDD_D_18/ADDR24 136
PIN_138/LDD_D_19/ADDR23 138
PIN_140/LDD_D_20/ADDR22 140
PIN_142/LDD_D_21/ADDR21 142
PIN_144/LDD_D_22/ADDR20 144
PIN_146/LDD_D_23/ADDR19 146
X1L SODIMM_44_S
SODIMM_46_S
SODIMM_48_S
SODIMM_50_S
SODIMM_52_S
SODIMM_54_S
SODIMM_56_S
SODIMM_58_S
SODIMM_60_S
SODIMM_62_S
SODIMM_64_S
SODIMM_66_S
SODIMM_68_S
SODIMM_70_S
SODIMM_72_S
SODIMM_74_S
SODIMM_76_S
SODIMM_78_S
SODIMM_80_S
SODIMM_82_S
SODIMM_57_S
SODIMM_61_S
SODIMM_71_S
22RRA5A 22RRA5B 22RRA5C 22RRA5D 22RRA6A 22RRA6B 22RRA6C 22RRA6D 22RRA7A 22RRA7B 22RRA7C 22RRA7D 22RRA8A 22RRA8B 22RRA8C 22RRA8D 22RRA9A 22RRA9B
22RRA4C 22RRA4D
22RRA30D 22RRA29C 22RRA1A BL_ON
LCD_BIAS
LCD_D_4
LCD_D_0
LCD_D_1
LCD_D_2
LCD_D_3
LCD_D_5
LCD_D_6
LCD_D_10
LCD_D_8
LCD_D_11
LCD_D_9
LCD_D_7
LCD_D_14
LCD_D_15
LCD_D_13
LCD_D_12
LCD_D_16
LCD_D_17
LCD_PCLK_WR
LCD_LCLK_A0
LCD_FCLK_RD
1473005-1
PIN_59/PWM_A 59
PIN_67 67
PIN_28/PWM_B 28
PIN_30/PWM_C 30
Colibri -PWM
5 of 16
X1E SODIMM_59_S 22RRA29D PWM_A

Colibri Carrier Board Design Guide
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Page | 16
18-bit Color Mapping
The color mapping for the 18-bit LVDS interface is standardized and is shown in the following
picture:
Figure 8: 18-bit LVDS Color Mapping
24-bit JEIDA Color Mapping
The JEIDA color mapping is compatible with the 18bit LVDS interface. Therefore, the mapping is
sometimes also called “24bit / 18bit Compatible Color Mapping”. The signal names of the color
bits are renamed (e.g. the 18bit R5 is renamed to 24bit R7) but the position of the MSB is kept the
same. The additional least significant bits R0, R1, G0, G1, B0 and B1 are located at the additional
fourth LVDS data pair.
Figure 9: 24-bit JEIDA LVDS Color Mapping
24-bit VESA Color Mapping
Most of the 24bit LVDS displays follow the VESA Color mapping. The VESA color mapping does not
rename the signal bits. This means that the position of the MSB is changed since they are available
at the additional data pair. Therefore, the VESA color mapping is not compatible with the 18bit
interface.
Figure 10: 24-bit VESA LVDS Color Mapping
2.4.3 Unused Parallel RGB Interface Signal Termination
All unused parallel RGB interface signals can be left unconnected.
LVDS1_A_CLK+
LVDS1_B_CLK+
LVDS1_A_TX0+/-
LVDS1_B_TX0+/-
LVDS1_A_TX1+/-
LVDS1_B_TX1+/-
LVDS1_A_TX2+/-
LVDS1_B_TX2+/-
Previous Cycle Current Cycle Next Cycle
G0 R5 R4 R3 R2 R1 R0
B1 B0 G5 G4 G3 G2 G1
DE VSYNC HSYNC B5 B4 B3 B2
LVDS1_A_CLK+
LVDS1_B_CLK+
LVDS1_A_TX0+/-
LVDS1_B_TX0+/-
LVDS1_A_TX1+/-
LVDS1_B_TX1+/-
LVDS1_A_TX2+/-
LVDS1_B_TX2+/-
LVDS1_A_TX3+/-
LVDS1_B_TX3+/-
Previous Cycle Current Cycle Next Cycle
G2 R7 R6 R5 R4 R3 R2
B3 B2 G7 G6 G5 G4 G3
DE VSYNC HSYNC B7 B6 B5 B4
N/A B1 B0 G1 G0 R1 R0
LVDS1_A_CLK+
LVDS1_B_CLK+
LVDS1_A_TX0+/-
LVDS1_B_TX0+/-
LVDS1_A_TX1+/-
LVDS1_B_TX1+/-
LVDS1_A_TX2+/-
LVDS1_B_TX2+/-
LVDS1_A_TX3+/-
LVDS1_B_TX3+/-
Previous Cycle Current Cycle Next Cycle
G0 R5 R4 R3 R2 R1 R0
B1 B0 G5 G4 G3 G2 G1
DE VSYNC HSYNC B5 B4 B3 B2
N/A B7 B6 G7 G6 R7 R6

Colibri Carrier Board Design Guide
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
Page | 17
2.5 HDMI/DVI
The HDMI and DVI interface uses a TMDS compatible physical link to transfer video and optional
audio data. While electrically, HDMI and DVI are both similar, but there can be a few differences in
their protocols. HDMI is the successor of DVI and specifies the additional transport for audio data
and content protection (HDCP). As HDMI is backward compatible, HDMI devices (monitor,
television set etc.) work with DVI signals. Forward compatibility is not guaranteed. Not all DVI
displays accept the HDMI protocol or are HDCP compatible. Please read the datasheet of the
Colibri modules for more information about the provided HDMI and DVI protocols.
The HDMI and DVI interface define different connectors. There are passive adapters available in
both types. Please be advised that both HDMI and HDCP require to be licensed. The HDMI/DVI
signals are available on a dedicated FFC connector. Check carefully to confirm which modules
provide the interface.
2.5.1 HDMI/DVI Signals
Colibri
FFC Pin
Colibri
Signal Name
I/O
Type
Power
Rail
Description
2
HDMI_1_CLK_P
O
TDMS
HDMI/DVI differential clock positive
3
HDMI_1_CLK_N
O
TDMS
HDMI/DVI differential clock negative
5
HDMI_1_DATA0_P
O
TDMS
HDMI/DVI differential data lane 0 positive
6
HDMI_1_DATA0_N
O
TDMS
HDMI/DVI differential data lane 0 negative
8
HDMI_1_DATA1_P
O
TDMS
HDMI/DVI differential data lane 1 positive
9
HDMI_1_DATA1_N
O
TDMS
HDMI/DVI differential data lane 1 negative
11
HDMI_1_DATA2_P
O
TDMS
HDMI/DVI differential data lane 2 positive
12
HDMI_1_DATA2_N
O
TDMS
HDMI/DVI differential data lane 2 negative
14
HDMI_1_HPD
I
CMOS
3.3V
Hot plug detect
16
HDMI_DDC_SDA
I/O
OD
3.3V
I2C interface for reading the extended display identification data (EDID)
over DDC.
15
HDMI_DDC_SCL
O
OD
3.3V
Table 8: HDMI/DVI Signals
2.5.2 Reference Schematics
2.5.2.1 DVI Schematic Example
There are different configurations of DVI connectors available. The DVI-D (digital) contains only the
native DVI signals The DVI-A (analogue) provides no DVI signals. Only the analogue VGA signals
are provided. The DVI-I (integrated) combines the digital DVI signals and the analogue VGA
signals. For the DVI-A and DVI-I, there are passive adapters available for the D-SUB VGA
connector. There is only one DDC channel available on the DVI-I interface. Therefore, the
connector is not designed to use both links (DVI and VGA) contemporaneously. Nevertheless, there
are Y-cables available which provides a DVI and VGA output contemporaneously. Such cables are
not standardized and provide normally the DDC only on the DVI or VGA output. Please be aware
of the DDC when using such a Y-cable.
The following schematic example shows a DVI-I implementation. It can also be used as an example
for a DVI-D design, just remove the analogue VGA signals. The sync signals for the VGA signals
need to be level shifted from 3.3V to 5V. The same is necessary for the DDC signals. The TDMS
signals need to be ESD protected by using diodes. The schematic example shows a discrete
solution for the level shifting and protection. There are also integrated solutions available.

Colibri Carrier Board Design Guide
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
Page | 18
Figure 11: DVI-I Reference Schematic
2.5.2.2 HDMI Schematic Example
The HDMI connector does not feature an Analogue VGA interface, but there is an optional
Consumer Electronics Control (CEC) interface available on the connector. The location of the CEC
signal is not standardized on the Colibri modules. Check the datasheet of the modules for more
information to the position of the signal. The CEC is a single- wire interface that is used to control
consumer audio and video devices such as television set or AV receivers. There are many different
trade names for CEC (VIERA Link, Anynet+, EasyLink, Aquos Link, BRAVIA Link, etc.). The CEC is a
3.3V interface. Nevertheless, it is recommended to add level shifter from the internal 3.3V logic
level. This eliminates problems with displays that pull-up the signal to other voltage levels.
The I2C signals for the DDC and the hot plug detection (HPD) need to be shifted to/from the 5V
logic level of the HDMI to the Colibri level of 3.3V. The HPD has a 100kΩpull down resistor
already on the baseboard
TMDS_CLK_P
TMDS_CLK_N
TMDS_DATA0_P
TMDS_DATA0_N
TMDS_DATA1_P
TMDS_DATA1_N
TMDS_DATA2_P
TMDS_DATA2_N
GND
CRT_VSYNC
CRT_HSYNC
CRT_BLUE
CRT_GREEN
CRT_RED
DDC_CLK
DDC_DATA
5V
74320-1004
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C1
C2
C3
C4
C5
SHIELD X2
SHIELD X1
X5
HOTPLUG_DETECT
BAT54
D2
GND
GND
GND
GND
DVI_5V
GND
HOTPLUG_DETECT_T
DDC_CLK_T
DDC_DATA_T
CRT_RED_T
CRT_GREEN_T
CRT_BLUE_T
CRT_VSYNC_T
CRT_HSYNC_T
RCLAMP0504S
1
2
34
5
6
D4
TMDS_CLK_P
TMDS_CLK_N
TMDS_DATA0_P
TMDS_DATA0_N
TMDS_DATA1_P
TMDS_DATA1_N
TMDS_DATA2_P
TMDS_DATA2_N
47pF
50V
C12
GND
47pF
50V
C14
GND
10pF
50V
C18
10pF
50VC19150RR9
GND
GND
1K
R18 220pF
50V
C34 GND
1.8KR
R19
1.8KR
R17
DDC_CLK
DDC_DATA
RCLAMP0504S
1
2
34
5
6
D1
RCLAMP0504S
1
2
3
4
5
6
D5
500mA
220R@100MHz
L1
500mA
220R@100MHz
L2
500mA
220R@100MHz
L8
500mA
220R@100MHz
L9
PLACE D1, D3, D4, D5 NEARTHE DVI-I CONNECTOR
SN74LVC1G17
NC 1
A
2
GND
3
Y4
VCC
5
IC1
SN74LVC1G17
NC 1
A
2
GND
3
Y4
VCC
5
IC2
5V
5V
GND
33R
R5
33R
R4
100nF
16V
C13
100nF
16V
C15
SHIELD2
SHIELD2
600mA
40R@100MHz
L3
4.7pF
50V
C32
4.7pF
50V
C33
DVI_5V
DVI_5V
10pF
50V
C20
150RR10
GND
GND 10pF
50VC21
600mA
40R@100MHz
L4
10pF
50V
C22
150RR13
GND
GND 10pF
50VC23
600mA
40R@100MHz
L5
FH12-24S-0.5SV(55)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
X6
GND
CRT_VSYNC
CRT_HSYNC
RCLAMP0504S
1
2
34
5
6
D3
SHIELD2 SHIELD2
CRT_BLUE
CRT_GREEN
CRT_RED
GND
GND
GND
GND
SHIELD2
DVI-I Connector
FFCConnector
HOTPLUG_DETECT
GND GND
TMDS_CLK_P
TMDS_CLK_N
TMDS_DATA0_P
TMDS_DATA0_N
TMDS_DATA1_P
TMDS_DATA1_N
TMDS_DATA2_P
TMDS_DATA2_N
DVI_5V

Colibri Carrier Board Design Guide
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
Page | 19
Figure 12: HDMI Reference Schematic
2.5.3 Unused HDMI/DVI Signal Termination
All unused HDMI/DVI signals can be left unconnected. The HPD has a 100kΩpull down resistor on
the module.
Colibri
Pin
Colibri
Signal Name
Recommended Termination
2
HDMI_1_CLK_P
Leave NC if not used
3
HDMI_1_CLK_N
Leave NC if not used
5
HDMI_1_DATA0_P
Leave NC if not used
6
HDMI_1_DATA0_N
Leave NC if not used
8
HDMI_1_DATA1_P
Leave NC if not used
9
HDMI_1_DATA1_N
Leave NC if not used
11
HDMI_1_DATA2_P
Leave NC if not used
12
HDMI_1_DATA2_N
Leave NC if not used
14
HDMI_1_HPD
Leave NC if not used, 100kΩ resistor on Colibri module
16
HDMI_DDC_SDA
Add pull-up resistor or disable the I2C function in software
15
HDMI_DDC_SCL
Add pull-up resistor or disable the I2C function in software
Table 9: Unused HDMI/DVI Signals Termination
52435-2471
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
X2
GND
GND
GND
GND
GND
GND
GND
TMDS_CLK_P
TMDS_CLK_N
TMDS_DATA0_P
TMDS_DATA0_N
TMDS_DATA1_P
TMDS_DATA1_N
TMDS_DATA2_P
TMDS_DATA2_N
HOTPLUG_DETECT_T
R1
1K
DDC_SCL_T
DDC_SDA_T
RCLAMP0504S
1
2
34
5
6
D1
10029449-111RLF
TDMS_D2P
1
TDMS_D2_Shield
2
TDMS_D2N
3
TDMS_D1P
4
TDMS_D1_Shield
5
TDMS_D1N
6
TDMS_D0P
7
TDMS_D0_Shield
8
TDMS_D0N
9
TDMS_CLKP
10
TDMS_CLK_Shield
11
TDMS_CLKN
12
CEC
13
HEC
14
DDR_SCL
15
DDR_SDA
16
GND
17
PWR_5V_50mA
18
HotPlug_HECDP
19
SH1 S1
SH2 S2
SH3 S3
SH4 S4
X1
RCLAMP0504S
1
2
34
5
6
D2
SHIELD SHIELD
SHIELD
TMDS_CLK_P
TMDS_CLK_N
TMDS_DATA0_P
TMDS_DATA0_N
TMDS_DATA1_P
TMDS_DATA1_N
TMDS_DATA2_P
TMDS_DATA2_N
GND
GND
GND
GND
GND
HOTPLUG_DETECT
HDMI_I2C_SCL
HDMI_I2C_SDA
220pF
50V
C1
HOTPLUG_DETECT
HDMI_I2C_SCL
HDMI_I2C_SDA
5V_HDMI
R2
1.8K
R3
1.8K
4.7pF
50V
C2
4.7pF
50V
C3
GND
GND
220R@100MHz
500mA
L1
220R@100MHz
500mA
L2
GND
RCLAMP0504S
1
2
34
5
6
D3
SHIELD
5V_HDMI
5V_HDMI
DIFF100
DIFF100
DIFF100
DIFF100
DIFF100
DIFF100
DIFF100
DIFF100
5V
BAT54
D4
5V_HDMI
TMDS_CLK_P
TMDS_CLK_N
TMDS_DATA0_P
TMDS_DATA0_N
TMDS_DATA1_P
TMDS_DATA1_N
TMDS_DATA2_P
TMDS_DATA2_N
FFC Connector

Colibri Carrier Board Design Guide
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
Page | 20
2.6 Analogue VGA
Some Colibri modules feature a dedicated VGA interface on the HDMI FFC connector. For systems
which need to be compatible with a wide range of Colibri modules, it is recommended to use a
parallel RGB to VGA DAC instead of the dedicated VGA interface.
2.6.1 VGA Signals
Colibri
FFC Pin
Colibri
Signal Name
I/O
Type
Power
Rail
Description
18
VGA_1_R
O
Analogue
Analogue red video (0 to 0.7V)
20
VGA_1_G
O
Analogue
Analogue green video (0 to 0.7V)
22
VGA_1_B
O
Analogue
Analogue blue video (0 to 0.7V)
24
VGA_1_HSYNC
O
CMOS
3.3V
Horizontal sync
23
VGA_1_VSYNC
O
CMOS
3.3V
Vertical sync
16
HDMI_DDC_SDA
I/O
OD
3.3V/
5V tolerant
I2C interface for reading the extended display identification data
(EDID) over DDC. Signal shared with the HDMI interface
15
HDMI_DDC_SCL
O
OD
3.3V/
5V tolerant
Table 10: VGA Signals
2.6.2 Reference Schematics
The horizontal and vertical sync signals need to be level shifted on the baseboard. The DDC signals
on the FFC connector do not require a level shifter since these signals are 5V tolerant. If a different
I2C interface is used as DDC, the shifters are needed. In the VGA connector standard, the carrier
board needs to provide 5V power supply for the EDID memory on the DDC. This allows the system
to read out the EDID information of an attached display even if it is not powered. Unfortunately,
some displays source the 5V internally and also provide internal pull-up resistors to the I2C lines.
This can cause back feeding problems. Therefore we recommend connecting the display and pull-
up resistor 5V supply over a diode to the module supply.
It is mandatory to place on every analogue RGB signal a 150Ωresistor to ground. Place this
resistor as close to the VGA connector as possible. Before this resistor, the signal trace can be
routed with 50Ωimpedance. After the resistor, the signal should be routed with 75Ωimpedance.
Depending on the layer stack up, 75Ω traces cannot be reached since the trace with is getting too
small. In this case, lower traces impedance (e.g. 50Ω) can be used but the trace length should be
kept short.
All signals on the VGA D-SUB connector need to be ESD protected. TSR diodes can be used. It is
recommended to add a PI-filter to the analogue RGB signals. The values for the capacitors and
inductors depend on the maximum required display resolution. The PI-filter reduces EMI problems,
but also limits the maximum bandwidth of the VGA signal.