Toradex Verdin User manual

Verdin Computer Module
Carrier Board Design Guide

Verdin Carrier Board Design Guide
Preliminary –Subject to Change
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Issued by:
Toradex
Document Type:
Carrier Board Design Guide
Purpose:
This document is a guideline for developing a carrier board that conforms to the
specifications for the Verdin Computer Module
Document
Version:
0.94
Revision History
Date
Version
Remarks
June 30, 2020
V0.9
Initial Release: Preliminary Version
October 16, 2020
V0.91
Correct position of standoff holes in carrier board land pattern drawing (Figure 92)
Remove additional notches from the drawings of the module
October 28, 2020
V0.92
Correction of CTRL_SLEEP_MOCI# signal type from open drain to CMOS
Correction of standoff hole position in Figure 3
Section 2.6: add information to DSI display adapters
January 5, 2021
V0.93
Replace front picture
Section 2.5.2.2: Change HDMI ESD protection IC in reference schematic
February 5, 2021
V0.94
Add section 3.5 Backfeeding
Section 2.2.2.3: Update figure 10
Section 2.3.2.2: Update figure 15
Section 2.5.2.1: Update figure 28
Section 2.7.2: Update figure 36

Verdin Carrier Board Design Guide
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Contents
1Introduction................................................................................................................... 6
1.1 Overview........................................................................................................................ 6
1.2 Additional Documents...................................................................................................... 6
1.2.1 Layout Design Guide............................................................................................. 6
1.2.2 Verdin Module Datasheets ..................................................................................... 6
1.2.3 Verdin Module Definition........................................................................................ 6
1.2.4 Toradex Developer Center..................................................................................... 6
1.2.5 Verdin Reference Designs...................................................................................... 7
1.2.6 Pinout Designer .................................................................................................... 7
1.3 Abbreviations.................................................................................................................. 7
2Interfaces.................................................................................................................... 10
2.1 Architecture.................................................................................................................. 10
2.1.1 "Always Compatible" Interfaces............................................................................. 11
2.1.2 "Reserved" Interfaces.......................................................................................... 12
2.1.3 "Module-specific" Interfaces.................................................................................. 13
2.1.4 Pin Numbering.................................................................................................... 13
2.2 PCI Express ................................................................................................................. 15
2.2.1 PCIe Signals....................................................................................................... 15
2.2.2 Reference Schematics......................................................................................... 15
2.2.3 Unused PCIe Signals Termination......................................................................... 21
2.3 Ethernet....................................................................................................................... 21
2.3.1 Media Dependent Ethernet Port............................................................................ 21
2.3.2 Reduced Gigabit Media-Independent Interface Ethernet Port.................................... 24
2.4 USB............................................................................................................................. 25
2.4.1 USB Signals....................................................................................................... 26
2.4.2 Reference Schematics......................................................................................... 27
2.4.3 Unused USB Signal Termination........................................................................... 32
2.5 HDMI/DVI..................................................................................................................... 33
2.5.1 HDMI/DVI Signals............................................................................................... 33
2.5.2 Reference Schematics......................................................................................... 33
2.5.3 Unused HDMI/DVI Signal Termination................................................................... 35
2.6 Display Serial Interface (MIPI DSI) .................................................................................. 35
2.6.1 MIPI DSI Signals................................................................................................. 36
2.6.2 Reference Schematics......................................................................................... 36
2.6.3 MIPI DSI Display Adapters................................................................................... 39
2.6.4 Unused MIPI DSI Signal Termination..................................................................... 42
2.7 Camera Serial Interface (MIPI CSI-2)............................................................................... 42
2.7.1 MIPI CSI-2 Signals.............................................................................................. 43
2.7.2 Reference Schematics......................................................................................... 43
2.8 SD/MMC/SDIO.............................................................................................................. 44
2.8.1 SD/MMC/SDIO Signals........................................................................................ 44
2.8.2 Reference Schematics......................................................................................... 44
2.8.3 Unused SD/MMC/SDIO Interface Signal Termination .............................................. 45
2.9 I2C............................................................................................................................... 45
2.9.1 I2C Signals ......................................................................................................... 46
2.9.2 Reference Schematics......................................................................................... 46
2.9.3 Unused I2C Signal Termination............................................................................. 46
2.10 UART........................................................................................................................... 46
2.10.1 UART Signals.................................................................................................. 47
2.10.2 Reference Schematics...................................................................................... 47
2.10.3 Unused UART Signal Termination...................................................................... 49
2.11 SPI.............................................................................................................................. 49
2.11.1 SPI Signals..................................................................................................... 50

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2.11.2 Unused SPI Signal Termination......................................................................... 50
2.12 Quad Serial Peripheral Interface (Quad SPI)..................................................................... 50
2.12.1 Quad SPI Signals............................................................................................. 50
2.12.2 Unused Quad SPI Signal Termination ................................................................ 50
2.13 CAN ............................................................................................................................ 51
2.13.1 CAN Signals.................................................................................................... 51
2.13.2 Reference Schematics...................................................................................... 51
2.13.3 Unused CAN Interface Signal Termination.......................................................... 51
2.14 PWM ........................................................................................................................... 52
2.14.1 PWM Signals................................................................................................... 52
2.14.2 Reference Schematics...................................................................................... 52
2.14.3 Unused PWM Signal Termination ...................................................................... 52
2.15 Inter-IC Sound (I2S)....................................................................................................... 53
2.15.1 Digital Audio Signals ........................................................................................ 53
2.15.2 Reference Schematics...................................................................................... 54
2.15.3 Unused Digital Audio Interface Signal Termination............................................... 54
2.16 Analog Inputs................................................................................................................ 54
2.16.1 Analog Input Signals ........................................................................................ 54
2.16.2 Unused Analog Inputs Signal Termination........................................................... 54
2.17 General Purpose Clock Outputs...................................................................................... 55
2.17.1 Clock Output Signals........................................................................................ 55
2.17.2 Schematic and Layout Considerations................................................................ 55
2.17.3 Unused Clock Output Signal Termination............................................................ 55
2.18 GPIO........................................................................................................................... 55
2.18.1 GPIO Signals .................................................................................................. 55
2.18.2 Unused GPIO Termination................................................................................ 56
2.19 JTAG interface.............................................................................................................. 56
2.19.1 JTAG Signals.................................................................................................. 56
2.19.2 Reference Schematics...................................................................................... 56
2.19.3 Unused JTAG Signal Termination...................................................................... 57
2.20 Module Recovery .......................................................................................................... 57
2.20.1 Recovery Signals............................................................................................. 57
2.20.2 Reference Schematics...................................................................................... 57
2.20.3 Unused Recovery Signal Termination................................................................. 58
3Power Management..................................................................................................... 59
3.1 Power Signals............................................................................................................... 59
3.1.1 Power Supply Signals.......................................................................................... 59
3.1.2 Power Management Signals................................................................................. 59
3.2 Module Power States..................................................................................................... 60
3.3 General Power Sequences............................................................................................. 62
3.3.1 “No VCC” to “Running” (startup)............................................................................ 62
3.3.2 “Running” to “Reset” (reset).................................................................................. 63
3.3.3 “Reset” to “Running” (startup after reset)................................................................ 64
3.3.4 “Running” to “Sleep” (sleep).................................................................................. 65
3.3.5 “Sleep” to “Running” (wake).................................................................................. 66
3.3.6 “Running” to “Module OFF” (shutdown).................................................................. 67
3.3.7 “Running” to “No VCC” (force off) .......................................................................... 68
3.3.8 “Module OFF” to “Running” (startup after shutdown) ................................................ 69
3.3.9 “Module OFF” to “No VCC” (power off after shutdown)............................................. 70
3.3.10 Remove VCC in any power state ....................................................................... 70
3.4 Power Supply Use Cases............................................................................................... 71
3.4.1 Switched VCC Approach (Verdin Development Board)............................................ 71
3.4.2 Minimalist Carrier Board Power Approach.............................................................. 74
3.4.3 Single Cell Battery Power Approach...................................................................... 77
3.5 Backfeeding.................................................................................................................. 79
3.5.1 Introduction ........................................................................................................ 79
3.5.2 What is Backfeeding............................................................................................ 80

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3.5.3 Potential Issues Caused by Backfeeding................................................................ 82
3.5.4 Identify Backfeeding Issues.................................................................................. 83
3.5.5 Backfeeding Prevention....................................................................................... 86
4Mechanical and Thermal Consideration........................................................................ 95
4.1 Module Connector and Stacking Height ........................................................................... 95
4.2 Fixation of the Module.................................................................................................... 96
4.3 Thermal Solution........................................................................................................... 96
4.4 Module Dimensions....................................................................................................... 97
4.5 Connector and Standoff Land Pattern Requirements ......................................................... 97
4.6 Carrier Board Space Requirements................................................................................. 98
5Appendix A –Module Top Side Signal Definition.......................................................... 99
6Appendix B –Module Bottom Side Signal Definition................................................... 103
7Appendix C - Physical Pin Definition and Location ..................................................... 107

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1 Introduction
1.1 Overview
This document guides users through the development of a customized carrier board for the Verdin
System-on-Module (SoM) family. It describes the different interfaces of those modules and provides
reference schematics as well. The document highlights standardized features of Verdin SoMs
(compatible between different modules). "Module-specific" interfaces, features and alternate
functions are not detailed in this document. These interfaces are detailed in the respective
datasheets of Verdin SoMs. Some Verdin modules do not feature the full set of the "Reserved"
interfaces. It is strongly recommended to always read the datasheet of the module that is intended
to be used with and off-the-shelf or a custom carrier board.
Verdin modules feature new high-speed interfaces such as PCI Express, HDMI, MIPI CSI and DSI
which require special layout considerations regarding trace impedance and length matching.
Please read carefully the Toradex Layout Design Guide for additional information on the routing of
these interfaces.
1.2 Additional Documents
1.2.1 Layout Design Guide
This document contains layout requirement specifications for high-speed signals and helps to avoid
issues related to layout.
https://developer.toradex.com/carrier-board-design
1.2.2 Verdin Module Datasheets
For every Verdin Module, there is a datasheet available. Among other things, this document
describes the "Module-specific" interfaces and secondary functionalities of pins. Before starting the
development of a customized carrier board, please check these documents to verify if the required
interfaces are available on the selected modules.
https://www.toradex.com/computer-on-modules/verdin-arm-family
1.2.3 Verdin Module Definition
This document describes the Verdin Module standard. It provides information on the mechanical
and electrical properties of Verdin modules, in addition to functionalities and interfaces provided
by those modules.
The document is available soon.
1.2.4 Toradex Developer Center
You can find a lot of additional information in the Toradex Developer Center, which is updated
with the latest product support information on a regular basis.
Please note that the Developer Center is common for all Toradex products. You should always
check to ensure if information is valid or relevant to the Verdin modules.
https://developer.toradex.com/

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1.2.5 Verdin Reference Designs
Schematic files, assembly drawings, bills of material and the complete Altium project files for the
Verdin reference carrier boards are available for download for free. There is also an online viewer
available which is convenient to use for customers without a license for Altium.
https://developer.toradex.com/carrier-board-design/reference-designs
1.2.6 Pinout Designer
The Toradex Pinout Designer is a powerful tool for evaluating different pin multiplexing options for
Verdin, Apalis, and Colibri Modules. Defining the pin multiplexing configuration to use or design
for is a vital step in the process of designing a custom carrier board.
The tool allows comparing interfaces across different modules as well.
http://developer.toradex.com/knowledge-base/pinout-designer
1.3 Abbreviations
Abbreviation
Explanation
ADC
Analog to Digital Converter
AGND
Analog Ground, separate ground for analog signals
Auto-MDIX
Automatically Medium Dependent Interface Crossing, a PHY with Auto-MDIX can detect whether RX and
TX need to be crossed (MDI or MDIX)
BSP
Board Support Package
CAD
Computer-Aided Design, in this document is referred to PCB Layout tools
CAN
Controller Area Network, a bus that is manly used in automotive and industrial environment
CAN FD
Controller Area Network Flexible Data-Rate, an extension to the original CAN bus protocol which allows
higher data rates and larger message sizes.
CEC
Consumer Electronic Control, HDMI feature that allows to control CEC compatible devices
CPU
Central Processor Unit
CSI
Camera Serial Interface
DAC
Digital to Analog Converter
DDC
Display Data Channel, interface for reading out the capability of a monitor, in this document DDC2B
(based on I2C) is always meant
DFP
Downstream Facing Port, USB Type-C port that acts as a host
DRC
Design Rule Check, a tool for checking whether all design rules are satisfied in a CAD tool
DRD
Dual-Role Data, USB Type-C port that can act as host or device
DRP
Dual-Role Port, USB Type-C port that can operate as power sink and source
DSI
Display Serial Interface
DVI
Digital Visual Interface, digital signals are electrical compatible with HDMI
DVI-A
Digital Visual Interface Analog only, signals are compatible with VGA
DVI-D
Digital Visual Interface Digital only, signals are electrical compatible with HDMI
DVI-I
Digital Visual Interface Integrated, combines digital and analog video signals in one connector
EDA
Electronic Design Automation, software for schematic capture and PCB layout (CAD or ECAD)
EDID
Extended Display Identification Data, timing setting information provided by the display in a PROM
EMI
Electromagnetic Interference, high frequency disturbances
eMMC
Embedded Multi Media Card, flash memory combined with MMC interface controller in a BGA package,
used as internal flash memory
ESD
Electrostatic Discharge, high voltage spike or spark that can damage electrostatic- sensitive devices
FPD-Link
Flat Panel Display Link, high-speed serial interface for liquid crystal displays. In this document also called
LVDS interface.
GBE
Gigabit Ethernet, Ethernet interface with a maximum data rate of 1000Mbit/s
GMII
Gigabit Media-Independent Interface, interface between Ethernet MAC and PHY for up to 1Gb/s

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Abbreviation
Explanation
GND
Ground
GPI
General Purpose Input
GPIO
General Purpose Input/Output, pin that can be configured being an input or output
GPO
General Purpose Output
GSM
Global System for Mobile Communications
HDA
High Definition Audio (HD Audio), digital audio interface between CPU and audio codec
HDCP
High-Bandwidth Digital content Protection, copy protection system that is used by HDMI beside others
HDMI
High-Definition Multimedia Interface, combines audio and video signal for connecting monitors, TV sets or
Projectors, electrical compatible with DVI-D
I2C
Inter-Integrated Circuit, two-wire interface for connecting low-speed peripherals
I2S
Integrated Interchip Sound, serial bus for connecting PCM audio data between two devices
IrDA
Infrared Data Association, infrared interface for connecting peripherals
JTAG
Joint Test Action Group, widely used debug interface
LCD
Liquid Crystal Display
LSB
Least Significant Bit
LVDS
Low-Voltage Differential Signaling, electrical interface standard that can transport high-speed signals over
twisted-pair cables. Many interfaces like PCIe or SATA use this interface. Since the first successful
application was the Flat Panel Display Link, LVDS became a synonymous for this interface. In this
document, the term LVDS is used for the FPD-Link interface.
MAC
Medium Access Control, is part of the second layer (data link layer) in the Ethernet stack
MII
Media-Independent Interface, interface between Ethernet MAC and PHY for up to 100Mb/s
MIPI
Mobile Industry Processor Interface Alliance
MDI
Medium Dependent Interface, physical interface between Ethernet PHY and cable connector
MDIO
Management Data Input/Output, an interface that is used for controlling the Ethernet PHY. The bus
consists of the MDC clock and the MDIO bidirectional data signal.
MDIX
Medium Dependent Interface Crossed, an MDI interface with crossed RX and TX interfaces
mini PCIe
PCI Express Mini Card, card form factor for internal peripherals. The interface features PCIe and USB 2.0
connectivity
MMC
MultiMediaCard, flash memory card
MSB
Most Significant Bit
mSATA
Mini-SATA, a standardized form factor for small solid-state drive, similar dimensions as mini PCIe
MXM3
Mobile PCI Express Module (second generation), graphic card standard for mobile device, the Apalis form
factor uses the physical connector but not the pin-out and the PCB dimensions of the MXM3 standard.
N/A
Not Available
N/C
Not Connected
OD
Open Drain
OTG
USB On-The-Go, a USB host interface that can also act as USB client when connected to another host
interface
OWR
One Wire (1-Wire), low-speed interface which needs just one data wire plus ground
PCB
Printed Circuit Board
PCI
Peripheral Component Interconnect, parallel computer expansion bus for connecting peripherals
PCIe
PCI Express, high-speed serial computer expansion bus, replaces the PCI bus
PCM
Pulse-Code Modulation, digitally representation of analog signals, standard interface for digital audio
PD
Pull-Down Resistor
PHY
Physical Layer of the OSI model
PMIC
Power Management IC, integrated circuit that manages amongst others the power sequence of a system
PU
Pull-up Resistor
PWM
Pulse-Width Modulation
QSPI
Quad SPI, SPI interface with four bidirectional data signals
RGB
Red Green Blue, color channels in common display interfaces
RGMII
Reduced Gigabit Media-Independent Interface, interface between Ethernet MAC and PHY for up to 1Gb/s
RJ45
Registered Jack, common name for the 8P8C modular connector that is used for Ethernet wiring
RMII
Reduced Media-Independent Interface, interface between Ethernet MAC and PHY for up to 100Mb/s

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Abbreviation
Explanation
RS232
Single ended serial port interface
RS422
Differential signaling serial port interface, full duplex
RS485
Differential signaling serial port interface, half duplex, multi drop configuration possible
R-UIM
Removable User Identity Module, identifications card for CDMA phones and networks, an extension of the
GSM SIM card
S/PDIF
Sony/Philips Digital Interconnect Format, optical or coaxial interface for audio signals
SATA
Serial ATA, high-speed differential signaling interface for hard drives and SSD
SD
Secure Digital, flash memory card
SDIO
Secure Digital Input Output, an external bus for peripherals that uses the SD interface
SIM
Subscriber Identification Module, identification card for GSM phones
SMBus
System Management Bus (SMB), two wire bus based on the I2C specifications, used specially in x86
design for system management.
SoC
System on a Chip, IC which integrates the main component of a computer on a single chip
SPI
Serial Peripheral Interface Bus, synchronous four wire full duplex bus for peripherals
TIM
Thermal Interface Material, thermal conductive material between CPU and heat spreader or heat sink
TMDS
Transition-Minimized Differential Signaling, serial high-speed transmitting technology that is used by DVI
and HDMI
TVS Diode
Transient-Voltage-Suppression Diode, diode that is used to protect interfaces against voltage spikes
UFP
Upstream Facing Port, USB Type-C port that acts as a client
UART
Universal Asynchronous Receiver/Transmitter, serial interface, in combination with a transceiver a RS232,
RS422, RS485, IrDA or similar interface can be achieved
USB
Universal Serial Bus, serial interface for internal and external peripherals
VCC
Positive supply voltage
VGA
Video Graphics Array, analog video interface for monitors
Table 1: Abbreviations

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2 Interfaces
2.1 Architecture
The block diagram in Figure 1 shows the basic architecture of the Verdin module, depicting the
“Always Compatible”interfaces, “Reserved”interfaces, and some examples of “Module-specific”
interfaces.
1x Gigabit Ethernet
1x RGMII
1x LVDS
1x USB 2.0 OTG
1x USB 2.0 Host
1x I2C
1x SPI
3x UART (RX, TX only)
1x PWM
10x GPIO
1x SDIO
1x USB SuperSpeed Lane
1x PCIe (1x Lane)
1x HDMI
3x I2C
1x QSPI
2x UART (Extra RTS, CTS)
1x UART (RX, TX only)
2x CAN
1x MIPI DSI (4x Lanes)
1x MIPI CSI-2 (4x Lanes)
2x I2S
2x PWM
4x ADC
1x SDIO
1x MIPI CSI-2 (4x Lanes)
Verdin
Module
3.135 to 5.5V Input
System Control
RTC Backup
eMMC
M.2 1216
Wi-Fi
Bluetooth
RAM
EEPROM
RTC
Always Compatible Reserved Module-Specific (examples)

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Features of Verdin modules are split into three distinct groups: "Always Compatible", "Reserved"
and "Module-specific".
"Always Compatible" interfaces are features that shall be present on each SoM in the Verdin
Family. Customers can expect on upgradeability and maximum scalability.
"Reserved" interfaces are features that are defined and reserved, but possibly missing on some
Verdin SoMs. The reason for that could be that a certain SoC does not feature an interface or there
is an assembly option which omits certain interfaces for cost optimization purposes. Replacement
pins must be electrically compatible with the functionality specified. This means that any Verdin
SoM can be inserted into any Verdin carrier board without risking damage to the module or to the
carrier board (caused by electrically not compatible pins).
A "Module-specific" feature is a feature which is not guaranteed to be functionally or electrically
compatible across Verdin modules. If a carrier board design uses such features, then it is possible
that other modules in the Verdin module family do not provide these features and instead provide
other features on the associated pins. In this case, Verdin modules which are suitable for being
used together with the carrier board design may need to be restricted. An incompatible
SoM/carrier board combination may disable any/all functionalities or even possibly damage the
SoM and/or the carrier board. Using or relying on functionalities provided on "Module-specific"
pins or interfaces in the context of a carrier board could make upgrades to other Verdin modules
impossible.
2.1.1 "Always Compatible" Interfaces
The table below shows the "Always Compatible" interfaces that are provided by each and every
Verdin module. The “GPIO Capable” column indicates whether, for a specific interface, the
assigned pins can be used as GPIOs.
The “Instances” column indicates the number of interfaces that the Verdin specification defines for
the "Always Compatible" interfaces. Even though the "Always Compatible" interfaces shall be
available on all Verdin modules, customers should consult the datasheet for specific Verdin module
variants to check for special features or restrictions of the interface.
Description
Instances
Note
GPIO
Capable
Gigabit Ethernet
1
Media dependent interface (PHY on module), backward
compatible with Fast Ethernet.
No
USB 2.0 Host
1
High-Speed USB, backward compatible with Full and Low
Speed USB.
No
USB 2.0 OTG
1
Can be configured for host or client usage. SoC usually
use this port in recovery mode.
No
I2C
1
General Purpose
Yes*
SPI
1
Single chip select pin
Yes*
UART (RX, TX)
2
General Purpose
Yes*
UART (RX, TX)
1
Primary operating system debug port (console)
Yes*
PWM
1
General Purpose
Yes*
SDIO
1
4-bit interface, I/O voltage might be switchable between
1.8V and 3.3V for UHS-I support
Yes*
GPIO
4
General Purpose
Yes
JTAG
1
No*
Table 2: "Always Compatible" Interfaces
*May differ on some modules. Please check the datasheet of the respective module or the Pinout
Designer tool.

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2.1.2 "Reserved" Interfaces
Some of the "Reserved" interfaces are adding extra functionality to an "Always Compatible"
interface. E.g. the additional USB 3.x SuperSpeed signals in the "Reserved" class are required to be
used in conjunction with the USB 2.0 Host interface signals in the "Always Compatible" class. There
are additional RTS/CTS hardware flow control signals which need to be used in conjunction with
the respective general purpose UARTs found in the "Always Compatible" class.
Since "Reserved" interfaces are possibly not provided by some modules, it is mandatory to consult
module datasheets for further information. A useful tool is the Toradex Pinout Designer which
supports comparing the available features of different Verdin modules.
If a module does not feature all possible instances of "Reserved" interfaces (defined by the Verdin
standard), interfaces will be filled in an ascending order (starting from the lowest instance index).
For example, in the Verdin standard, there are two CAN interfaces (CAN_1 and CAN_2). Both are
in the "Reserved" class. If only one CAN is required by a custom carrier board design, it is advisable
to use CAN_1. This guarantees better compatibility with other Verdin modules that e.g. feature a
single CAN interface (CAN_1) only.
Some interfaces (I2C and PWM) have instances that are reserved for other interfaces (e.g HDMI).
When filling interfaces during the design of Verdin SoMs, these instances are prioritized according
to the availability of the interface they belong to. For example, there are up to four I2C instances in
the Verdin specification (I2C_1, I2C_2_DSI, I2C_3_HDMI, I2C_4_CSI). If a SoC features only three
I2C instances and offers no HDMI interface but has a CSI interface, the following interface
interfaces will be provided by the module: I2C_1, I2C_2_DSI and I2C_4_CSI. As the example
shows, in these cases the indices of interfaces provided can be non-continuous.
Description
Standard
Note
GPIO
Capable
MIPI DSI
1
Primary display interface, up to 4 data lanes.
No
HDMI
1
Secondary display interface
No
RGMII
1
Backward compatibility with RMII is not mandatory
Optional
USB 3.x Host
1
Additional SuperSpeed signals that need to be used in
conjunction with the USB 2.0 Host interface
No
PCIe
1
1 lane with reference clock. Supported generation depends
on the module
No
I2C
3
1x reserved for DSI (might be usable as general purpose)
1x reserved for HDMI (might be usable as general
purpose)
1x reserved for CSI (might be usable as general purpose)
Yes*
QSPI
1
Backward compatible with SPI interface, independent from
general purpose SPI interface.
Yes*
UART (RX, TX)
1
Secondary operating system (real-time OS) debug port.
Might be usable as general purpose UART.
Yes*
UART (RTS, CTS)
2
Complementary hardware flow control signals for the fully
compatible general purpose UART interfaces
Yes*
CAN
2
CAN or CAN FD compatible
Yes*
MIPI CSI-2
1
Up to 4 data lanes
No
PWM
2
1x general purpose
1x reserved for display backlight control
Yes*
I2S
2
1x with master clock output
1x without master clock output
Yes*
GPIO
6
2x reserved for MIPI DSI
4x reserved for MIPI CSI-2
Yes
ADC
4
No*
Table 3: "Reserved" Interfaces

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*May differ on some modules. Please check the datasheet of the respective module or the Pinout
Designer tool.
2.1.3 "Module-specific" Interfaces
"Module-specific" interfaces allow for the possibility of including and providing module interfaces to
customers which may not be widely adopted (yet), or may be specific to a device or groups of
devices. They also offer a mechanism for extending features which are present on "Always
Compatible" or "Reserved" interfaces, e.g. providing additional PCI-Express lanes.
It should be noted that "Module-specific" interfaces will be kept common across modules that share
such interfaces (whenever possible). For example, if both module A and module B have an LVDS
interface in the "Module-specific" category, then they shall be provided on the same "Module-
specific" pins. Hence, both module A and module B shall share compatibility between these parts
of the "Module-specific" interface. Please not that exceptions are possible to this rule. Please always
consult the datasheet(s) of the respective module(s).
2.1.4 Pin Numbering
The Verdin module follows the same pin numbering scheme as the SODIMM DDR4 standard. Pins
on the top side of the module have an odd number while the pins on the bottom side have an
even number.
Figure 1: Pin numbering schema on the top side of the module (top view)
Pin 259Pin 143 Pin 145Pin 1

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Toradex AG l Ebenaustrasse 10 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
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Figure 2: Pin numbering schema on the bottom side of the module (bottom view)
Figure 3: Pin numbering schema on the module connector land pattern (top view)
Pin 2
Pin 146 Pin 144
Pin 260
Pin 1 Pin 143 Pin 145 Pin 259
Pin 146
Pin 144 Pin 260
Pin 2

Verdin Carrier Board Design Guide
Preliminary –Subject to Change
Toradex AG l Ebenaustrasse 10 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
Page | 15
2.2 PCI Express
The Verdin module form factor features one PCIe lane as "Reserved" interface. Depending on the
module, there may be additional lanes available in the "Module-specific" area.
2.2.1 PCIe Signals
Verdin
Pin
Verdin
Signal Name
I/O
Type
Power
Rail
Description
228
PCIE_1_CLK_P
O
PCIe
PCIe 100MHz reference clock output positive
226
PCIE_1_CLK_N
O
PCIe
PCIe 100MHz reference clock output negative
234
PCIE_1_L0_RX_P
I
PCIe
PCIe receive data positive
232
PCIE_1_L0_RX_N
I
PCIe
PCIe receive data negative
240
PCIE_1_L0_TX_P
O
PCIe
PCIe transmit data positive
238
PCIE_1_L0_TX_N
O
PCIe
PCIe transmit data negative
252
CTRL_WAKE1_MICO#
I
CMOS
1.8V
General purpose wake signal
244
PCIE_1_RESET#
O
CMOS
1.8V
Dedicated PCIe reset output
12
I2C_1_SDA
I/O
OD
1.8V
General purpose I2C interface data, optional
14
I2C_1_SCL
O
OD
1.8V
General purpose I2C interface clock, optional
Table 4: PCIe signals
The PCIe interface supports polarity inversion. This means that the positive and negative signal pins
can be inverted to simplify the layout by avoiding crossing of the signals. Some PCIe devices
support additional lane reversal for multi-lane interfaces. As the "Reserved" interfaces on Verdin
provide a single lane PCIe interface, the lane reversal feature is not relevant to the Verdin
specification. Some Verdin modules provide additional multi-lane PCIe interfaces as "Module-
specific" interfaces. Please consult the datasheets of such modules to determine if lane reversal is
applicable and supported.
2.2.2 Reference Schematics
The PCIe schematic differs depending on whether the PCIe device is soldered directly to the carrier
board (device-down) or is located on a PCIe card. Special care needs to be taken to determine as
to whether AC coupling capacitors are required. The maximum trace length of the lanes depends
on whether the design is for an external card or a device-down.
Every PCIe lane consists of a pair of transmitting (TX) and receiving (RX) traces. Unfortunately, the
names RX and TX can be confusing as the host transmitter needs to be connected to the receiver of
the device and vice versa. Normally, the signals are named from the host’s perspective until they
reach the pins of the PCIe device. Therefore, the transmitting pins of the Verdin modules should be
called TX at the carrier board while the receiving pins of the module should be called RX. Please
carefully read the datasheet of the PCIe device to make sure that RX and TX are not inadvertently
swapped.
PCIe devices need a 100MHz reference clock. It is not permitted to connect a reference clock to
two device loads. The Verdin module provides one reference clock output as a "Reserved" interface.
There may be additional PCIe reference clock outputs in the "Module-specific" area. If there are not
enough PCIe reference clocks available (e.g. if a PCIe switch is used or the PCIe interfaces in the
"Module-specific" area do not provide additional clock outputs), a zero-delay PCIe clock buffer is
required on the carrier board. Some PCIe switches feature an internal PCIe clock buffer, which can
eliminate the need for a dedicated clock buffer.

Verdin Carrier Board Design Guide
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Figure 4: PCIe reference clock buffer example
2.2.2.1 PCIe x1 Slot Connector Schematic Example
For a regular PCIe slot connector, no additional decoupling capacitors are permitted to be placed
on the carrier board in the RX, TX and reference clock lines. The decoupling capacitors are located
on the module and the PCIe card.
Figure 5: PCIe x1 Slot Connector Block Diagram
The Verdin module standard features a dedicated PCIe reset. This reset (PCIE_1_RESET#) should be
used to guarantee the power ramp up timing requirements of PCI Express. Since the PCIe slot
connector has a 3.3V logic level and the PCIE_1_RESET# output of the module is only 1.8V, a level
shifter is required. Please note that the Verdin module standard does not support PCIe hot-plug
functionality.
The PCIe x1 slot connector has two card present signals (PRSNT1#, pin A1 and PRSNT2#, pin B18)
which are shorted to ground by the card (if it is inserted). Since the Verdin standard does not
feature the PCIe hot-plug feature, these pins can be left unconnected or connected to any free
module GPIOs if the presence detection of the card needs to be emulated.
The wake output of the PCIe slot (WAKE#, pin B11) can be connected to the general wake input of
the Verdin module (CTRL_WAKE1_MICO#). Wake-up-capable PCIe cards such as Ethernet cards
can use this signal to wake up the module from the suspend state. The WAKE# signal of the PCIe
card slot is an open drain type. Therefore, no level shifter is required if the signal is pulled up to
1.8V on the carrier board, and not to 3.3V.
The JTAG interface on the PCIe slot can be left unconnected. This interface is only used for
debugging purposes. No termination on the carrier board is needed.
PCIE1_CLK_N
PCIE1_CLK_P PCIE1_CLK_N
PCIE1_CLK_P
PCIE1[0..1]
PCIE1A_CLK_N
PCIE1A_CLK_P
PCIE1B_CLK_N
PCIE1B_CLK_P
PCIE1C_CLK_N
PCIE1C_CLK_P
PCIE1A-C_CLK[0..5]
PCIE1A-C_CLK[0..5]
PCIE1_SDA
PCIE1_SCL
100nF
C2 100nF
C3 100nF
C4 100nF
C5
R1 33R
R3 33R
R5 33R
R6 33R
R7 33R
R8 33R
R10
R11R12
R13R14
R15
GND
1%
R16
475R
GND
GND
R9
1K
120R@100MHz
3A
L1
+V3.3_PCIE_CLK_BUF+V3.3
+V3.3_PCIE_CLK_BUF
C1
2.2uF
GND
100nF
C6
120R@100MHz
3A
L2
+V3.3_PCIE_CLK_BUF +V3.3_PCIE_CLK_BUF_A
+V3.3_PCIE_CLK_BUF_A
GND
+V3.3_PCIE_CLK_BUF
GND
+V3.3_PCIE_CLK_BUF
SRC_IN
2
SRC_IN#
3OE_INV 25
DIF_1 6
SRC_STOP
16
BYPASS#/PLL
12
HIGH_BW
17
PD
13
SCLK
13
SDATA
14
OE6# 21
OE1# 8
DIF_1# 7
DIF_2 9
DIF_2# 10
DIF_5 20
DIF_5# 19
DIF_6 23
DIF_6# 22
IREF 26
VDD1
1
VDD2
5
VDD3
11
VDD4
18
VDD5
24
GND
4
ICS9DB401CGLF
GNDA 27
VDDA 28
IC1
6X
49.9R
PCIE_1_CLK_N 226
PCIE_1_CLK_P 228
PCIE_1_L0_RX_N 232
PCIE_1_L0_RX_P 234
PCIE_1_L0_TX_N 238
PCIE_1_L0_TX_P 240
PCIE_1_RESET# 244
X1V
2309409-2
R20 1K
R21 1K
+V3.3_PCIE_CLK_BUF
PCIe
Device
PCIe
Host
PCIe Slot
Connector
Module
Connector
Verdin Module Carrier Board PCIe Card
TX
RX
RX
TX
PCIE_1_L0_TX_P
PCIE_1_L0_TX_N
PCIE_1_L0_RX_P
PCIE_1_L0_RX_N
PCIE_1_L0_TX_P
PCIE_1_L0_TX_N
PCIE_1_L0_RX_P
PCIE_1_L0_RX_N
2x 100nF
2x 100nF
PET0+
PET0-
PER0+
PER0-

Verdin Carrier Board Design Guide
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Toradex AG l Ebenaustrasse 10 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
Page | 17
The PCIe slot pin-out features an SMB interface for additional power management control. As the
SMB and I2C buses are compatible from a hardware perspective, it is recommended that the
general purpose I2C_1 interface of the Verdin module is used if the SMB interface is needed. Most
PCIe cards do not make use of the SMB interface though. Therefore, these pins can be left
unconnected for most applications. Please note that the SMB interface has a logic level of 3.3V
while the I2C_1 has 1.8V. Therefore, a bidirectional level shifter is required.
According to the PCIe specifications, the regular +3.3V supply rail (pin A9, A10, and B8) as well as
the +12V (pin A2, A3, B1 and B2) are required to be provided. The +3.3Vaux is optional.
However, the +3.3Vaux must be supplied to the PCIe add-in card slot if the platform supports the
wake features (WAKE#).
Not all PCIe cards need the +12V supply. For a battery powered system or a carrier board with a
wide voltage input range, it might be difficult to generate a regulated 12V rail. In this case, we
recommend checking with the PCIe card(s) manufacturer to determine if the +12V supply is
required. Please note that omitting the +12V is violating the PCI Express specifications and makes
therefore the design incompatible with some add-in cards.
Figure 6: PCIe x1 slot reference schematic
2.2.2.2 Mini PCIe Card Schematic Example
The Mini PCIe Card (also called PCI Express Mini Card, Mini PCI Express or Mini PCIe) features
beside the PCIe link an USB 2.0 high-speed interface. In order to be compliant, the carrier board
needs to provide both interfaces, the PCIe and USB. As most of the Mini PCIe Cards use only one
of its interfaces for an embedded carrier board which is developed for a restricted set of
compatible cards, it might be enough to implement only the required interface. Check with the
Mini PCIe Card vendor whether the USB, PCIe or both interfaces are used by the card.
The Mini PCIe Card features the decoupling capacitors for the RX lines on the card. Therefore, no
additional decoupling capacitors should be placed on the carrier board in either the RX, TX or
reference clock lines.
PRSNT1#
A1 +12V B1
+12V
A2 +12V B2
+12V
A3 RSVD B3
GND
A4 GND B4
TCK
A5 SMCLK B5
TDI
A6 SMDAT B6
TDO
A7 GND B7
TMS
A8 +3.3V B8
+3.3V
A9 TRST# B9
+3.3V
A10 +3.3VAux B10
PERST#
A11 WAKE# B11
GND
A12 RSVD B12
REFCLK+
A13 GND B13
REFCLK-
A14 PET0+ B14
GND
A15 PET0- B15
PER0+
A16 GND B16
PER0-
A17 PRSNT2# B17
GND
A18 GND B18
X2
GND GND
GND
GND
GND GND
GND
GND
GND
WAKE1_MICO#
I2C1_SDA
I2C1_SCL
GND
PCIE1_PRSNT2# TP1
R1
4.7K
22uF
16V
+
C2
GND
22uF
10V
+
C1
GND
I2C1[0..1]
+V3.3_SW
+V3.3_STB+V3.3_SW
+V3.3_SW
+V3.3_SW+V12_SW
PCIE1_RX_N
PCIE1_RX_P PCIE1_TX_N
PCIE1_TX_PPCIE1_CLK_N
PCIE1_CLK_P
+V12_SW
+V12_SW +V12_SW +V12_SW
PCIE1_RX_N
PCIE1_RX_P
PCIE1_TX_N
PCIE1_TX_P
PCIE1_CLK_N
PCIE1_CLK_P
PCIE1[0..5]
I2C1_SDA
I2C1_SCL
PCIE1_SMDAT
PCIE1_SMCLK 0RR2 0RR3
Optional
R4
4.7K
PCIE_1_CLK_N 226
PCIE_1_CLK_P 228
PCIE_1_L0_RX_N 232
PCIE_1_L0_RX_P 234
PCIE_1_L0_TX_N 238
PCIE_1_L0_TX_P 240
PCIE_1_RESET# 244
X1V
2309409-2
I2C_1_SDA 12
I2C_1_SCL 14
X1M
2309409-2
CTRL_RECOVERY_MICO# 246
CTRL_PWR_BTN_MICO# 248
CTRL_FORCE_OFF_MOCI# 250
CTRL_WAKE1_MICO# 252
CTRL_PWR_EN_MOCI 254
CTRL_SLEEP_MOCI# 256
CTRL_RESET_MOCI# 258
CTRL_RESET_MICO# 260
X1W
2309409-2
GNDGNDGND
2
16
NTZD3154NT1G
T9A
3
5
4
NTZD3154NT1G
T9B
R82
100K
R84
100K
R83
10K
+V3.3_SW
100nF
16V
C98
GND
+V1.8
100nF
16V
C99
GND
FXMA2102L8X
GND
4
VCCA
1
A0
2
OE
5
A1
3B1 6
B0 7
VCCB 8
IC2 +V3.3_SW
+V1.8 +V1.8
R85
1.8K R86 1.8K
+V3.3_SW
R143
1.8K R144 1.8K
+V1.8
+V3.3_SW
PCIE1_RESET#_3.3V
+V1.8

Verdin Carrier Board Design Guide
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Page | 18
Figure 7: Mini PCIe Card Block Diagram
The Verdin module standard features a dedicated PCIe reset. This reset (PCIE_1_RESET#) should be
used in order to guarantee the power ramp up timing requirements of PCI Express. Since the Mini
PCIe card has a 3.3V logic level for the reset input (PERST#, pin 22) and the PCIE_1_RESET# output
of the module is only 1.8V, a level shifter is required. Please note that the in the Verdin module
standard does not support PCIe hot-plug functionality.
The clock request output of the card (CLKREQ#, Pin 7) can be left unconnected. It might also be
connected to a free GPIO on the Verdin module. In this case, the clock request functionality needs
to be implemented in software.
The wake output of the Mini PCIe Card (WAKE#, pin 1) can be connected to the generic wake
input of the Verdin module (CTRL_WAKE1_MICO#). Wake-up-capable Mini PCIe Cards such as
Ethernet cards can use this signal to wake up the module from the suspend state. The WAKE#
signal of the Mini PCIe Cards slot is an open drain type. Therefore, no level shifter is required if the
signal is pulled up to 1.8V on the carrier board, and not to 3.3V.
The R-UIM interface of the Mini PCIe Card (UIM, pin 8, 10, 12, 14 and 16) are only needed for
mobile broadband modem cards such as 3G and 4G cards. If the card interface needs to support
such modems, an additional SIM card holder needs to be attached to this interface.
The Mini PCIe Card pin-out features an SMB interface for additional power management control.
As the SMB and I2C buses are compatible from a hardware perspective, it is recommended that
the general purpose I2C_1 interface on the Verdin module is used if the SMB interface is needed.
Most Mini PCIe Card do not make use of the SMB interface though. Therefore, these pins can be
left unconnected for most applications. Please note that the SMB interface has a logic level of 3.3V
while the I2C_1 has 1.8V. Therefore, a bidirectional level shifter is required.
PCIe
Device
PCIe
Host
Verdin Module Carrier Board PCIe Mini Card
TX
RX
RX
TX
PET0+
PET0-
PER0+
PER0-
2x 100nF
2x 100nF
USB_x_D_P
USB_x_D_N
USB_x_D_P
USB_x_D_N
USB_D+
USB_D-
PCIe Mini Card
Connector
Module
Connector
USB
Device
USB
Host
PCIE_1_L0_TX_P
PCIE_1_L0_TX_N
PCIE_1_L0_RX_P
PCIE_1_L0_RX_N
PCIE_1_L0_TX_P
PCIE_1_L0_TX_N
PCIE_1_L0_RX_P
PCIE_1_L0_RX_N

Verdin Carrier Board Design Guide
Preliminary –Subject to Change
Toradex AG l Ebenaustrasse 10 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
Page | 19
Figure 8: Mini PCIe card reference schematic
Mini PCIe Latch
MECH1
67910-5700
WAKE#
1
3V3 2
COEX1
3
GND 4
COEX2
5
1V5 6
CLKREQ#
7
UIM_PWR 8
GND 9
UIM_DATA 10
REF_CLK-
11
REF_CLK+
13
GND 15
SIM_C8/RSVD 17
SIM_C4/RSVD 19
GND 21
PCIe_RX-
23
PCIe_RX+
25
GND 27
GND 29
PCIe_TX-
31
PCIe_TX+
33
GND 35
GND 37
RSVD
39
RSVD
41
GND 43
RSVD
45
RSVD
47
RSVD
49
RSVD
51
UIM_CLOCK 12
UIM_RESET 14
UIM_VPP 16
GND 18
W_DISABLE#
20
PERST#
22
3V3_AUX 24
GND 26
1V5 28
SMB_CLK
30
SMB_DAT
32
GND 34
USB_D-
36
USB_D+
38
GND 40
LED_WWAN# 42
LED_WLAN# 44
LED_WPAN# 46
1V5 48
GND 50
3V3 52
X2
7111S2015X02LF
VCC
1
RESET
2
CLOCK
3
GND
5
VPP
6
I/O
7
X3
SC4215A
NC
1
EN
2V_IN
3
NC
4
NC
5
V_OUT 6
FB 7
GND 8
GND_PAD 9
IC1
GND
10uF
10V
C2
GND
R10
20K
R9
40.2K
10uF
10V
C3 100nF
16V
C1
GND
+V1.5
10uF
10V
C4
GND
33R@100MHz
3A
L1
10uF
10V
C5
GND
PCIE1_UIM_PWR
PCIE1_UIM_RESET
PCIE1_UIM_CLK
PCIE1_UIM_VPP
PCIE1_UIM_DATA
GND
RESET_MOCI#
WAKE1_MICO#
PCIE1_SMDAT
PCIE1_SMCLK0RR2 0RR3I2C1_SDA
I2C1_SCL
GND PCIE1_WDISABLE#
+V3.3_PCIE +V1.5
LED1
LED2
LED3
150R
R6
150R
R7
150R
R8
+V3.3_SW
PCIE1_WWLAN#
PCIE1_WLAN#
PCIE1_WPAN#
USBH_D_P
USBH_D_N
USBH[0..1]
+V3.3_SW
+V3.3_SW+V3.3_SW
PCIE1_RX_N
PCIE1_RX_P
PCIE1_CLK_N
PCIE1_CLK_P
PCIE1_TX_N
PCIE1_TX_P
PCIE_FB
R1
47K
3.3V_STB
+V3.3_PCIE
+V3.3_PCIE
Power
+V1.5
+V1.5
+V3.3_PCIE
+V3.3_PCIE
USBH_D_P
USBH_D_N
Optional
JP1
PCIE1_RX_N
PCIE1_RX_P
PCIE1_TX_N
PCIE1_TX_P
PCIE1_CLK_N
PCIE1_CLK_P
PCIE_1_CLK_N 226
PCIE_1_CLK_P 228
PCIE_1_L0_RX_N 232
PCIE_1_L0_RX_P 234
PCIE_1_L0_TX_N 238
PCIE_1_L0_TX_P 240
PCIE_1_RESET# 244
X1V
2309409-2
I2C_1_SDA 12
I2C_1_SCL 14
X1M
2309409-2
CTRL_RECOVERY_MICO# 246
CTRL_PWR_BTN_MICO# 248
CTRL_FORCE_OFF_MOCI# 250
CTRL_WAKE1_MICO# 252
CTRL_PWR_EN_MOCI 254
CTRL_SLEEP_MOCI# 256
CTRL_RESET_MOCI# 258
CTRL_RESET_MICO# 260
X1W
2309409-2
GNDGNDGND
2
16
NTZD3154NT1G
T10A
3
5
4
NTZD3154NT1G
T10B
R149
100K
R151
100K
R150
10K
+V3.3_SW
100nF
16V
C100
GND
+V1.8
100nF
16V
C101
GND
FXMA2102L8X
GND
4
VCCA
1
A0
2
OE
5
A1
3B1 6
B0 7
VCCB 8
IC16 +V3.3_SW
+V1.8 +V1.8
R145
1.8K R146 1.8K
+V3.3_SW
R147
1.8K R148 1.8K
+V1.8
+V3.3_SW
R152
4.7K
+V1.8
USB_1_EN 155
USB_1_OC# 157
USB_1_VBUS 159
USB_1_D_N 163
USB_1_D_P 165
USB_1_ID 161
USB_2_SSTX_N 169
USB_2_SSTX_P 171
USB_2_SSRX_N 175
USB_2_SSRX_P 177
USB_2_D_N 181
USB_2_D_P 183
USB_2_EN 185
USB_2_OC# 187
X1H
2309409-2

Verdin Carrier Board Design Guide
Preliminary –Subject to Change
Toradex AG l Ebenaustrasse 10 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
Page | 20
2.2.2.3 PCIe x1 Device-Down Schematic Example
Device-Down means that the PCIe device is soldered directly to the carrier board. The decoupling
capacitors for the RX lanes (TX from the device) need to be placed on the carrier board. As the
capacitors for the TX lanes are located on the Verdin module, no additional capacitors should be
place on the TX lines. The reference clock lines do not need decoupling capacitors.
Figure 9: PCIe Device-Down block diagram
The schematic diagram shown below is an example of a device-down design of a gigabit Ethernet
controller. Please be aware that the TX lane from the module needs to be connected to the RX
input of the controller. The RX lane from the module needs to be connected to the TX output of the
controller. Check your device carefully to determine whether it needs this crossing or not.
Figure 10: PCIe Device-Down example schematic
PCIe
Device
(down)
PCIe
Host
Module
Connector
Verdin Module Carrier Board
TX
RX
RX
TX
PCIE_RX+
PCIE_RX-
PCIE_TX+
PCIE_TX-
2x 100nF
2x 100nF
PCIE_1_L0_TX_P
PCIE_1_L0_TX_N
PCIE_1_L0_RX_P
PCIE_1_L0_RX_N
PCIE_1_L0_TX_P
PCIE_1_L0_TX_N
PCIE_1_L0_RX_P
PCIE_1_L0_RX_N
ETH1[0..9]
0RR4 0RR3 ETH1_SDA
ETH1_SCL
I2C1_SCL
I2C1_SDA
I210
VDD3P3_1
10
VDD3P3_2
27
VDD3P3_3
41
VDD3P3_4
51
VDD3P3_5
64
VDD1P5_1
47
VDD1P5_2
56
VDD0P9_1
11
VDD0P9_2
32
VDD0P9_3
42
VDD0P9_4
59
RSVD_22_NC
22
VDD1P5_OUT 39
VDD0P9_OUT 40
CTOP 40
CBOT 37
GND HS
IC1B
PCIE1_RX_S_N
PCIE1_RX_S_P
PCIE1_TX_N
PCIE1_TX_P
PCIE1_CLK_N
PCIE1_CLK_P
PCIE1[0..5]
100nF
C1
100nF
C2
PCIE1_RX_N
PCIE1_RX_P
Optional
RESET_MOCI#
WAKE1_MICO#
I210
PE_RX_P
24
PE_CLK_P
26
PE_CLK_N
25
JTAG_TCK
19
JTAG_TDO
4
JTAG_TMS
18
JTAG_TDI
29
SMB_DATA
36 SMB_CLK
34
PE_TX_P
21
PE_TX_N
20
SDP0
63
XTAL_1
46
MDI_0_P 58
PE_RX_N
23
PE_RST#
17
PE_WAKE#
16
DEV_OFF#
28
LAN_PWR_GOOD
1
SMB_ALERT#
35
SDP1/PCIE_DIS
61
SDP2
62
SDP3
60
XTAL_2
45
MDI_0_N 57
MDI_1_N 54
MDI_1_P 55
MDI_2_N 52
MDI_2_P 53
MDI_3_N 49
MDI_3_P 50
NVM_CS# 15
NVM_SK 13
NVM_SI 12
NVM_SO 14
LED0 31
LED1 30
LED2 33
NC_SI_TXD0 9
NC_SI_TXD1 8
NC_SI_RXD0 6
NC_SI_RXD1 5
NC_SI_ARB_IN 43
NC_SI_ARB_OUT 44
NC_SI_CLK_IN 2
NC_SI_CRS_DV 3
NC_SI_TX_EN 7
RSET 48
IC1A
R1 10K
R2 10K
R5 10K
+V3.3_SW
R7 10K
GND
R14 10R
25.0000 MHz - 22pF -50ESR
1 2
OSC133pF 25V
C433pF
25V
C3
GNDGND
R13 10K
R12 10K
R11 10K
R15 4.99K
GND
R10 10K
R9 10K
R8 10K
R6 10K
+V3.3_SW
ETH1_MDI0_N
ETH1_MDI1_P
ETH1_MDI1_N
ETH1_MDI2_P
ETH1_MDI2_N
ETH1_MDI3_P
ETH1_MDI3_N
ETH1_MDI0_P
ETH1_ACT
ETH1_LINK
10uF
C6 100nF C7 100nF C8 100nF C9 100nF C10
47uF
C5
+V3.3_SW
+V3.3_SW
+V3.3_SW
GND
10uF
C13
100nF
C14
100nF
C15
100nF
C16
100nF
C17
GND
+V1.5_LAN
10uF
C18 100nF C19 100nF C20 100nF C21 100nF C22
GND
+V0.9_LAN
100nF
C24
GND
NA
39nF
25V
C23
10uF
C12
GND
+V1.5_LAN
+V0.9_LAN
10uF
C11
GND
GND
ETH1[0..9]
PCIE1_RX_N
PCIE1_RX_P
PCIE1_TX_N
PCIE1_TX_P
PCIE1_CLK_N
PCIE1_CLK_P
PCIE_1_CLK_N 226
PCIE_1_CLK_P 228
PCIE_1_L0_RX_N 232
PCIE_1_L0_RX_P 234
PCIE_1_L0_TX_N 238
PCIE_1_L0_TX_P 240
PCIE_1_RESET# 244
X1V
2309409-2
I2C_1_SDA 12
I2C_1_SCL 14
X1M
2309409-2
CTRL_RECOVERY_MICO# 246
CTRL_PWR_BTN_MICO# 248
CTRL_FORCE_OFF_MOCI# 250
CTRL_WAKE1_MICO# 252
CTRL_PWR_EN_MOCI 254
CTRL_SLEEP_MOCI# 256
CTRL_RESET_MOCI# 258
CTRL_RESET_MICO# 260
X1W
2309409-2
GNDGNDGND
2
16
NTZD3154NT1G
T11A
3
5
4
NTZD3154NT1G
T11B
R153
100K
R155
100K
R154
10K
+V3.3_SW
100nF
16V
C102
GND
+V1.8
100nF
16V
C103
GND
FXMA2102L8X
GND
4
VCCA
1
A0
2
OE
5
A1
3B1 6
B0 7
VCCB 8
IC19 +V3.3_SW
+V1.8 +V1.8
R161
1.8K R162 1.8K
+V3.3_SW
R159
1.8K R160 1.8K
+V1.8
+V3.3_SW
R158
4.7K
+V1.8
+V3.3_SW