Toradex Verdin User manual

Verdin Computer Module
Carrier Board Design Guide

Verdin Carrier Board Design Guide
Preliminary –Subject to Change
Toradex AG l Ebenaustrasse 10 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
Page | 2
Issued by:
Toradex
Document Type:
Carrier Board Design Guide
Purpose:
This document is a guideline for developing a carrier board that conforms to the
specifications for the Verdin Computer Module
Document
Version:
0.94
Revision History
Date
Version
Remarks
June 30, 2020
V0.9
Initial Release: Preliminary Version
October 16, 2020
V0.91
Correct position of standoff holes in carrier board land pattern drawing (Figure 92)
Remove additional notches from the drawings of the module
October 28, 2020
V0.92
Correction of CTRL_SLEEP_MOCI# signal type from open drain to CMOS
Correction of standoff hole position in Figure 3
Section 2.6: add information to DSI display adapters
January 5, 2021
V0.93
Replace front picture
Section 2.5.2.2: Change HDMI ESD protection IC in reference schematic
February 5, 2021
V0.94
Add section 3.5 Backfeeding
Section 2.2.2.3: Update figure 10
Section 2.3.2.2: Update figure 15
Section 2.5.2.1: Update figure 28
Section 2.7.2: Update figure 36

Verdin Carrier Board Design Guide
Preliminary –Subject to Change
Toradex AG l Ebenaustrasse 10 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
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Contents
1Introduction................................................................................................................... 6
1.1 Overview........................................................................................................................ 6
1.2 Additional Documents...................................................................................................... 6
1.2.1 Layout Design Guide............................................................................................. 6
1.2.2 Verdin Module Datasheets ..................................................................................... 6
1.2.3 Verdin Module Definition........................................................................................ 6
1.2.4 Toradex Developer Center..................................................................................... 6
1.2.5 Verdin Reference Designs...................................................................................... 7
1.2.6 Pinout Designer .................................................................................................... 7
1.3 Abbreviations.................................................................................................................. 7
2Interfaces.................................................................................................................... 10
2.1 Architecture.................................................................................................................. 10
2.1.1 "Always Compatible" Interfaces............................................................................. 11
2.1.2 "Reserved" Interfaces.......................................................................................... 12
2.1.3 "Module-specific" Interfaces.................................................................................. 13
2.1.4 Pin Numbering.................................................................................................... 13
2.2 PCI Express ................................................................................................................. 15
2.2.1 PCIe Signals....................................................................................................... 15
2.2.2 Reference Schematics......................................................................................... 15
2.2.3 Unused PCIe Signals Termination......................................................................... 21
2.3 Ethernet....................................................................................................................... 21
2.3.1 Media Dependent Ethernet Port............................................................................ 21
2.3.2 Reduced Gigabit Media-Independent Interface Ethernet Port.................................... 24
2.4 USB............................................................................................................................. 25
2.4.1 USB Signals....................................................................................................... 26
2.4.2 Reference Schematics......................................................................................... 27
2.4.3 Unused USB Signal Termination........................................................................... 32
2.5 HDMI/DVI..................................................................................................................... 33
2.5.1 HDMI/DVI Signals............................................................................................... 33
2.5.2 Reference Schematics......................................................................................... 33
2.5.3 Unused HDMI/DVI Signal Termination................................................................... 35
2.6 Display Serial Interface (MIPI DSI) .................................................................................. 35
2.6.1 MIPI DSI Signals................................................................................................. 36
2.6.2 Reference Schematics......................................................................................... 36
2.6.3 MIPI DSI Display Adapters................................................................................... 39
2.6.4 Unused MIPI DSI Signal Termination..................................................................... 42
2.7 Camera Serial Interface (MIPI CSI-2)............................................................................... 42
2.7.1 MIPI CSI-2 Signals.............................................................................................. 43
2.7.2 Reference Schematics......................................................................................... 43
2.8 SD/MMC/SDIO.............................................................................................................. 44
2.8.1 SD/MMC/SDIO Signals........................................................................................ 44
2.8.2 Reference Schematics......................................................................................... 44
2.8.3 Unused SD/MMC/SDIO Interface Signal Termination .............................................. 45
2.9 I2C............................................................................................................................... 45
2.9.1 I2C Signals ......................................................................................................... 46
2.9.2 Reference Schematics......................................................................................... 46
2.9.3 Unused I2C Signal Termination............................................................................. 46
2.10 UART........................................................................................................................... 46
2.10.1 UART Signals.................................................................................................. 47
2.10.2 Reference Schematics...................................................................................... 47
2.10.3 Unused UART Signal Termination...................................................................... 49
2.11 SPI.............................................................................................................................. 49
2.11.1 SPI Signals..................................................................................................... 50

Verdin Carrier Board Design Guide
Preliminary –Subject to Change
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2.11.2 Unused SPI Signal Termination......................................................................... 50
2.12 Quad Serial Peripheral Interface (Quad SPI)..................................................................... 50
2.12.1 Quad SPI Signals............................................................................................. 50
2.12.2 Unused Quad SPI Signal Termination ................................................................ 50
2.13 CAN ............................................................................................................................ 51
2.13.1 CAN Signals.................................................................................................... 51
2.13.2 Reference Schematics...................................................................................... 51
2.13.3 Unused CAN Interface Signal Termination.......................................................... 51
2.14 PWM ........................................................................................................................... 52
2.14.1 PWM Signals................................................................................................... 52
2.14.2 Reference Schematics...................................................................................... 52
2.14.3 Unused PWM Signal Termination ...................................................................... 52
2.15 Inter-IC Sound (I2S)....................................................................................................... 53
2.15.1 Digital Audio Signals ........................................................................................ 53
2.15.2 Reference Schematics...................................................................................... 54
2.15.3 Unused Digital Audio Interface Signal Termination............................................... 54
2.16 Analog Inputs................................................................................................................ 54
2.16.1 Analog Input Signals ........................................................................................ 54
2.16.2 Unused Analog Inputs Signal Termination........................................................... 54
2.17 General Purpose Clock Outputs...................................................................................... 55
2.17.1 Clock Output Signals........................................................................................ 55
2.17.2 Schematic and Layout Considerations................................................................ 55
2.17.3 Unused Clock Output Signal Termination............................................................ 55
2.18 GPIO........................................................................................................................... 55
2.18.1 GPIO Signals .................................................................................................. 55
2.18.2 Unused GPIO Termination................................................................................ 56
2.19 JTAG interface.............................................................................................................. 56
2.19.1 JTAG Signals.................................................................................................. 56
2.19.2 Reference Schematics...................................................................................... 56
2.19.3 Unused JTAG Signal Termination...................................................................... 57
2.20 Module Recovery .......................................................................................................... 57
2.20.1 Recovery Signals............................................................................................. 57
2.20.2 Reference Schematics...................................................................................... 57
2.20.3 Unused Recovery Signal Termination................................................................. 58
3Power Management..................................................................................................... 59
3.1 Power Signals............................................................................................................... 59
3.1.1 Power Supply Signals.......................................................................................... 59
3.1.2 Power Management Signals................................................................................. 59
3.2 Module Power States..................................................................................................... 60
3.3 General Power Sequences............................................................................................. 62
3.3.1 “No VCC” to “Running” (startup)............................................................................ 62
3.3.2 “Running” to “Reset” (reset).................................................................................. 63
3.3.3 “Reset” to “Running” (startup after reset)................................................................ 64
3.3.4 “Running” to “Sleep” (sleep).................................................................................. 65
3.3.5 “Sleep” to “Running” (wake).................................................................................. 66
3.3.6 “Running” to “Module OFF” (shutdown).................................................................. 67
3.3.7 “Running” to “No VCC” (force off) .......................................................................... 68
3.3.8 “Module OFF” to “Running” (startup after shutdown) ................................................ 69
3.3.9 “Module OFF” to “No VCC” (power off after shutdown)............................................. 70
3.3.10 Remove VCC in any power state ....................................................................... 70
3.4 Power Supply Use Cases............................................................................................... 71
3.4.1 Switched VCC Approach (Verdin Development Board)............................................ 71
3.4.2 Minimalist Carrier Board Power Approach.............................................................. 74
3.4.3 Single Cell Battery Power Approach...................................................................... 77
3.5 Backfeeding.................................................................................................................. 79
3.5.1 Introduction ........................................................................................................ 79
3.5.2 What is Backfeeding............................................................................................ 80

Verdin Carrier Board Design Guide
Preliminary –Subject to Change
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3.5.3 Potential Issues Caused by Backfeeding................................................................ 82
3.5.4 Identify Backfeeding Issues.................................................................................. 83
3.5.5 Backfeeding Prevention....................................................................................... 86
4Mechanical and Thermal Consideration........................................................................ 95
4.1 Module Connector and Stacking Height ........................................................................... 95
4.2 Fixation of the Module.................................................................................................... 96
4.3 Thermal Solution........................................................................................................... 96
4.4 Module Dimensions....................................................................................................... 97
4.5 Connector and Standoff Land Pattern Requirements ......................................................... 97
4.6 Carrier Board Space Requirements................................................................................. 98
5Appendix A –Module Top Side Signal Definition.......................................................... 99
6Appendix B –Module Bottom Side Signal Definition................................................... 103
7Appendix C - Physical Pin Definition and Location ..................................................... 107

Verdin Carrier Board Design Guide
Preliminary –Subject to Change
Toradex AG l Ebenaustrasse 10 l 6048 Horw l Switzerland l [phone] l www.toradex.com l [e-mail]
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1 Introduction
1.1 Overview
This document guides users through the development of a customized carrier board for the Verdin
System-on-Module (SoM) family. It describes the different interfaces of those modules and provides
reference schematics as well. The document highlights standardized features of Verdin SoMs
(compatible between different modules). "Module-specific" interfaces, features and alternate
functions are not detailed in this document. These interfaces are detailed in the respective
datasheets of Verdin SoMs. Some Verdin modules do not feature the full set of the "Reserved"
interfaces. It is strongly recommended to always read the datasheet of the module that is intended
to be used with and off-the-shelf or a custom carrier board.
Verdin modules feature new high-speed interfaces such as PCI Express, HDMI, MIPI CSI and DSI
which require special layout considerations regarding trace impedance and length matching.
Please read carefully the Toradex Layout Design Guide for additional information on the routing of
these interfaces.
1.2 Additional Documents
1.2.1 Layout Design Guide
This document contains layout requirement specifications for high-speed signals and helps to avoid
issues related to layout.
https://developer.toradex.com/carrier-board-design
1.2.2 Verdin Module Datasheets
For every Verdin Module, there is a datasheet available. Among other things, this document
describes the "Module-specific" interfaces and secondary functionalities of pins. Before starting the
development of a customized carrier board, please check these documents to verify if the required
interfaces are available on the selected modules.
https://www.toradex.com/computer-on-modules/verdin-arm-family
1.2.3 Verdin Module Definition
This document describes the Verdin Module standard. It provides information on the mechanical
and electrical properties of Verdin modules, in addition to functionalities and interfaces provided
by those modules.
The document is available soon.
1.2.4 Toradex Developer Center
You can find a lot of additional information in the Toradex Developer Center, which is updated
with the latest product support information on a regular basis.
Please note that the Developer Center is common for all Toradex products. You should always
check to ensure if information is valid or relevant to the Verdin modules.
https://developer.toradex.com/

Verdin Carrier Board Design Guide
Preliminary –Subject to Change
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1.2.5 Verdin Reference Designs
Schematic files, assembly drawings, bills of material and the complete Altium project files for the
Verdin reference carrier boards are available for download for free. There is also an online viewer
available which is convenient to use for customers without a license for Altium.
https://developer.toradex.com/carrier-board-design/reference-designs
1.2.6 Pinout Designer
The Toradex Pinout Designer is a powerful tool for evaluating different pin multiplexing options for
Verdin, Apalis, and Colibri Modules. Defining the pin multiplexing configuration to use or design
for is a vital step in the process of designing a custom carrier board.
The tool allows comparing interfaces across different modules as well.
http://developer.toradex.com/knowledge-base/pinout-designer
1.3 Abbreviations
Abbreviation
Explanation
ADC
Analog to Digital Converter
AGND
Analog Ground, separate ground for analog signals
Auto-MDIX
Automatically Medium Dependent Interface Crossing, a PHY with Auto-MDIX can detect whether RX and
TX need to be crossed (MDI or MDIX)
BSP
Board Support Package
CAD
Computer-Aided Design, in this document is referred to PCB Layout tools
CAN
Controller Area Network, a bus that is manly used in automotive and industrial environment
CAN FD
Controller Area Network Flexible Data-Rate, an extension to the original CAN bus protocol which allows
higher data rates and larger message sizes.
CEC
Consumer Electronic Control, HDMI feature that allows to control CEC compatible devices
CPU
Central Processor Unit
CSI
Camera Serial Interface
DAC
Digital to Analog Converter
DDC
Display Data Channel, interface for reading out the capability of a monitor, in this document DDC2B
(based on I2C) is always meant
DFP
Downstream Facing Port, USB Type-C port that acts as a host
DRC
Design Rule Check, a tool for checking whether all design rules are satisfied in a CAD tool
DRD
Dual-Role Data, USB Type-C port that can act as host or device
DRP
Dual-Role Port, USB Type-C port that can operate as power sink and source
DSI
Display Serial Interface
DVI
Digital Visual Interface, digital signals are electrical compatible with HDMI
DVI-A
Digital Visual Interface Analog only, signals are compatible with VGA
DVI-D
Digital Visual Interface Digital only, signals are electrical compatible with HDMI
DVI-I
Digital Visual Interface Integrated, combines digital and analog video signals in one connector
EDA
Electronic Design Automation, software for schematic capture and PCB layout (CAD or ECAD)
EDID
Extended Display Identification Data, timing setting information provided by the display in a PROM
EMI
Electromagnetic Interference, high frequency disturbances
eMMC
Embedded Multi Media Card, flash memory combined with MMC interface controller in a BGA package,
used as internal flash memory
ESD
Electrostatic Discharge, high voltage spike or spark that can damage electrostatic- sensitive devices
FPD-Link
Flat Panel Display Link, high-speed serial interface for liquid crystal displays. In this document also called
LVDS interface.
GBE
Gigabit Ethernet, Ethernet interface with a maximum data rate of 1000Mbit/s
GMII
Gigabit Media-Independent Interface, interface between Ethernet MAC and PHY for up to 1Gb/s

Verdin Carrier Board Design Guide
Preliminary –Subject to Change
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Abbreviation
Explanation
GND
Ground
GPI
General Purpose Input
GPIO
General Purpose Input/Output, pin that can be configured being an input or output
GPO
General Purpose Output
GSM
Global System for Mobile Communications
HDA
High Definition Audio (HD Audio), digital audio interface between CPU and audio codec
HDCP
High-Bandwidth Digital content Protection, copy protection system that is used by HDMI beside others
HDMI
High-Definition Multimedia Interface, combines audio and video signal for connecting monitors, TV sets or
Projectors, electrical compatible with DVI-D
I2C
Inter-Integrated Circuit, two-wire interface for connecting low-speed peripherals
I2S
Integrated Interchip Sound, serial bus for connecting PCM audio data between two devices
IrDA
Infrared Data Association, infrared interface for connecting peripherals
JTAG
Joint Test Action Group, widely used debug interface
LCD
Liquid Crystal Display
LSB
Least Significant Bit
LVDS
Low-Voltage Differential Signaling, electrical interface standard that can transport high-speed signals over
twisted-pair cables. Many interfaces like PCIe or SATA use this interface. Since the first successful
application was the Flat Panel Display Link, LVDS became a synonymous for this interface. In this
document, the term LVDS is used for the FPD-Link interface.
MAC
Medium Access Control, is part of the second layer (data link layer) in the Ethernet stack
MII
Media-Independent Interface, interface between Ethernet MAC and PHY for up to 100Mb/s
MIPI
Mobile Industry Processor Interface Alliance
MDI
Medium Dependent Interface, physical interface between Ethernet PHY and cable connector
MDIO
Management Data Input/Output, an interface that is used for controlling the Ethernet PHY. The bus
consists of the MDC clock and the MDIO bidirectional data signal.
MDIX
Medium Dependent Interface Crossed, an MDI interface with crossed RX and TX interfaces
mini PCIe
PCI Express Mini Card, card form factor for internal peripherals. The interface features PCIe and USB 2.0
connectivity
MMC
MultiMediaCard, flash memory card
MSB
Most Significant Bit
mSATA
Mini-SATA, a standardized form factor for small solid-state drive, similar dimensions as mini PCIe
MXM3
Mobile PCI Express Module (second generation), graphic card standard for mobile device, the Apalis form
factor uses the physical connector but not the pin-out and the PCB dimensions of the MXM3 standard.
N/A
Not Available
N/C
Not Connected
OD
Open Drain
OTG
USB On-The-Go, a USB host interface that can also act as USB client when connected to another host
interface
OWR
One Wire (1-Wire), low-speed interface which needs just one data wire plus ground
PCB
Printed Circuit Board
PCI
Peripheral Component Interconnect, parallel computer expansion bus for connecting peripherals
PCIe
PCI Express, high-speed serial computer expansion bus, replaces the PCI bus
PCM
Pulse-Code Modulation, digitally representation of analog signals, standard interface for digital audio
PD
Pull-Down Resistor
PHY
Physical Layer of the OSI model
PMIC
Power Management IC, integrated circuit that manages amongst others the power sequence of a system
PU
Pull-up Resistor
PWM
Pulse-Width Modulation
QSPI
Quad SPI, SPI interface with four bidirectional data signals
RGB
Red Green Blue, color channels in common display interfaces
RGMII
Reduced Gigabit Media-Independent Interface, interface between Ethernet MAC and PHY for up to 1Gb/s
RJ45
Registered Jack, common name for the 8P8C modular connector that is used for Ethernet wiring
RMII
Reduced Media-Independent Interface, interface between Ethernet MAC and PHY for up to 100Mb/s

Verdin Carrier Board Design Guide
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Abbreviation
Explanation
RS232
Single ended serial port interface
RS422
Differential signaling serial port interface, full duplex
RS485
Differential signaling serial port interface, half duplex, multi drop configuration possible
R-UIM
Removable User Identity Module, identifications card for CDMA phones and networks, an extension of the
GSM SIM card
S/PDIF
Sony/Philips Digital Interconnect Format, optical or coaxial interface for audio signals
SATA
Serial ATA, high-speed differential signaling interface for hard drives and SSD
SD
Secure Digital, flash memory card
SDIO
Secure Digital Input Output, an external bus for peripherals that uses the SD interface
SIM
Subscriber Identification Module, identification card for GSM phones
SMBus
System Management Bus (SMB), two wire bus based on the I2C specifications, used specially in x86
design for system management.
SoC
System on a Chip, IC which integrates the main component of a computer on a single chip
SPI
Serial Peripheral Interface Bus, synchronous four wire full duplex bus for peripherals
TIM
Thermal Interface Material, thermal conductive material between CPU and heat spreader or heat sink
TMDS
Transition-Minimized Differential Signaling, serial high-speed transmitting technology that is used by DVI
and HDMI
TVS Diode
Transient-Voltage-Suppression Diode, diode that is used to protect interfaces against voltage spikes
UFP
Upstream Facing Port, USB Type-C port that acts as a client
UART
Universal Asynchronous Receiver/Transmitter, serial interface, in combination with a transceiver a RS232,
RS422, RS485, IrDA or similar interface can be achieved
USB
Universal Serial Bus, serial interface for internal and external peripherals
VCC
Positive supply voltage
VGA
Video Graphics Array, analog video interface for monitors
Table 1: Abbreviations

Verdin Carrier Board Design Guide
Preliminary –Subject to Change
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2 Interfaces
2.1 Architecture
The block diagram in Figure 1 shows the basic architecture of the Verdin module, depicting the
“Always Compatible”interfaces, “Reserved”interfaces, and some examples of “Module-specific”
interfaces.
1x Gigabit Ethernet
1x RGMII
1x LVDS
1x USB 2.0 OTG
1x USB 2.0 Host
1x I2C
1x SPI
3x UART (RX, TX only)
1x PWM
10x GPIO
1x SDIO
1x USB SuperSpeed Lane
1x PCIe (1x Lane)
1x HDMI
3x I2C
1x QSPI
2x UART (Extra RTS, CTS)
1x UART (RX, TX only)
2x CAN
1x MIPI DSI (4x Lanes)
1x MIPI CSI-2 (4x Lanes)
2x I2S
2x PWM
4x ADC
1x SDIO
1x MIPI CSI-2 (4x Lanes)
Verdin
Module
3.135 to 5.5V Input
System Control
RTC Backup
eMMC
M.2 1216
Wi-Fi
Bluetooth
RAM
EEPROM
RTC
Always Compatible Reserved Module-Specific (examples)