Transcend TS1~2GUSD-S3 Manual

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microSD Memory Card + Reader S3
Transcend Information Inc.
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Description
Transcend microSD card series are non-volatile,
which means no external power is required to retain
the information stored on it. Besides, it is also a
solid-state device that without moving parts to skip or
break down. Based on original NAND flash chip,
Transcend microSD can offer an incredible
combination of fast data transfer, great flexibility,
excellent security and incredibly small size.
Placement
Front Back
Features
•ROHS compliant product.
•Operating Voltage: 2.7 ~ 3.6V
•Operating Temperature: -25 ~ 85°C
•Durability: 10,000 insertion/removal cycles
•Fully compatible with SD card spec. v1.1
•Comply with SD Association File System Specification
•Mechanical Write Protection Switch with microSD adapter
•SD Host allows MultiMediaCard upward compatibility
•Form Factor: 11mm x 15mm x 1mm
1 2 3 4 5 6 7 8
Pin Definition
SD Mode SPI Mode
Pin No.
Name Type Description Name Type Description
1 DAT2 I/O/PP Data Line [Bit2] RSV Reserved
2 CD/DAT3 I/O/PP Card Detect / Data Line [Bit3] CS I Chip Select
3 CMD PP Command / Response DI I Data In
4 VDD S Supply voltage VDD S Supply voltage
5 CLK I Clock SCLK I Clock
6 VSS S Supply voltage ground VSS S Supply voltage ground
7 DAT0 I/O/PP Data Line [Bit0] DO O/PP Data out
8 DAT1 I/O/PP Data Line [Bit1] RSV Reserved
S: Power Supply; I:Input; O:Output; PP:Push-Pull

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Architecture

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Bus Operating Conditions
• General
Parameter Symbol Min. Max. Unit Remark
Peak voltage on all lines -0.3 VDD+0.3 V
All Inputs
Input Leakage Current -10 10 µA
All Outputs
Output Leakage Current -10 10 µA
• Power Supply Voltage
Parameter Symbol Min. Max. Unit Remark
Supply voltage VDD 2.0 3.6 V CMD0, 15,55,ACMD41
commands
Supply voltage specified in OCR register Except CMD0, 15,55,
ACMD41 commands
Supply voltage differentials (VSS1, VSS2) -0.3 0.3 V
Power up time 250 ms From 0v to VDD Min.
Note. The current consumption of any card during the power-up procedure must not exceed 10 mA.
• Bus Signal Line Load
The total capacitance CLthe CLK line of the SD Memory Card bus is the sum of the bus master capacitance CHOST, the bus
capacitance CBUS itself and the capacitance CCARD of each card connected to this line:
CL= CHOST + CBUS + Ν*CCARD
Where N is the number of connected cards. Requiring the sum of the host and bus capacitances not to exceed 30 pF for
up to 10 cards, and 40 pF for up to 30 cards, the following values must not be exceeded:
Parameter Symbol Min. Max. Unit Remark
Bus signal line capacitance CL100 pF fPP ≤ 20 MHz, 7 cards
Single card capacitance CCARD 10 pF
Maximum signal line inductance 16 nH fPP ≤ 20 MHz
Pull-up resistance inside card (pin1) RDAT3 10 90 KΩMay be used for card
detection
Note that the total capacitance of CMD and DAT lines will be consist of CHOST, CBUS and one CCARD only since they are
connected separately to the SD Memory Card host.
Parameter Symbol Min. Max. Unit Remark
Pull-up resistance RCMD, RDAT 10 100 KΩTo prevent bus floating
Bus signal line capacitance CL250 pF fPP ≤ 5 MHz, 21 cards

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• Bus Signal Levels
As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage.
To meet the requirements of the JEDEC specification JESD8-1A, the card input and output voltages shall be within the
following specified ranges for any VDD of the allowed voltage range:
Parameter Symbol Min. Max. Unit Remark
Output HIGH voltage VOH 0.75*VDD V IOH = -100 μA @VDD min
Output LOW voltage VOL 0.125*VDD V IOL = 100 μA @VDD min
Input HIGH voltage VIH 0.625*VDD VDD + 0.3 V
Input LOW voltage VIL VSS – 0.3 0.25*VDD V

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• Bus Timing
Parameter Symbol Min Max. Unit Remark
Clock CLK (All values are referred to min (VIH) and max (VIL)
Clock frequency Data Transfer Mode fPP 0 25 MHz CL≤ 100 pF, (7 cards)
Clock frequency Identification Mode
(The low freq. is required for MultiMediaCard
compatibility.)
fOD 0 400 KHz CL≤ 250 pF, (21 cards)
tWL 10 ns CL≤ 100 pF, (7 cards)Clock low time
50 ns CL≤ 250 pF, (21 cards)
tWH 10 ns CL≤ 100 pF, (7 cards)Clock high time
50 ns CL≤ 250 pF, (21 cards)
tTLH 10 ns CL≤ 100 pF, (7 cards)Clock rise time
50 ns CL≤ 250 pF, (21 cards)
tTHL 10 ns CL≤ 100 pF, (7 cards)Clock fall time
50 ns CL≤ 250 pF, (21 cards)
Inputs CMD, DAT (referenced to CLK)
Input set-up time tISU 5 ns CL≤ 25 pF, (1 cards)
Input hold time tIH 5 ns CL≤ 25 pF, (1 cards)
Outputs CMD, DAT (referenced to CLK)
Output Delay time tODLY 0 14 ns CL≤ 25 pF, (1 cards)

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Reliability and Durability
Temperature Operation: -25°C / 85°C (Target spec)
Moisture and corrosion Operation: 25°C / 95% rel. humidity
Storage: 40°C / 93% rel. hum./500h
Salt Water Spray: 3% NaCl/35C; 24h acc. MIL STD Method 1009
Durability 10000 mating cycles
Bending 10N
Torque 0.10N*m , +/- 2.5deg max
Drop test 1.5m free fall
UV light exposure UV: 254nm, 15Ws/cm² according to ISO 7816-1
Visual inspection
Shape and form
No warppage; no mold skin; complete form; no cavities surface smoothness <= -0.1
mm/cm² within contour; no cracks; no pollution (fat, oil dust, etc.)
Above technical information is based on standard data and tested to be reliable. However, Transcend makes no warranty,
either expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product.
Transcend reserves the right to make changes in specifications at any time without prior notice.

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Register Information
Within the card interface six registers are defined: OCR, CID, CSD, RCA, DSR and SCR. These can be accessed only
by corresponding commands (see Chapter 4.7). The OCR, CID, CSD and SCR registers carry the card/content specific
information, while the RCA and DSR registers are configuration registers storing actual configuration parameters.
1. OCR register
The 32-bit operation conditions register stores the VDD voltage profile of the card. In addition, this
register includes a status information bit. This status bit is set if the card power up procedure has
been finished. The OCR register shall be implemented by the cards which do not support the full
operating voltage range of the SD Memory Card bus, or if the card power up extends the definition
in the timing diagram.
A voltage range is not supported if the corresponding bit value is set to LOW. As long as the card is busy, the
corresponding bit (31) is set to LOW.

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2. CID Register
The Card IDentification (CID) register is 128 bits wide. It contains the card identification information used during the card
identification phase. Every individual flash card shall have a unique identification number. The structure of the CID
register is defined in the following paragraphs:
• MID
An 8 bit binary number that identifies the card manufacturer. The MID number is controlled, defined and allocated to a
SD Memory Card manufacturer by the SD Group. This procedure is established to ensure uniqueness of the CID
register.
• OID
A 2 ASCII string characters that identifies the card OEM and/or the card contents (when used as a distribution media
either on ROM or FLASH cards). The OID number is controlled, defined and allocated to a SD Memory Card
manufacturer by the SD Group. This procedure is established to ensure uniqueness of the CID register.
• PNM
The product name is a string, 5 ASCII characters long.
• PRV
The product revision is composed of two Binary Coded Decimal (BCD) digits, four bits each, representing an “n.m”
revision number. The “n” is the most significant nibble and “m” is the least significant nibble.
As an example, the PRV binary value field for product revision “6.2” will be: 0110 0010
• PSN
The Serial Number is 32 bits of binary number.
• MDT

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The manufacturing date composed of two hexadecimal digits, one is 8 bit representing the year(y)
and the other is four bits representing the month(m).
The “m” field [11:8] is the month code. 1 = January.
The “y” field [19:12] is the year code. 0 = 2000.
As an example, the binary value of the Date field for production date “April 2001” will be:
00000001 0100.
• CRC
CRC7 checksum (7 bits).
3. CSD Register
The Card-Specific Data register provides information on how to access the card contents. The CSD defines the data
format, error correction type, maximum data access time, whether the DSR register can be used etc. The programmable
part of the register (entries marked by W or E, see below) can be changed by CMD27. The type of the entries in the table
below is coded as follows: R= readable, W(1) = writable once, W = multiple writable.

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The following sections describe the CSD fields and the relevant data types. If not explicitly defined otherwise, all bit
strings are interpreted as binary coded numbers starting with the left bit first.
• CSD_STRUCTURE
Version number of the related CSD structure.
• TAAC
Defines the asynchronous part of the data access time.