Trenz Electronic TE0720 User manual

TE0720 User Manual
Date:
Revision:
Authors: Antti Lukats, Thorsten Trenz, Sven-Ole Voigt
0.2
26-Sep-2014 10:35

TE0720 User Manual Revision: 0.2
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Table of Contents
Overview: TE0720 GigaZee Zynq SoM _____________________________________________________ 7
Features ___________________________________________________________________________ 7
Document Change History _____________________________________________________________ 8
Overview _____________________________________________________________________________ 9
Sample Applications __________________________________________________________________ 9
Key Features ________________________________________________________________________ 9
Getting Started _______________________________________________________________________ 11
Preloaded (Factory default) SPI Flash Image ______________________________________________ 11
Boot Procedure _____________________________________________________________________ 13
FSBL (First Stage Bootloader) ______________________________________________________ 13
SSBL (Second Stage Bootloader) ____________________________________________________ 14
Boot Modes ________________________________________________________________________ 14
QSPI Boot Mode _________________________________________________________________ 15
Update the SPI Flash from an SD Card ___________________________________________ 15
Update the SPI Flash from a network ____________________________________________ 15
SD Card Boot Mode ______________________________________________________________ 17
Programming the FPGA with new Configurations ___________________________________________ 17
Configuring the FPGA via JTAG _____________________________________________________ 17
Configuring the FPGA by the Processing System (PS) ___________________________________ 17
Configuring the FPGA with U-Boot ___________________________________________________ 17
Configuring the FPGA in Linux ______________________________________________________ 18
Detailed Description ___________________________________________________________________ 19
Overview __________________________________________________________________________ 19
System Management, Power Supply & Resets _____________________________________________ 20
System Management Controller (SC) _________________________________________________ 21
Overview: System Management Controller (SC) ____________________________________ 21
Custom SC Programming _____________________________________________________ 21
SC B2B Pins _______________________________________________________________ 21
NOSEQ Pin ____________________________________________________________ 21
No Sequencing mode _______________________________________________ 22
Normal mode ______________________________________________________ 22
Normal mode with user function on NOSEQ ______________________________ 22
SC pins to the FPGA _________________________________________________________ 22
Default Mode _______________________________________________________________ 22
LED Control Status __________________________________________________________ 23
SC Demystified _____________________________________________________________ 25
SC Firmware ver 0.02 ________________________________________________________ 27
Version check __________________________________________________________ 27
Reading MAC Address ___________________________________________________ 28
SC Registers ___________________________________________________________ 28
Power Supply ___________________________________________________________________ 30
Power Supply Specifications ___________________________________________________ 30

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Power Sequencer and System Management _______________________________________ 30
Power Rails ________________________________________________________________ 30
I/O Voltages ________________________________________________________________ 31
Example Application Diagrams _________________________________________________ 31
Dual Supply Application __________________________________________________ 31
3.3V Single Supply with no Power Sequencing ________________________________ 32
XADC Power _______________________________________________________________ 32
Backup Battery ______________________________________________________________ 32
Operating with a power supply of less than 3.1V ____________________________________ 32
AC & DC Characteristics ______________________________________________________ 33
AC Characteristic _______________________________________________________ 33
DC Characteristic _______________________________________________________ 33
Ethernet PHY Power-down ________________________________________________ 33
USB PHY Power-down ___________________________________________________ 34
Resets _________________________________________________________________________ 35
Software forced Resets _______________________________________________________ 35
Peripheral Resets ____________________________________________________________ 35
SC update for TE0720-02 __________________________________________________________ 36
Board-level Components ______________________________________________________________ 38
DDR3 SDRAM ___________________________________________________________________ 39
Configuration _______________________________________________________________ 39
Manufacturer Documentation ___________________________________________________ 39
e·MMC _________________________________________________________________________ 40
Format internal eMMC Card (Linux) ______________________________________________ 40
Ethernet ________________________________________________________________________ 42
Overview: Ethernet ___________________________________________________________ 42
Cable Diagnostic and VCT _____________________________________________________ 42
Media Autodetect ____________________________________________________________ 42
Advanced PHY Features ______________________________________________________ 42
Temperature sensor _____________________________________________________ 42
PHY Connections ____________________________________________________________ 43
SGMII/Fiber ____________________________________________________________ 44
PHY LED Control ____________________________________________________________ 45
Default behavior ________________________________________________________ 45
PHY LED Demo Design __________________________________________________ 45
Testing of the LED's _____________________________________________________ 46
On-board LEDs __________________________________________________________________ 48
Overview: On-board LEDs _____________________________________________________ 48
LED1 GREEN ______________________________________________________________ 48
LED2 RED _________________________________________________________________ 48
LED3 GREEN (FPGA Done) ___________________________________________________ 48
LED Status Codes ___________________________________________________________ 48
TODO: MEMS ___________________________________________________________________ 50
RTC ___________________________________________________________________________ 51
USB ___________________________________________________________________________ 52
SPI Flash _______________________________________________________________________ 53

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Programming _______________________________________________________________ 53
__________________________________________________________________________ 53
Board-level Interfaces ________________________________________________________________ 54
Zynq SoM: Multiplexed I/O (MIO) Assignments _________________________________________ 55
MIO Bank 0 Usage ___________________________________________________________ 55
Compatibility with TE07xx series ________________________________________________ 56
I2C Peripherals __________________________________________________________________ 57
I2C Testing with U-Boot _______________________________________________________ 57
High-Speed I/O __________________________________________________________________ 58
Board-to-Board Connectors ________________________________________________________ 59
Mechanical Ratings: __________________________________________________________ 59
Manufacturer Documentation: __________________________________________________ 59
Pinout _____________________________________________________________________ 61
Connector left __________________________________________________________ 61
Connector top __________________________________________________________ 62
Connector bottom _______________________________________________________ 66
Technical Specifications ______________________________________________________________ 70
TE0720 Board Dimensions & Attributes _______________________________________________ 71
Dimensions ________________________________________________________________ 71
Power Supplies _____________________________________________________________ 73
Temperature Ranges _________________________________________________________ 73
Weight ____________________________________________________________________ 73
TE0720 Schematic _______________________________________________________________ 74
Carrier Boards for TE0720 ______________________________________________________________ 75
TE0701 Carrier Board ________________________________________________________________ 75
Configuring FMC Power Supply Voltage on TE0701 via I2C (CPLD Firmware Rev 0.1) __________ 75
Reading I2C-to-GPIO Status Register on TE0701 CPLD (CPLD Firmware Rev 0.1) _____________ 76
HDMI Interface of TE0720 on TE0701 Carrier Board _____________________________________ 78
TE0720 with TE0603 Carrier ___________________________________________________________ 79
______________________________________________________________________________ 79
Functions available with TE0603 _____________________________________________________ 79
UART Console __________________________________________________________________ 80
Carrier Board Checklist _______________________________________________________________ 81
Schematic Checklist ______________________________________________________________ 81
PCB Checklist ___________________________________________________________________ 81
Visual Check of Module placement ______________________________________________ 81
Reference Projects ____________________________________________________________________ 83
Working with Reference Projects _______________________________________________________ 84
Boot Sequence __________________________________________________________________ 84
Projects Build ___________________________________________________________________ 85
Base PlanAhead Project ______________________________________________________________ 86
Base XPS Project __________________________________________________________________ 101
FSBL - First Stage Boot Loader _______________________________________________________ 103
Vivado 2013.4 FSBL _____________________________________________________________ 103
Creating FSBL __________________________________________________________________ 105
Build Environment __________________________________________________________________ 110

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Toolchain ______________________________________________________________________ 110
CentOS Linux kernel and the U-Boot build environment __________________________________ 111
Configure CentOS Guest Operating System ______________________________________ 111
Ubuntu Linux kernel and U-Boot build environment _____________________________________ 114
U-Boot ___________________________________________________________________________ 119
Get the U-Boot Repository ________________________________________________________ 119
Build U-Boot ___________________________________________________________________ 119
U-Boot user scripting _____________________________________________________________ 120
Linux kernel 3.9 ____________________________________________________________________ 122
Get Trenz Electronic Linux Kernel Repository _________________________________________ 122
Build the Linux Kernel ____________________________________________________________ 122
Preparing boot media _______________________________________________________________ 125
SD memory card boot ____________________________________________________________ 125
QSPI Flash memory boot _________________________________________________________ 125
QSPI Flash memory map _____________________________________________________ 125
Base Vivado Project ________________________________________________________________ 127
Vivado Flow (Video and Step-by-Step Tutorial) ___________________________________________ 136
_____________________________________________________________________________ 136
Creating a Vivado Example Project for TE0720 Zynq SoC Module _________________________ 136
Video Tutorial (Vivado 2013.2) _________________________________________________ 136
Step-by-Step Tutorial (Vivado 2013.3) ___________________________________________ 136
Getting Started: Create New Vivado Project __________________________________ 137
Creating Vivado Block Design (IP Integrator) _________________________________ 142
Software Implementation: Create First Stage Boot Loader (FSBL) and "Hello World"
application project in SDK ________________________________________________ 151
Hardware Synthesis & Implementation ______________________________________ 160
Software Implementation: "Hello World 2.0" (implementing access to I2C peripherals via
Xilinx Zynq PL custom logic) ______________________________________________ 171
Debugging the "Hello World" Project _________________________________________________ 171
Video Tutorial ______________________________________________________________ 171
Step-by-Step Tutorial ________________________________________________________ 171
FPGA design without PS _____________________________________________________________ 175
Xilinx repository ____________________________________________________________________ 176
Using official Xilinx linux kernel repository with TE0720 __________________________________ 176
High speed ADC Interfacing __________________________________________________________ 178
Petalinux _________________________________________________________________________ 179
FSBL _________________________________________________________________________ 179
MAC Address handling ___________________________________________________________ 179
Debug _____________________________________________________________________________ 180
Booting U-Boot via JTAG ____________________________________________________________ 181
Booting U-Boot via JTAG _________________________________________________________ 181
Old instructions _________________________________________________________________ 181
ARM DS-5 ________________________________________________________________________ 187
Streamline _____________________________________________________________________ 191
Compile/Install _____________________________________________________________________ 192
DCC Console ______________________________________________________________________ 196

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Xilinx precompiled OCM RAM u-boot images __________________________________________ 196
Handling and usage precautions ________________________________________________________ 197
General __________________________________________________________________________ 197
Removal Instructions ________________________________________________________________ 197
Winbond 32MByte SPI Flash in 2013.4 ___________________________________________________ 199
Problem description: ________________________________________________________________ 199
Recovery Instructions: _______________________________________________________________ 200
Legal Notices _______________________________________________________________________ 201
Document Warranty _________________________________________________________________ 201
Limitation of Liability ________________________________________________________________ 201
Copyright Notice ___________________________________________________________________ 201
Technology Licenses ________________________________________________________________ 201
Environmental protection _____________________________________________________________ 201
REACH (Registration, Evaluation, Authorisation and Restriction of Chemicals) compliance statement _
202
RoHS (Restriction of Hazardous Substances) compliance statement _______________________ 202
WEEE (Waste Electrical and Electronic Equipment) _____________________________________ 202

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1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Overview: TE0720 GigaZee Zynq SoM
Figure 1: TE0720 GigaZee Zynq SoM (REV 01).
Features
1.5A, 4MHz PowerSoC DC-DC Step-Down Converter with Integrated Inductor ( )Enpirion EP53F8QI
for 1.8V Power Supply
System Controller CPLD ( ): 1,200 Macrocell CPLD with Block RAM, FlashLattice LCMXO2-1200HC
and PLL
User LED 1 (Green)
User LED 2 (Red)
32 Mbyte Quad SPI Flash memory ( )Winbond W25Q256FV
MEMS sensor ( ): 3-axis accelerometer and 3-axis magnetometerST Microelectronics LSM303DLMTR
Real Time Clock with Embedded Crystal ( ): ±5ppm AccuracyIntersil ISL12020M
1Gbyte = 2x 256Mbitx16 (32-bit wide) DDR3 Memory ( )Memphis MEM4G16D3EABG-125I
e·MMC NAND Flash ( may also be different manufacturer due toMicron MTFC4GMVEA-4M,
availability) usually 4 GByte, depends on assembly option
Xilinx Zynq-7000 System-on-Module ( ) - Processing System: Dual ARM Cortex-A9,Xilinx XC7Z020
unified 512Kbyte L2 Cache, 256Kbyte on-chip Memory, 54 Multiplexed I/O Pins (MIOs);
Programmable Logic: Artix-7 FPGA, 85K Logic Cells, 560 Kbyte extensible Block RAM (140x 36 Kbit
BRAM Blocks), 220 programmable DSP Slices, Dual 12bit 1Msps Analog-to-Digital Converter, 200
I/O Pins (SelectIO Interfaces)
User LED 3 / FPGA Done (Green)

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12.
13.
14.
15.
16.
4A High-Efficiency Power SoC DC-DC Step-Down Converter with Integrated Inductor (Enpirion
) for 1.0V Power SupplyEN6347
1.5A, 4MHz PowerSoC DC-DC Step-Down Converter with Integrated Inductor ( )Enpirion EP53F8QI
for 1.5V Power Supply
Trenz 4x5 Module Socket Connector (3x )Samtec LSHM Series Connectors
Gigabit Ethernet Transceiver PHY ( )Marvell 88E1512
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver ( )Microchip USB3320C-EZK
Document Change History
date revision authors description
2014-02-10 0.2 Sven-Ole Voigt Work in progress
2013-04-17 0.1 Antti Lukats, Thorsten Trenz Initial release
All Antti Lukats, Thorsten Trenz, Sven-Ole Voigt

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Overview
Trenz Electronic GigaZee XC7Z series are industrial-grade SoMs (system on modules) integrating a
leading-edge Xilinx Zynq-7000 SoC, gigabit Ethernet transceiver, 32-bit-wide 1 gigabyte DDR3 SDRAM, 32
megabyte SPI Flash memory for configuration and operation, eMMC, and powerful switch-mode power
supplies for all on-board voltages. A large number of configurable I/Os is provided via robust board-to-board
(B2B) connectors. All this on a tiny footprint smaller than half a credit card, at the most competitive price.
Development boards are available in our ; reference designs are available in ouronline shop open design
.repositories
Sample Applications
Cryptographic hardware module
Digital signal processing
Embedded industrial OEM platform
Embedded system design
Emulation platforms
FPGA graphics
FPGA video processing
Image processing
IP (intellectual property) cores
Parallel processing
Rapid prototyping
Reconfigurable computing
System-on-Chip (SoC) development
Key Features
Industrial-grade Xilinx Zynq-7000 SoM (system on module)
Rugged for shock and high vibration

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ARM dual-core Cortex-A9 MPCore @ up to 800 MHz
10/100/1000 tri-speed gigabit Ethernet transceiver (PHY), SGMII accessible on a board-to-board
connector
USB 2.0 high-speed ULPI transceiver
32-bit-wide 1 Gbyte DDR3 SDRAM
32 Mbyte SPI Flash memory supporting XiP
4 Gbyte e·MMC (up to 64 Gbyte)
Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips
board-to-board connectors152 FPGA I/Os (75 LVDS pairs possible) and 14 MIOs available on
4.0 A x 1.0 V power rail
1.5 A x 1.5 V power rail
1.5 A x 1.8 V power rail
System management and power sequencing
eFUSE bit-stream encryption
AES bit-stream encryption
Valid MAC Address and 2 kilobit serial EEPROM
SHA-256 authentication chip with unique serial number
temperature compensated RTC (real-time clock)
MEMS sensor (3-axis accelerometer and 3-axis magnetometer)
3 user LEDs
Evenly-spread supply pins for good signal integrity
Other assembly options for cost or performance optimization available upon request

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Getting Started
Preloaded (Factory default) SPI Flash Image
The TE0720 module comes with the SPI Flash preloaded with a default bootloader, U-Boot and Linux are
setup to run automatically if SPI flash boot mode is selected (Red LED fast blinking after power up). U-Boot
is configured with a standard 3 second delay to allow the U-Boot interactive console to be used. The console
is connected to PS UART0, mapped to MIO14 (UART0_RX) and MIO15 (UART0_TX), and has a baud rate
of 115200. The MIO14 and MIO15 signals are routed to the CPLD on the TE0701 Carrier Board which, in
turn, connects these PS UART0 RX and TX signals to the onboard FTDI USB to Multipurpose UART/FIFO
IC ( ). Hence, the console output view can be easily accomplished (e.g., in SDK "Terminal"FTDI FT2232H
window or in HTerm) by attaching it to the corresponding virtual COM port (the COM port number may
differ):
Please consult TE0701 Carrier Board User Manual | Connecting FTDI USB-to-UART/FIFO
for more details on the required VCOM configuration!Interface
Figure 1: Booting Linux Kernel (by default from SPI Flash) - SDK "Terminal" window

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Figure 2: Booting Linux Kernel (by default from SPI Flash) - Another (optional) console output, e.g., in
HTerm
After sucessfully starting the kernel on Xilinx Zynq, the following Linux prompt appears:

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Congratulations! You have been successfully booting up the preloaded SPI Flash image on the TE07020
GigaZee Zynq SoM.
The preloaded images provided are to demonstrate the board's capability. It is expected that the
customer will replace them with their own images.
Boot Procedure
FSBL (First Stage Bootloader)
The primary boot source for the TE0720 is the on-board SPI Flash. After power on the Zynq PS boot ROM
fetches the FSBL from the SPI Flash and executes it. Then the FSBL code takes over and initializes the
Zynq PS peripherals as well as the DDR3 memory controller. Finally the FSBL proceeds to load the PS
object code or FPGA configuration data. Primary factory FSBL for the TE0720 only loads SSBL (Second
Stage Bootloader) from SPI Flash and executes it. This way it is possible to boot the O/S (Linux) with or
without configuring the FPGA Fabric. Boot configuration can select the order of the images to be loaded. It is
possible that the SSBL loads the FPGA only, loads the FPGA and then loads and executes application (O/S)
code, or loads the user application without configuring the FPGA fabric.
FPGA images and application code can reside in on-board SPI Flash, in on-board eMMC or on an external
SD card.
Note: an FSBL image can not be loaded from eMMC. FSBL is fetched from SPI Flash or from an
external SD card.

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Note: Xilinx wizard generated FSBL does not properly initialize the SD card detect multiplexer
values. By default MIO0 remains selected. If writing your own FSBL it is necessary to initialize it
properly. TE0720 standard FSBL selects the EMIO63 pin for SD card detect and WP inputs (this
forces the card detect to succeed).
SD0_WP_CD_SEL = 0x003F003F;
SD1_WP_CD_SEL = 0x003F003F;
Pseudo code to initialize the CD and WP selection bit to point to EMIO63 (tied low if not connected in user
logic).
SSBL (Second Stage Bootloader)
Second stage bootloader is usually fetched from SPI flash. By default a customized U-Boot is used which is
responsible for loading the O/S. If U-Boot functionality is not needed then the user application could be
implemented as SSBL image.
Boot Modes
The Zynq-7000 generally supports several boot modes that can be selected by five boot mode pins
BOOT_MODE[4:0], where BOOT_MODE[4] / MIO[6] enables the PLLs. The other boot mode pins select the
boot source in the following way (see Xilinx , UG585 v1.6.1,Zynq-7000 AP SoC Technical Reference Manual
Table 6-2 on page 147):
BOOT_MODE[0]
MIO[5] BOOT_MODE[2] MIO[4] BOOT_MODE[1] MIO[3] BOOT_MODE[3] MIO[2]
Cascaded JTAG 0
Independent JTAG 1
JTAG 0 0 0 0
Quad-SPI 1 0 0
SD Card 1 1 0
Table 1: Zynq-7000 AP SoC Boot_Mode MIO Pins (Extract)
As it can be seen in Table 1 the only difference between and boot mode is Quad-SPI SD Card
BOOT_MODE[2] / MIO[4]. This is exactly the only signal which is controlled by the MODE output of the
TE0701 on-board CPLD. The BOOT_MODE[0] / MIO[5] and BOOT_MODE[1] / MIO[3] input pins are
tightend correspondingly, e.g., on the TE0720 Zynq SoC Module to pull-up (i.e., SPI-DQ3/M3 = PS_MIO5 =
1) and pull-down (i.e., SPI_DQ1/M1 = PS_MIO3 = 0) resistors.

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The TE0720 Zynq SoC Module on the TE0701 Carrier Boards supports two different boot modes:
QSPI and SD Card booting. For more information on configuring the boot mode please refer to "
".TE0701 Carrier Board User Manual | Configuring Boot Mode
QSPI Boot Mode
Xilinx Answer record AR47023
Currently writing to the SPI Flash is only possible from Vivado SDK starting from version.2013.4
Writing from Impact (any version) is not supported.
U-Boot functions can be used to update SPI Flash.
Xilinx Answer record need to be followed, currently the system controller firmware does notAR57744
provide this safety function.
Update the SPI Flash from an SD Card
To update SPI Flash contents from files stored on an SD card use the U-Boot commands "fatload" and "sf".
Example:
Read boot.bin from SD Card to memory address 0x1000000
fatload mmc 0 0x1000000 boot.bin
Initialize SPI Interface
sf probe 0 0 0
Write 0x450000 bytes from address 0x1000000 to offset 0 in SPI Flash
sf update 0x1000000 0 0x450000
The default U-Boot environment has predefined command sequences to update SD Flash from an SD card.
This update contain files used for Linux boot (boot.bin, uImage, uramdisk.image.gz and tevicetree.dtb).
run sdfetch
run reflash_all
Update the SPI Flash from a network
To update SPI Flash via Ethernet the U-Boot commands "tftp" and "sf" can be used.

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Host PC network interface should have IP address 192.168.42.2. Direct connection from a host PC to the
board is recommended. It is possible to change the IP address of the board from U-Boot, but there could be
other issues when the connection goes via a corporate network.
TFTP server software should be installed on the host PC to provide file access via the TFTP protocol. A
TFTP server is no longer provided by Microsoft as part of the Windows O/S, so third-party software must be
used.
Example of TFTP server configuration
Download OpenTFTPServer from http://sourceforge.net/projects/tftp-server/
Install OpenTFTPServer
Run Open TFTP Server -> Configure from Start menu
Edit configuration file.
[LISTEN-ON]
192.168.42.2
[HOME]
c:\firmware\
[LOGGING]
All
[ALLOWED-CLIENTS]
[TFTP-OPTIONS]
Run Open TFTP Server -> Run Stand Alone
After configuration files in C:\firmware can be downloded via TFTP.
Example:
Download boot.bin from host PC to memory address 0x1000000
tftp 0x1000000 boot.bin
Initialize SPI Interface
sf probe 0 0 0
Write 0x450000 bytes from address 0x1000000 to offset 0 in SPI Flash
sf update 0x1000000 0 0x450000

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SD Card Boot Mode
TE0720 can also boot directly from an SD card. In this mode SPI Flash is not used (all code starting from the
FSBL is loaded from the SD card).
SDIO0 Bootable slot MIO pins have a 1.8V fixed I/O voltage so the SD card must be connected via
a level shifter on the carrier board.
Programming the FPGA with new Configurations
Configuring the FPGA via JTAG
Either Xilinx Impact or ChipScope can be used to load bitstreams over JTAG.
Configuring the FPGA by the Processing System (PS)
Files that can be used for FPGA configuration using the PS DEVCFG interface have to be binary bitstreams
with the preamble stripped and the bytes swapped within 32-bit words. The Xilinx bitgen tool can produce
files with a BIN extension and a stripped header, but the generated files do not have the correct byte swap.
Example for "promgen" parameters to convert bitstream "top.bit" to byte-swapped binary file "top.bin":
promgen.exe -w -b -p bin -o top.bin -u 0 top.bit -data_width 32
Bitstreams that do include PS instantiation have to be generated with CCLK as the startup clock.
Configuring the FPGA with U-Boot
The FPGA can be configured or reconfigured from the U-Boot prompt:
zynq-uboot> nm 0xf8007080
f8007080: 00000010 ? 0
f8007080: 00000000 ? x
zynq-uboot> nm 0xf8007080
f8007080: 00000000 ? x
zynq-uboot> fatload mmc 0 0x100000 top.bin
reading top.bin
4045564 bytes read in 628 ms (6.1 MiB/s)
zynq-uboot> fpga load 0 0x100000 0x3dbafc

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Writing 0 to address 0xF8007080 is a temporary fix for the first revision of the FSBL shipped. It is
required to make the FPGA configuration correctly both in U-Boot and in Linux. An explanation has
been given by a Xilinx employee on the .Xilinx User Community Forums
Configuring the FPGA in Linux
The FPGA can also be configured within Linux:
zynq> mkdir /tmp/sd
zynq> mount /dev/mmcblk1p1 /tmp/sd
zynq> cd /tmp/sd
zynq> cat top.bin > /dev/xdevcfg
You must apply the write to address 0xF8008070 in U-Boot before booting Linux, otherwise the
FPGA load will fail.

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Detailed Description
Overview
Figure 2: TE0720 GigaZee Zynq SoM Block Diagram

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System Management, Power Supply & Resets
Figure 3: Overview: TE0720 System Management, Power Supply & Resets
Note: The DDR3 SDRAM size depends on assembly option.
1
1.0V and 1.8V TE0720 power supply circuits are not shown to create a better overview (see
2TE0720 User Manual | Power
for more details).Supply
Four independent VCCIO voltages (VCCIO13, VCCIO33, VCCIO34, VCCIO35) are fully customizable (1.5V, 1.8V, 2.5V, 3.3V)
3
and can be chosen application-specifically (on a user defined "Carrier Board"). For example, on our "TE0701-03 Carrier Board" the
VCCIO voltages have been chosen on the one hand for VCCIO33 and VCCIO34 to be 2.5V by default (or alternatively 3.3V) and
on the other hand for VCCIO13 and VCCIO35 to be the user-programmable FMC_VADJ voltage via I2C (see TE0720 User
) by default (or alternatively 2.5V and 3.3V,Manual | Carrier Boards for TE0720 - Configuring FMC Power Supply Voltage
respectively).