Ublox AMY-5M User manual

AMY-5M
u-blox 5 GPS Modules
Hardware Integration Manual
Abstract
This document describes the hardware features and specifications of
the cost effective and high-performance AMY-5M ROM-Based GPS
module featuring the u-blox 5 positioning engine.
The AMY-5M module boasts the industry’s smallest form factor and
is a fully tested standalone solution that requires no host
integration.
This module combines exceptional GPS performance with highly
flexible power, design, and serial communication options
locate, communicate, accelerate
www.u-blox.com

AMY-5M - Hardware Integration Manual
GPS.G5-MS5-08207-A3 Page 2 of 54
Document Information
Title
AMY-5M
Subtitle
u-blox 5 GPS Modules
Document type
Hardware Integration Manual
Document number
GPS.G5-MS5-08207-A3
Document status
Preliminary
This document contains preliminary data, revised and supplementary data may be
published later.
This document applies to the following products:
Name
Type number
ROM/FLASH version
PCN reference
AMY-5M
AMY-5M-0-003
ROM5.00
n/a
This document and the use of any information contained therein, is subject to the acceptance of the u-blox terms and conditions. They
can be downloaded from www.u-blox.com.
u-blox makes no warranties based on the accuracy or completeness of the contents of this document and reserves the right to make
changes to specifications and product descriptions at any time without notice.
u-blox reserves all rights to this document and the information contained herein. Reproduction, use or disclosure to third parties without
express permission is strictly prohibited. Copyright © 2010, u-blox AG.
u-blox®is a registered trademark of u-blox Holding AG in the EU and other countries. ARM®is the registered trademark of ARM Limited in
the EU and other countries.

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Preface
u-blox Technical Documentation
As part of our commitment to customer support, u-blox maintains an extensive volume of technical
documentation for our products. In addition to our product-specific technical data sheets, the following manuals
are available to assist u-blox customers in product design and development.
GPS Compendium: This document, also known as the GPS book, provides a wealth of information
regarding generic questions about GPS system functionalities and technology.
Receiver Description including Protocol Specification: Messages, configuration and functionalities of
the u-blox 5 software releases and receivers are explained in this document.
Hardware Integration Manual: This Manual provides hardware design instructions and information on
how to set up production and final product tests.
Application Note: document provides general design instructions and information that applies to all u-blox
GPS receivers. See Section Related documents for a list of Application Notes related to your GPS receiver.
How to use this Manual
The AMY-5M Hardware Integration Manual provides the necessary information to successfully design in and
configure these u-blox 5-based GPS/GALILEO receiver modules. For navigating this document please note the
following:
This manual has a modular structure. It is not necessary to read it from the beginning to the end. To help in
finding needed information, a brief section overview is provided below:
1. Hardware description: This chapter introduces the basics of function and architecture of the u-blox 5
modules.
2. Design-in: This chapter provides the Design-In information necessary for a successful design.
3. Product handling: This chapter defines packaging, handling, shipment, storage and soldering.
4. Product testing: This chapter provides information about testing of OEM receivers in production.
The following symbols are used to highlight important information within the manual:
An index finger points out key information pertaining to module integration and performance.
A warning symbol indicates actions that could negatively impact or damage the module.
Questions
If you have any questions about u-blox 5 Hardware Integration, please:
Read this manual carefully.
Read the questions and answers on our FAQ database on the homepage http://www.u-blox.com
Contact our information service on the homepage http://www.u-blox.com
Technical Support
Worldwide Web
Our website (www.u-blox.com) is a rich pool of information. Product information, technical documents and
helpful FAQ can be accessed 24h a day.

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By E-mail
If you have technical problems or cannot find the required information in the provided documents, contact the
nearest of the Technical Support offices by email. Use our service pool email addresses rather than any personal
email address of our staff. This makes sure that your request is processed as soon as possible. You will find the
contact details at the end of the document.
Helpful Information when Contacting Technical Support
When contacting Technical Support please have the following information ready:
Receiver type (AMY-5M) and firmware version (e.g. V5.00)
Receiver configuration
Clear description of your question or the problem together with a u-center logfile
A short description of the application
Your complete contact details

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Contents
Preface ................................................................................................................................3
Contents..............................................................................................................................5
1Hardware description ..................................................................................................8
1.1 Overview .............................................................................................................................................. 8
1.2 Architecture.......................................................................................................................................... 8
2Design-in.......................................................................................................................9
2.1 Power management ............................................................................................................................. 9
2.1.1 Overview ....................................................................................................................................... 9
2.1.2 Power management configuration .............................................................................................. 11
2.1.3 System power consumption ........................................................................................................ 11
2.1.4 How to connect the power supply pins ....................................................................................... 12
2.1.5 Single 2.5…3.6 V supply ............................................................................................................. 12
2.1.6 Single 1.75…2.0 V supply ........................................................................................................... 13
2.1.7 Separate supplies of 1.8 V (1.75…2.0V) and 1.4 V (1.4…3.6 V) .................................................. 14
2.1.8 Separate supplies of 3.0 V (2.5…3.6 0V) and 1.4 V (1.4…3.6 V) ................................................. 15
2.1.9 Power modes .............................................................................................................................. 15
2.1.10 Active antenna supply ................................................................................................................. 16
2.2 System functions ................................................................................................................................ 17
2.2.1 EXTINT - external interrupt pin..................................................................................................... 17
2.2.2 System monitoring ...................................................................................................................... 17
2.3 Interfaces............................................................................................................................................ 17
2.3.1 Serial ........................................................................................................................................... 17
2.3.2 USB ............................................................................................................................................. 17
2.3.3 Display Data Channel (DDC) ........................................................................................................ 18
2.4 I/O Pins ............................................................................................................................................... 23
2.4.1 Peripheral Input Output (PIO)....................................................................................................... 23
2.4.2 Configuration Pins....................................................................................................................... 23
2.4.3 SAFEBOOT_N .............................................................................................................................. 26
2.4.4 RTC ............................................................................................................................................. 26
2.5 Increasing interference immunity ........................................................................................................ 26
2.6 Active antenna supervisor ................................................................................................................... 26
2.7 Design-in checklist .............................................................................................................................. 27

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2.7.1 Schematic design-in checklist for u-blox 5 ................................................................................... 27
2.7.2 AMY-5M design .......................................................................................................................... 28
2.7.3 Design for AMY-5M .................................................................................................................... 29
2.8 Layout design-in checklist ................................................................................................................... 31
2.9 Layout ................................................................................................................................................ 32
2.9.1 Footprint ..................................................................................................................................... 32
2.9.2 Paste mask .................................................................................................................................. 32
2.9.3 Placement ................................................................................................................................... 33
2.10 Migration considerations................................................................................................................. 33
2.11 EOS/ESD/EMI precautions................................................................................................................ 34
2.11.1 Abbreviations .............................................................................................................................. 34
2.11.2 Electrostatic Discharge (ESD)........................................................................................................ 34
2.11.3 ESD protection measures............................................................................................................. 34
2.11.4 Electrical Overstress (EOS)............................................................................................................ 35
2.11.5 EOS protection measures............................................................................................................. 35
2.11.6 Electromagnetic Interference (EMI) .............................................................................................. 35
2.11.7 GSM applications ........................................................................................................................ 36
2.11.8 Recommended parts ................................................................................................................... 38
3Product handling & soldering....................................................................................39
3.1 Packaging, shipping, storage and moisture preconditioning ............................................................... 39
3.2 ESD handling precautions ................................................................................................................... 39
3.3 Soldering ............................................................................................................................................ 40
3.3.1 Soldering paste............................................................................................................................ 40
3.3.2 Reflow soldering ......................................................................................................................... 40
3.3.3 Optical inspection........................................................................................................................ 40
3.3.4 Repeated reflow soldering........................................................................................................... 40
3.3.5 Wave soldering............................................................................................................................ 40
3.3.6 Hand soldering ............................................................................................................................ 40
3.3.7 Rework........................................................................................................................................ 40
3.3.8 Conformal coating ...................................................................................................................... 40
3.3.9 Casting........................................................................................................................................ 41
3.3.10 Use of ultrasonic processes.......................................................................................................... 41
4Product testing ...........................................................................................................42
4.1 Test parameters for OEM manufacturer .............................................................................................. 42
4.2 System sensitivity test ......................................................................................................................... 42
4.2.1 Guidelines for sensitivity tests ...................................................................................................... 42

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4.2.2 ‘Go/No go’ tests for integrated devices........................................................................................ 42
Appendix ..........................................................................................................................43
AComponent selection .................................................................................................43
A.1 RTC crystal (Y2) .................................................................................................................................. 43
A.2 I2C Serial EEPROM memory ................................................................................................................ 43
A.3 USB line protection (D2) ..................................................................................................................... 43
A.4 USB LDO (U3) ..................................................................................................................................... 43
A.5 Operational amplifier (U31) ................................................................................................................ 44
A.6 Dual open-drain buffer (U32).............................................................................................................. 44
A.7 Antenna supervisor switch transistor (T31).......................................................................................... 44
A.8 Ferrite bead filter (FB1) ....................................................................................................................... 44
A.9 Inductor (L) ......................................................................................................................................... 44
A.10 Standard capacitors ........................................................................................................................ 44
A.11 Standard resistors ........................................................................................................................... 45
BReference designs ......................................................................................................46
B.1 Minimum bill of material smart antenna ............................................................................................. 46
B.1.1 Schematic.................................................................................................................................... 47
B.1.2 Bill of material ............................................................................................................................. 48
B.1.3 Layout ......................................................................................................................................... 48
B.2 LEA-5 smart antenna with AMY-5M ................................................................................................... 49
B.2.1 Schematic.................................................................................................................................... 50
B.2.2 Bill of material ............................................................................................................................. 51
B.2.3 Layout ......................................................................................................................................... 52
CGlossary ......................................................................................................................52
Related documents...........................................................................................................53
Revision history................................................................................................................53
Contact..............................................................................................................................54

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1Hardware description
1.1 Overview
The AMY-5M is the GPS industry’s smallest standalone receiver. It is a fully tested ROM-based solution that
features the high performance u-blox 5 positioning engine. The AMY-5M has been developed for easy design
and integration, requires no host integration, which enables extremely short times to market.
The AMY-5M offers three different serial interfaces. The receiver features u-blox SuperSense®Indoor GPS -and
uses a standard Crystal, which provides fast acquisition and tracking performance at an economical price.
Furthermore, 2-layer PCB integration is supported, which brings additional cost savings.
AMY-5M’s miniature size means that it can be integrated into the smallest portable devices. Advanced
interference suppression mechanisms and innovative RF architecture ensure maximum performance even in
hostile signal environments.
1.2 Architecture
The AMY-5M module consists of two functional parts - the RF and the Baseband sections. See Figure 1 for a
block diagram of the AMY-5M.
The RF Front-End includes the DC-block, the input matching elements, the integrated Low Noise Amplifier (LNA),
the SAW bandpass filter, the u-blox 5 RF-IC and the Crystal.
The Baseband section contains the u-blox 5 Baseband processor. The RTC crystal and additional elements such as
the optional external memory for enhanced programmability and flexibility are optional
RF Front-End Baseband
Digital IF Filter
SRAM
ROMCode
ARM7TDMI-S
®
GPS / GALILEO
Engine
Power MGM
RTC
Backup RAM
Interfaces
RTCCrystal
(optional)
GPIO
UART
USB V2.0
DDC
(I
2
C compatible.)
Crystal
F
RF Front-End
Integrated LNA
Fractional
NSynthesizer
Main Power
RF Input
Matching
Active
antenna
SAWFilter
Backup Battery
AMY-5M
Available
Interfaces
Figure 1:AMY-5M hardware block schematic

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2Design-in
In order to obtain good performance with a GPS receiver module, there are a number of points that require
careful attention during the design-in. These include:
Power Supply
Good performance requires a clean and stable power supply.
Interfaces
Ensure correct wiring, rate and message setup on the module and your host system.
Antenna interface
For optimal performance seek short routing, matched impedance and no stubs.
With AMY-5M an external LNA is required if no active antenna is used.
2.1 Power management
2.1.1 Overview
The power supply circuitry can be adapted to various concepts, depending on the intended application.
Figure 2 gives an overview of the power supply features.
AMY-5
VDD_B NC
VDD_IO VDD_IO 1.65...3.6 V
XTAL_IN
XTAL_OUT
V_DCDC
1.4...3.6 V
Main Battery
1.4...3.6 V
Backup Battery V_BCKP
VDD_ANA NC
VDD_LNA NC
V_TH
V_TH=0: V_DCDC=2.5V - 3.6V
V_TH open: V_DCDC=1.75V - 2.0V
VDD_C
Crystal C20
f
XTAL
= 32.768 kHz
Y2
C19
(optional)
VDD_3V
VDD_RF
V_RESET
V_RESETmust be high to run the receiver. C
Figure 2: Power supply diagram
2.1.1.1 Main supply voltage
In operation the base-band supply current is supplied through pin V_DCDC. The built-in LDO generates the
stabilized core voltage V_DDC from V_DCDC. The current at V_DCDC depends heavily on the current system
state and is in general very dynamic.
It is strongly recommended to use a low-impedance supply (<< 1 Ohm) to the V_DCDC pin.

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2.1.1.2 Base-band I/O supply voltage
In general, the digital I/Os of the base-band part are supplied with VDD_IO from the host system. The wide
range of VDD_IO allows seamless interfacing to standard logic voltage levels. VDD_IO must be supplied in any
case with a voltage in the specified range, as some CFG_xx pins are always read during system boot in order to
define the initial configuration of the receiver.
The power management unit does not supervise VDD_IO. External circuitry must guarantee that VDD_IO
is within operating specification before the system boots and that it remains within specification until
the system shuts down. See also section 2.1.1.6.
2.1.1.3 Base-band core voltages
The core voltages VDD_B and VDD_C core are generated separately, in order to enable main supply VDD_C
switch off while the back-up domain VDD_B remains alive. The core voltages are generated by means of internal
LDOs. The input voltage range of the LDOs is wide and allows the use of several types of batteries.
2.1.1.4 Backup power supply
A backup battery can be connected to supply the RTC and the backup RAM in case of power failure at the main
battery (VDD_IO). An internal switch will supply the internal VDD_B power domain in case VDD_IO drops below
the specified minimum value. VDD_IO will supply the VDD_B power domain if a sufficiently high input voltage is
detected. See also section 2.1.1.6.
Limit V_BCKP and VDD_IO to 3.6 V.
2.1.1.5 RF supply voltages
The main supply of the RF unit is 1.8 V supplied to the VDD_RF pin. Optionally, this voltage can be generated
with the internal LDO from the VDD_3V input. Depending on the application, the VDD_3V pin can be supplied
independently, or it can be connected to the V_DCDC via a filter.
VDD_RF must be a clean supply to obtain optimal performance. Since the V_DCDC current is very dynamic, a
supply filter (see Figure 3) is recommended to ensure little or no ripple on VDD_RF.
C10
FB1 V
RF
V
DCDC
Figure 3: Supply filter
2.1.1.6 Built-in supply voltage monitors
Built-in supply voltage monitors ensure that the system always operates within safe limits. The following
conditions need to be met in order for the system to run properly:
1. The core voltages VDD_C and VDD_B need to be within specification. These voltages are supervised by
internal supply monitors.
2. The RF supply voltage VDD_RF needs to be within specification.
3. If external memory is used, its supply voltage, i.e. VDD_IO, needs to be within the specification of this
part. This must be verified since there is no internal monitor of VDD_IO
With respect to points 2 and 3 listed above, the voltage that defines the lowest operational boundary condition
of the system shall be supervised at the V_RESET pin. This is usually either the TCXO supply voltage (VDD_3V) or
the RF IC supply voltage (VDD_RF). In designs using EEPROM memory it may also be VDD_IO. Normally, higher
system supply voltages take longer to rise and fall faster than lower supply voltages, e.g. if in a given application,

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the RF section requires 1.8 V but external memory requires 2.7 V, it is advisable to monitor VDD_IO rather than
VDD_RF.
The threshold at V_RESET for releasing the MR_N master reset signal can be configured using the V_TH pin. It
can be set to either 2.5 V or 1.8 V. If V_TH is open, the threshold is set to 1.8 V, if this pin is connected to GND
the threshold is at 2.5 V.
Internally, VDD_B and VDD_C are supervised by power-on reset circuits. Reset signals on backup and core
domains are only released once the respective supply voltages fall within the operational conditions.
An additional monitor switches the supply of the back-up region VDD_B from VDD_IO to V_BCKP, once VDD_IO
falls below its operational specification. Thus, a separate supply source can be used to maintain RTC and backup
RAM information even if VDD_IO fails. If this feature is not needed, V_BCKP must be connected to GND.
2.1.1.7 USB interface power supply
VDD_USB supplies the I/Os of the USB interface. If the USB interface is not used, the VDD_USB pin must be
connected to GND.
If the application uses USB, the correct USB power mode needs to be configured (bus-powered or self
powered). See the u-blox 5 Receiver Description including Protocol Specification [1].
2.1.2 Power management configuration
Depending on the application, the power supply schematic will differ. Some examples are shown in the
following sections:
Supply voltage nominal 3.3 V (2.5 –3.6 V) see section 2.1.5
Supply voltage nominal 1.8 V (1.75 –2.0 V) see section 2.1.6
Direct supply of core voltages (VDD_RF, VDD_3V 1.8 V, V_DCDC 1.4 V) see section 2.1.7
Dual power supply using 3.0V and 1.4V (VDD_3V 3.0 V, V_DCDC 1.4 V) see section 2.1.8
2.1.3 System power consumption
the total system power disipation p can be calculated using Equation 1:
P = (VRF IRF) + (V_DCDC IDCDC)
Equation 1: Calculation of system power dissipation
From this equation it is clear that a 1.4 V and 1.8 V dual supply provides the optimum solution in terms of power
efficiency. The corresponding application circuit is shown in section 2.1.7. In case distinct 1.4 V and 1.8 V supply
voltages are not available in the system, the single 1.8 V supply provides the best trade-off between circuit
complexity and power efficiency. This scenario is described in section 2.1.6.
At single 3.3 V supply voltage the use of a DC/DC converter may increase power efficiency only marginally, i.e.
by about 22% for continuous tracking operation. The optimum power-efficiency is achieved if the DC/DC
converter is only used to generate the 1.4 V core voltage and the RF-IC supply voltage is generated using the
built-in LDO. If power-efficiency is key for the application, use of an ultra-high efficiency external DC/DC
converter such as Linear Technology’s LTC3410 is recommend. This particular device also reduces the footprint
needed for the DC/DC converter by integrating all active components into a 2.8 × 18 mm2package. In section
2.1.7 and 2.1.8 the applicable power-supply circuitry for the baseband-IC is shown for the case if no DC/DC
converter is used. For supply voltages higher than 3.6 V, the use of an external regulator, preferably a DC/DC
converter, is mandatory. But again, this solution does not provide the utmost power-efficiency.

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2.1.4 How to connect the power supply pins
Table 1 lists the power supply pins and their requirements.
Pin
Function
Comments
V_DCDC
Main Core Supply
Always needs input. The current consumption varies over time (peak currents).
Keep series resistance low to prevent ripple on the power supply.
VDD_3V
Main RF Supply
Always needs input.
VDD_IO
I/O Ring Supply
Always needs an external supply
V_BCKP
Backup voltage supply
Connect to GND if not used
VDD_B
Backup Power
Not connected unless using supply capacitors.
VDD_C
Core Power
Connect to external supply capacitor.
VDD_RF
Core Power
Connect only as shown (refer to Figure 4 through Figure 6).
VDD_ANA
Analog Power
Not connected unless using supply capacitors.
VDD_LNA
LNA Power Supply
Not connected unless using supply capacitors.
Table 1: Power Supply Pins
2.1.5 Single 2.5…3.6 V supply
A single 3.0V power supply is very easy to design but is not the most economic solution to run u-blox 5 receivers
(see section 2.1.3 for details).
C
AMY-5
XTAL_IN
XTAL_OUT
V_DCDC
2.5...3.6 V
Main Battery
1.4...3.6 V
Backup Battery
V_BCKP Crystal C20
f
XTAL
= 32.768 kHz
Y2
C19
(optional)
V_TH
Connect
to GND
Connect
XTAL_IN
to GND
if no RTCused
VDD_3V
VDD_RF
When connecting
to V_DCDC
a filter is imperative
VDD_B
VDD_C
VDD_ANA
VDD_LNA
VDD_IO 1.65...3.6 V
V_RESET
Supply
Filter
Figure 4: Single 2.5…3.6 V supply (for supply filter see Figure 3).

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2.1.6 Single 1.75…2.0 V supply
The single 1.8V power supply a very efficient configuration to run u-blox 5 receivers (see section 2.1.3 for
details). Assure minimal serial resistance in the power supply as the current consumption during operation varies
significantly over time.
C
AMY-5
VDD_B
VDD_IO 1.65...3.6 V
XTAL_IN
XTAL_OUT
V_DCDC
1.75...2.0 V
Main Battery
1.4...3.6 V
Backup Battery
V_BCKP
VDD_ANA
VDD_LNA
VDD_C
V_TH
leave
V_TH
open
Crystal C20
f
XTAL
= 32.768 kHz
Y2
C19
(optional)
VDD_3V
VDD_RF
When connecting to
V_DCDC a filter is imperative
1.8V
Connect
XTAL_IN
to GND
if no RTCused
V_RESET
Supply
Filter
Figure 5: Single 1.75…2.0 V supply (for supply filter see Figure 3).
2.1.6.1 RF supply voltage
With a single 1.8 V supply, VDD_3V must be shorted with the VDD_RF pin, so that the internal LDO is shorted
and there is no voltage drop. The other LDOs in the RF unit provide improved supply rejection at very low
dropout voltage and are always required.

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2.1.7 Separate supplies of 1.8 V (1.75…2.0V) and 1.4 V (1.4…3.6 V)
The dual 1.8V and 1.4V power supply the most efficient configuration to run u-blox 5 receivers (see section
2.1.3 for details). It assures stability since the sensitive RF supply is well separated from the fluctuating base band
power supply.
C
AMY-5
VDD_IO VDD_IO 1.65...3.6 V
XTAL_IN
XTAL_OUT
V_DCDC
1.4...3.6 V
1.4V Supply
1.4...3.6 V
Backup Battery
V_BCKP
VDD_ANA
VDD_LNA
VDD_C
V_TH
Crystal C20
f
XTAL
= 32.768 kHz
Y2
C19
VDD_3V
1.75...2.0 V
1.8V Supply
VDD_RF
VDD_B
(optional)
V_RESET
Connect
XTAL_IN
to GND
if no RTCused
leave
V_TH
open
Figure 6: Separate supplies of 1.8 V and 1.4 V

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2.1.8 Separate supplies of 3.0 V (2.5…3.6 0V) and 1.4 V (1.4…3.6 V)
The dual 3.0V and 1.4V power supply the most efficient configuration to run u-blox 5 receivers (see section
2.1.3 for details). It assures a better stability than a single 3.0V power supply as the sensitive RF supply is well
separated from the fluctuating base band power supply.
AMY-5 VDD_IO VDD_IO 1.65...3.6 V
XTAL_IN
XTAL_OUT
V_DCDC
1.4...3.6 V
1.4V Supply
1.4...3.6 V
Backup Battery
V_BCKP
VDD_ANA
VDD_LNA
VDD_C
V_TH
Crystal C20
f
XTAL
= 32.768 kHz
Y2
C19
VDD_3V
2.5...3.6 V
3.0V Supply
VDD_RF
VDD_B
(optional)
V_RESET
Connect
XTAL_IN
to GND
if no RTCused
Connect
to GND
Figure 7: Dual supplies of 3.0 V and 1.4 V
2.1.9 Power modes
The u-blox 5 features 2 continuous operating modes (Maximum Performance and Eco). Eco mode optimizes the
use of the acquisition engine to deliver lower current consumption and shall be used with AMY-5M. Maximum
Performance mode is not supported with AMY-5M.
For more information, see the u-blox 5 Receiver Description including Protocol Specification [1].

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2.1.10 Active antenna supply
With AMY-5M modules active antennas are supplied via an external coil or circuit. AMY-5M modules do not
provide the antenna bias voltage for active antennas on the RF_IN pin. It is therefore necessary to provide this
voltage outside the module via an inductor as indicated in Figure 8. u-blox recommends using an inductor from
Murata (LQG15HS27NJ02). Alternative parts can be used if the inductor’s resonant frequency matches the GPS
frequency of 1575.4MHz.
R
Low Noise Amplifier
Active Antenna
RF_IN
VDD_3V
L
C
C1L1
C2
Figure 8: Recommended wiring for active antennas
For C and L values see Component Selection Section A.
For optimal performance, it is important to place the inductor as close to the microstrip as possible. Figure 9
illustrates the recommended layout and how it should not be done.
Microstrip RF_IN
Antenna Supply Voltage
(e.g. VDD_3V)
Inductor L
Antenna Supply Voltage
(e.g. VDD_3V)
Inductor L
Microstrip
Good Bad
RF_IN
Figure 9: Recommended layout for connecting the antenna bias voltage for AMY-5M

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2.2 System functions
2.2.1 EXTINT - external interrupt pin
EXTINT0 is an external interrupt pin. It will be used in future AMY-5M releases for wake-up functions in low-
power modes.
2.2.2 System monitoring
The u-blox-5 GPS Receiver provides System Monitoring functions that allow the operation of the embedded
processor and associated peripherals to be supervised. These System Monitoring functions are being output as
part of the UBX protocol, class ‘MON’.
Please refer to the u-blox 5 Receiver Description including Protocol Specification [1].For more information on
UBX messages, serial interfaces for design analysis and individual system monitoring functions.
2.3 Interfaces
2.3.1 Serial
UART 1 (RxD1/TxD1) is the default serial interface. It supports data rates from 4.8 kBit/s to 115 kBit/s. An
interface based on RS232 standard levels (+/- 12 V) can be realized using level shifters such as Maxim MAX3232.
The TxD1 output levels are dependant on VDD_IO. (see AMY-5M Data Sheet [1]). The RxD1 has fixed
input voltage thresholds, which do not depend on VDD_IO (see AMY-5M Data Sheet [1]).
For the default settings see the AMY-5M Data Sheet [1].
Hardware handshake signals and synchronous operation are not supported.
2.3.2 USB
The u-blox 5 USB interface supports the full-speed data rate of 12 Mbit/s.
2.3.2.1 USB external components
The USB interface requires some external components in order to implement the physical characteristics required
by the USB 2.0 specification. These external components are shown in Figure 10 and listed in Table 2.
In order to comply with USB specifications, VBUS must be connected through an LDO (U1) to pin VDD_USB of
the module.
If the USB device is self-powered it is possible that the power supply (V_DCDC) is shut down and the
Baseband-IC core is not powered. Since VBUS is still available, it still would be signaled to the USB host that the
device is present and ready to communicate. This is not desired and thus the LDO (U1) should be disabled using
the enable signal (EN) of the VDD_USB-LDO or the output of a voltage supervisor. Depending on the
characteristics of the LDO (U1) it is recommended to add a pull-down resistor (R11) at its output to ensure
VDD_USB is not floating if LDO (U1) is disabled or the USB cable is not connected i.e. VBUS is not supplied. If
the device is bus-powered, LDO (U1) does not need an enable control.
All u-blox 5 receivers based on ROM 5.00 and above support both Bus and Self Powered Mode on the USB
interface. Please be sure to use the latest drivers from our website.
Connect VDD_USB to GND if not used.

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AMY-5
V_DCDC
1.4...3.6 V
Backup Battery
V_BCKP
V_TH
Connect to GND
because VDD_USB LDO
supplies 3.3V to V_DCDC
VDD_USB
USB_DP
USB_DM
LDO
VDD_USB
R4
R5
C24 C23
D2
VBUS
DP
DM
GND
USB Device
Connector
U1
EN R11
EN
VDD_3V
VDD_RF
V_RESET
Figure 10: USB Interface (bus powered setup)
Name
Component
Function
Comments
U1
LDO
Regulates VBUS (4.4 …5.25 V)
down to a voltage of 3.3 V).
Almost no current requirement (~1 mA) if the GPS receiver is operated as a USB
self-powered device, but if bus-powered LDO (U1) must be able to deliver the
maximum current of ~150 mA. A low-cost DC/DC converter such as LTC3410
from Linear Technology may be used as an alternative.
C23,
C24
Capacitors
Required according to the specification of LDO U1
D2
Protection
diodes
Protect circuit from overvoltage
/ ESD when connecting.
Use low capacitance ESD protection such as ST Microelectronics USBLC6-2.
R4, R5
Serial
termination
resistors
Establish a full-speed driver
impedance of 28…44 Ohms
A value of 27 Ohms is recommended.
R11
Resistor
Ensures a pull down when LDO
is disabled.
10k R is recommended for USB self-powered setup. For bus-powered setup
R11 can be ignored.
Table 2: Summary of USB external components
2.3.3 Display Data Channel (DDC)
An I2C compatible Display Data Channel (DDC) interface is available for serial communication. For more
information about DDC implementation refer to the u-blox 5 Receiver Description including Protocol
Specification [1].
u-blox 5 GPS receivers normally run in the slave mode. Master Mode is only supported when external
EEPROM is used to store configuration. No other nodes are connected to the bus. In this case, the receiver
attempts to establish presence of such a non-volatile memory component by writing and reading from a
specific location.
Two wires, serial data (SDA) and serial clock (SCL), carry information between the devices connected to the bus.
These lines are connected to all devices on the DDC. SCL is used to synchronize data transfers and SDA is the
data line. Both SCL and SDA lines are "open drain" drivers. This means that DDC devices can only drive them
low or leave them open. The pull-up resistor (Rp) pulls the line up to VDD if no DDC device is pulling it down to
GND. If the pull-up resistors are missing, the SCL and SDA lines –are undefined and the DDC bus will not work.

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For most DDC systems the low and high input voltage level thresholds of SDA and SCL depend on VDD. See
receiver datasheet for the applicable voltage levels.
DDC Device A DDC Device B
V
DD
SDA
SCL
GND
RpRp
SDAin
SDAout
SCL in
SDAout
SDAin
SDAout
SCL in
SDAout
Figure 11: A simple DDC connection
The signal shape and the maximum rate in which data can be transferred over SDA and SCL is limited by the
values of Rp and the wire and I/O capacitance (Cp). Long wires and a large number of devices on the bus
increase Cp, therefore DDC connections should always be as short as possible. The resistance of the pull-up
resistors and the capacitance of the wires should be carefully chosen.
Figure 12: DDC block diagram
2.3.3.1 Addresses, roles and modes
Each device connected to a DDC is identified by a unique 7-bit address (e.g. whether it’s a microcontroller,
EEPROM or D/A Converter, etc) and can operate as either a transmitter or receiver, depending on the function of
the device. The default DDC address for u-blox GPS receivers is set to 0x42. Setting the mode field in the CFG-
PRT message for DDC accordingly can change this address.
The first byte sent is comprised of the address field and R/W bit. Hence the byte seen on the bus 0x42 is
shifted by 1 to the left plus R/W bit thus being 0x84 or 0x85 if analyzed by scope or protocol analyzer.
In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing
data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to
permit that transfer. At that time, any device addressed is considered a slave. The DDC-bus is a multi-master bus,
i.e. multiple devices are capable of controlling the bus. Such architecture is not permanent and depends on the
direction of data transfer at any given point in time. A master device not only allocates the time slots when
Rp
Rp

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slaves can respond but also enables and synchronizes designated slaves to physically access the bus by driving
the clock. Although multiple nodes can assume the role of a master, only one at any time is permitted to do so.
Thus, when one node acts as master, all other nodes act as slaves. Table 3 shows the possible roles and modes
for devices connected to a DDC bus.
Transmit
Receive
Master: sends the clock and addresses slaves
Sends data to slave
Receives data from slave
Slave: receives the clock and address
Sends data to master
Receives data from master
Table 3: Possible roles and modes of devices connected to DDC bus
u-blox 5 GPS receivers normally run in the slave mode. There is an exception when an external EEPROM is
attached. In that case, the receiver attempts to establish presence of such a non-volatile memory component by
writing and reading from a specific location. If EEPROM is present (assumed to be located at a fixed address
0xA0), the receiver assumes the role of a master on the bus and never changes role to slave until the following
start-up (subject to EEPROM presence). This process takes place only once at the start-up, i.e. the receiver’s role
cannot be changed during the normal operation afterward. This model is an exception and should not be
implemented if there are other participants on the bus contending for the bus control (µC / CPU, etc.).
As a slave on the bus, the u-blox 5 GPS receiver cannot initiate the data transfers. The master node has the
exclusive right and responsibility to generate the data clock, therefore the slave nodes need not be configured to
use the same baud rate. For the purpose of simplification, if not specified differently, SLAVE denotes the u-blox 5
GPS receiver while MASTER denotes the external device (CPU, μC) controlling the DDC bus by driving the SCL
line.
u-blox GPS receivers support standard mode I2C-bus specification with 7-bit addressing and a data
transfer rate up to 100 kbit/s.
2.3.3.2 Communicating to a slave with the GPS receiver as master
Pins SDA2 and SCL2 have internal pull-ups. If capacitive bus load is large, additional external pull-ups may be
needed in order to achieve the desired data rates.
Table 4 lists the maximum total pull-up resistor values for the DDC interface. The pull-up resistors integrated in
the pads of the baseband-IC can simply be ignored for high capacitive loads. However, for small loads, e.g. if just
connecting to an external EEPROM, these built-in pull-ups are sufficient.
Load Capacitance
Pull-Up Resistor Value R20, R21
50 pF
18 k
100 pF
9 k
250 pF
4 k
Table 4: Pull-up resistor values for DDC interface
Serial I2C memory can be connected to the DDC interface. It will automatically be recognized by firmware. The
memory address must be set to 0b1010000 and the size fixed to 4 kB.