Ublox UBX-G7020 Quick setup guide

UBX-G7020 - Hardware Integration Manual
GPS.G7-HW-10003 Page 1
UBX-G7020
u-blox 7 GPS/GNSS chips
Hardware Integration Manual
Highlights:
u-blox 7 position engine featuring excellent accuracy and
time-to-first-fix performance
Multi-GNSS engine for GPS, GLONASS, Galileo and QZSS
AssistNow Online, Offline and Autonomous for faster TTFF
Minimal board space
Low power consumption
Minimal e-BOM
www.u-blox.com
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Document Information
Title
UBX-G7020
Subtitle
u-blox 7 GPS/GNSS chips
Document type
Hardware Integration Manual
Document number
GPS.G7-HW-10003
Document status
Objective Specification
Document status information
Objective
Specification
This document contains target values. Revised and supplementary data will be published
later.
Advance
Information
This document contains data based on early testing. Revised and supplementary data will
be published later.
Preliminary
This document contains data from product verification. Revised and supplementary data
may be published later.
Released
This document contains the final product specification.
This document applies to the following products:
Name
Type number
ROM/FLASH version
PCN reference
UBX-G7020-KT
QFN40 package
(Standard grade)
UBX-G7020-KT-A0100 A
1.00
N/A
UBX-G7020-CT
WL-CSP50
(Standard grade)
UBX-G7020-CT-A0100 A
1.00
N/A
UBX-G7020-KA
QFN40 package
(Automotive grade)
UBX-G7020-KA-A0100 A
1.00
N/A
This document and the use of any information contained therein, is subject to the acceptance of the u-blox terms and conditions. They
can be downloaded from www.u-blox.com.
u-blox makes no warranties based on the accuracy or completeness of the contents of this document and reserves the right to make
changes to specifications and product descriptions at any time without notice.
u-blox reserves all rights to this document and the information contained herein. Reproduction, use or disclosure to third parties without
express permission is strictly prohibited. Copyright © 2012, u-blox AG.
u-blox®is a registered trademark of u-blox Holding AG in the EU and other countries. ARM®is the registered trademark of ARM Limited in
the EU and other countries.
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Preface
GPS.G7-HW-10003 Objective Specification Page 3 of 74
Preface
u-blox Technical Documentation
As part of our commitment to customer support, u-blox maintains an extensive volume of technical
documentation for our products. In addition to our product-specific technical data sheets, the following manuals
are available to assist u-blox customers in product design and development.
GPS Compendium: This document, also known as the GPS book, provides a wealth of information
regarding generic questions about GPS system functionalities and technology.
Receiver Description and Protocol Specification: Messages, configuration and functionalities of the
u-blox 7 software releases and receivers are explained in this document.
Hardware Integration Manual: This Manual provides hardware design instructions and information on
how to set up production and final product tests.
Application Note: This document provides general design instructions and information that applies to all
u-blox GPS receivers. See section Related documents for a list of Application Notes related to your GPS
receiver.
How to use this manual
This manual has a modular structure. It is not necessary to read it from the beginning to the end.
The following symbols are used to highlight important information within the manual:
An index finger points out key information pertaining to chipset integration and performance.
A warning symbol indicates actions that could negatively impact or damage the receiver.
Questions
If you have any questions about u-blox 7 Hardware Integration, please:
Read this manual carefully.
Contact our information service on the homepage www.u-blox.com.
Read the questions and answers on our FAQ database on the homepage.
Technical support
Worldwide web
Our website (www.u-blox.com) is a rich pool of information. Product information, technical documents and
helpful FAQ can be accessed 24h a day.
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GPS.G7-HW-10003 Objective Specification Page 4 of 74
By E-mail
If you have technical problems or cannot find the required information in the provided documents, contact the
nearest of the Technical Support offices by email. Use our service pool email addresses rather than any personal
email address of our staff. This makes sure that your request is processed as soon as possible. You will find the
contact details at the end of the document.
Helpful information when contacting technical support
When contacting Technical Support please have the following information ready:
Chipset type (e.g. UBX-G7020-KT) and revision (e.g. A0100)
Receiver configuration
Schematic at least of the GPS section of your circuit
Layout of the GPS section of your circuit and the PCB stack-up.
Clear description of your question or the problem together with a u-center logfile
A short description of the application
Your complete contact details
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UBX-G7020 - Hardware Integration Manual
Contents
GPS.G7-HW-10003 Objective Specification Page 5 of 74
Contents
Preface ................................................................................................................................3
Contents..............................................................................................................................5
1Hardware Description ..................................................................................................8
1.1 Overview .............................................................................................................................................. 8
1.2 Architecture.......................................................................................................................................... 8
2Design-in.......................................................................................................................9
2.1 Power management ........................................................................................................................... 10
2.1.1 Power domains............................................................................................................................ 10
2.1.2 Supply voltages ........................................................................................................................... 12
2.1.3 Built in supply monitors ............................................................................................................... 15
2.1.4 Operating Modes ........................................................................................................................ 15
2.2 PIOs.................................................................................................................................................... 16
2.2.1 SQI Flash memory........................................................................................................................ 17
2.2.2 Configuration pins ...................................................................................................................... 18
2.2.3 Communication interfaces........................................................................................................... 19
2.2.4 Time pulse................................................................................................................................... 21
2.2.5 External interrupt ........................................................................................................................ 21
2.2.6 SAFEBOOT_N Pin/ Safe Boot Mode.............................................................................................. 21
2.2.7 Active Antenna Supervisor........................................................................................................... 22
2.3 System reset ....................................................................................................................................... 24
2.4 Clock generation ................................................................................................................................ 25
2.4.1 Clock accuracies and tolerances .................................................................................................. 25
2.4.2 Crystal or TCXO package selection .............................................................................................. 26
2.4.3 Frequency perturbations.............................................................................................................. 26
2.4.4 Crystal oscillator .......................................................................................................................... 27
2.4.5 TCXO .......................................................................................................................................... 28
2.5 Real-Time Clock (RTC) ........................................................................................................................ 30
2.5.1 RTC using a crystal ...................................................................................................................... 30
2.5.2 RTC derived from the system clock; “Single Crystal” Feature....................................................... 30
2.5.3 RTC using an external clock......................................................................................................... 30
2.5.4 Time aiding ................................................................................................................................. 30
2.6 RF front-end ....................................................................................................................................... 32
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2.6.1 General notes on interference issues ........................................................................................... 32
2.6.2 RF front-end circuit options ......................................................................................................... 34
2.7 USB .................................................................................................................................................... 38
2.8 JTAG .................................................................................................................................................. 39
2.9 Layout ................................................................................................................................................ 40
2.9.1 Placement ................................................................................................................................... 40
2.9.2 Package footprint, copper and solder mask ................................................................................. 40
2.10 System Configuration ..................................................................................................................... 43
2.10.1 Communication Interface Configuration ..................................................................................... 43
2.10.2 Low Level Configuration.............................................................................................................. 43
2.10.3 Functional configuration.............................................................................................................. 47
2.10.4 Functional configuration at run time............................................................................................ 47
3Component Selection.................................................................................................48
3.1 TCXO (Y1) .......................................................................................................................................... 48
3.2 Crystal (Y2)......................................................................................................................................... 50
3.3 RTC crystal (Y3) .................................................................................................................................. 51
3.4 SQI flash (U3)...................................................................................................................................... 51
3.5 RF band-pass filter (F1) ....................................................................................................................... 51
3.6 External LNA protection filter (F2) ....................................................................................................... 52
3.7 USB line protection (D1) ..................................................................................................................... 52
3.8 USB LDO (U3) ..................................................................................................................................... 52
3.9 External LNA (U1) ............................................................................................................................... 52
3.10 LNA_IN ESD protection diode (D1) .................................................................................................. 53
3.11 Operational amplifier (U6)............................................................................................................... 53
3.12 Open-drain buffer (U4, U7 and U8)................................................................................................. 53
3.13 Antenna supervisor switch transistor (T1) ........................................................................................ 53
3.14 RF inductors .................................................................................................................................... 53
3.15 Inductor for DCDC converter (L2).................................................................................................... 54
3.16 Standard capacitors ........................................................................................................................ 54
3.17 Standard resistors ........................................................................................................................... 55
3.18 Ferrite beads (FB1) .......................................................................................................................... 55
3.19 Feed-thru capacitors ....................................................................................................................... 55
4Design-in Checklists ...................................................................................................56
4.1 Pin list................................................................................................................................................. 57
4.2 Schematic and bill of material design-in checklist................................................................................ 58
4.3 Layout design-in checklist ................................................................................................................... 58
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5Production ..................................................................................................................60
5.1 Packaging, shipping, storage and moisture preconditioning ............................................................... 60
5.2 ESD handling precautions ................................................................................................................... 60
5.3 Soldering ............................................................................................................................................ 60
5.4 Production.......................................................................................................................................... 61
5.4.1 Set the Low Level Configuration and program the optional SQI flash .......................................... 62
5.4.2 Test the GPS/GNSS performance ................................................................................................. 63
5.4.3 System monitoring ...................................................................................................................... 63
Appendix ..........................................................................................................................64
AReference schematics .................................................................................................64
A.1 Cost optimized circuit ......................................................................................................................... 64
A.2 Best performance circuit ..................................................................................................................... 65
A.3 Power optimized circuit ...................................................................................................................... 66
A.4 Improved jamming immunity .............................................................................................................. 67
A.5 1.8V design using TCXO ..................................................................................................................... 68
A.6 Circuit using active antenna................................................................................................................ 69
A.7 USB self-powered circuit ..................................................................................................................... 70
A.8 USB bus-powered circuit..................................................................................................................... 71
A.9 Circuit using 3-pin antenna supervisor ................................................................................................ 72
Related documents...........................................................................................................73
Revision history................................................................................................................73
Contact..............................................................................................................................74
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1Hardware Description
1.1 Overview
Featuring a single die solution, low power consumption and low costs, the UBX-G7020 GPS/GNSS chips are
multi-GNSS (GPS, GLONASS, Galileo, QZSS and SBAS) positioning chips developed to meet the requirements of
an extensive range of applications and end-products. Based on the high performance u-blox 7 position engine,
these receivers provide exceptional sensitivity and acquisition times without requiring an external host. u-blox’
advanced RF-design and interference suppression measures enable reliable positioning even in difficult signal
conditions.
u-blox 7 technology delivers high performance with low power consumption and low costs. An integrated
DC/DC converter and intelligent power management are breakthroughs for low-power applications. The minimal
BOM requires as few as 8 external components and the small footprint further reduces costs by enabling 2-layer
PCB integration. LDOs and an LNA are built-in and costly external memory is not needed. This makes UBX
G7020 positioning chips the ideal solutions for cost sensitive applications that don’t require firmware update
capability. For applications needing firmware update capability or taking advantage of the data logging feature
the UBX-G7020 can be connected to an external SQI FLASH memory. Lower price GPS/GNSS crystals as well as
high performance TCXOs are also supported.
1.2 Architecture
Figure 1 shows the block diagram of the UBX-G7020. The internal LNA requires an external input matching. As
with its predecessor, u-blox 6, the customer can choose between an external TCXO and an external crystal using
the internal oscillator to provide the UBX-G7020’s system clock. New with u-blox 7 is the internal DC/DC
converter reducing the power consumption significantly. A RTC crystal, an antenna supervisor circuit and an
external SQI FLASH memory can be added optionally.
Figure 1: UBX-G7020 block diagram
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2Design-in
In order to obtain good performance with UBX-G7020 chip design, there are a number of points that require
careful attention during the design-in. These include:
Power Supply:
Good performance requires a clean and stable power supply.
Interfaces:
Ensure correct wiring, rate and messages setup on the chipset and the host system.
Antenna interface:
For optimal performance seek short routing, matched impedance and no stubs.
RF front-end:
Use an external LNA if your design doesn’t include an active antenna and optimal performance is
important.
Clock/ Oscillator:
A stable clock is essential for GPS/GNSS performance.
Configuration:
It is mandatory for stable operation that all the configurations (Low Level Configuration) of the UBX-
G7020 are set properly.
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2.1 Power management
All the internal voltages for the UBX-G7020 are generated by internal LDOs. Thus no additional external LDOs
are required.
Figure 2 shows typical supply scheme of the Power Management Unit of the UBX-G7020.
Figure 2: UBX-G7020’ PMU
In addition the UBX-G7020 has an internal DC/DC converter, which optionally can be used to reduce the power
consumption, see section 2.1.2.1.1. Using the DC/DC converter requires one external inductor and one external
capacitor.
2.1.1 Power domains
The internal LDOs, which are LDO_B, LDO_C, LDO_RF and LDO_X, are used to provide the voltages for the 4
power domains, which are called backup, core, RF and clock domain. All the power domains are controlled by
PORs (Power On Resets), which are described in section 2.1.3.
2.1.1.1 Backup domain
The voltage for the backup domain is generated by LDO_B and is either supplied by VDD_IO or in case of a
power failure at VDD_IO, by V_BCKP. There is a voltage monitor at VDD_IO, VDD_IO_OK, which switches the
supply for the backup domain from VDD_IO to V_BCKP in case of power failure at VDD_IO.
The control registers for the UBX-G7020 are located in the backup domain - an always on domain which means
if the backup domain is not supplied, all the other domains will not be turned on. All the GPS/GNSS orbit data
and time are maintained in the backup memory to which the functional configuration can also be saved. The
backup domain also runs the RTC (Real Time Clock) section.
Use of valid time and the GPS/GNSS orbit data at start up will improve the GPS/GNSS performance i.e. enables
Hotstarts, Warmstarts and the AssistNow Autonomous process as well as the Power Save Mode. To make use of
these features connect a battery to V_BCKP to continue supplying the backup domain in case of power failure at
VDD_IO.
If no backup battery is used, V_BCKP must be connected to VDD_IO.
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2.1.1.2 Core domain
The voltage for the core domain is generated by LDO_C and is supplied by V_CORE. The core domain is the main
digital power domain and consists of the largest blocks in the chip and sinks most of the current. When it is
switched off, the RF power domain is also switched off.
The core domain requires the backup domain to be alive.
2.1.1.3 RF domain
The voltage for the RF domain is generated by LDO_RF and is supplied by V_CORE. This RF domain supplies most
of the analogue RF section.
The LDO_RF_OUT is used to supply VDD_ANA and VDD_LNA.
The RF domain needs the core domain to be alive.
2.1.1.4 Clock domain
The voltage for the clock domain is generated by LDO_X and is normally supplied by VDD_IO. If the “single
crystal” feature is enabled to provide the RTC function (see section RTC) and there is a power failure at VDD_IO
then the LDO_X input will be switched over to V_BCKP to supply the clock domain
The LDO_X provides the supply for the oscillator and all the clock related circuits.
When a TCXO is used, the LDO_X_OUT voltage has to be used to supply or enable it. The LDO_X_OUT voltage is
configurable and has to meet the TCXO power supply voltage. See section 2.4.5.
The clock power domain requires the backup domain to be alive.
If a TCXO is used, LDO_X_OUT has to be used to supply or enable it.
Remember to configure the LDO_X_OUT voltage according to the TCXO supply or enable voltage.
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2.1.2 Supply voltages
2.1.2.1 V_Core: Main supply voltage
V_CORE is the main supply which supplies the LDO_RF and LDO_C regulators to provide voltages for the core
domain and the RF domain.
The current at V_CORE depends heavily on the current system state and in general exhibits very dynamic
behaviour.
Do not add any series resistance (< 0.2 Ohm) into V_CORE supply as it will generate input voltage noise
owing to the dynamic current conditions.
2.1.2.1.1 DC/DC converter
To improve the power consumption, the supply for V_CORE can be generated with the optional built in DCDC
converter. It generates an output voltage of ~1.45V.
Figure 3: UBX-G7020’ PMU using DCDC converter
The DC/DC block provides an energy conversion efficiency of about 85%, the actual value depending on current
drawn and external inductor L2 and capacitor C6 used. Thus the power savings at a 3.3V power supply can be
almost 50%, see Figure 4.
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Figure 4: Power Savings using DCDC converter
For a 1.8V supply it does not make sense to use the DC/DC converter; the power savings are marginal (~5%). By
default the DC/DC converter is disabled.
The DC/DC converter has to be enabled by the Low Level Configuration. See section 2.10.2.
If the DC/DC converter is not used, V_DCDC_IN and V_DCDC_OUT must be connected to V_CORE.
The V_DCDC_IN pin may sink short term currents of up to 400mA when the DC/DC converter is enabled and the
receiver enters a Software Backup state, which can occur during Power Save Mode operation.
2.1.2.2 VDD_IO: I/O, clock and backup domain supply voltage
VDD_IO supplies all the PIOs, the backup domain and the clock domain. Thus all the PIOs comply with VDD_IO
voltage levels.
The current drawn at VDD_IO depends on the activity and loading of the PIOs plus the crystal or TCXO
consumption. Most of the VDD_IO current is consumed by the SQI bus if the firmware runs out of the optional
SQI flash.
2.1.2.3 V_BCKP: Backup supply voltage
In the event of a power failure at VDD_IO, the backup domain will be supplied by V_BCKP. Furthermore, if the
“single crystal” feature is enabled (which derives the RTC frequency from the main clock), it also supplies the
clock domain in case of a power failure at VDD_IO.
Providing a V_BCKP supply will maintain the time (RTC) and the GPS/GNSS orbit data in backup memory. This
ensures that any subsequent re-starts after a VDD_IO power failure will benefit from the stored data, providing a
faster TTFF than otherwise possible, e.g. when performing a hotstart, warmstart of making use of the AssistNow
Autonomous or AssistNow Offline functions. Thus make sure the V_BCKP supply is independent of VDD_IO
supply.
The GPS satellite ephemeris data are typically valid for up to 4 hours, so it makes sense that the battery/
capacitor at V_BCKP is able to supply the backup current for at least 4 hours to enable hotstarts. For warmstarts
or when making use of the AssistNow Autonomous or AssistNo Offline functions the V_BCKP source has to be
able to supply current for up to a few days.
If the “single crystal” feature is used, the current into V_BCKP will be increased! Make sure your backup
battery capacity is chosen accordingly to meet your specification.
If a backup supply is not provided connect V_BCKP to VDD_IO.
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2.1.2.4 VDD_ANA and VDD_LNA
VDD_ANA is the supply for all the analogue parts in the UBX-G7020. VDD_LNA is the supply for the low noise
amplifier inside the UBX-G7020.
VDD_ANA and VDD_LNA must be supplied by VDD_RF_OUT. If a clean power supply cannot be provided at
V_CORE (which supplies the LDO_RF), it is recommended to add external filtering (FB1 and C3) to supply
VDD_ANA/ VDD_LNA.
Figure 5: Filtering for VDD_LNA and VDD_ANA
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2.1.3 Built in supply monitors
Built-in supply voltage monitors ensure that the system always operates in safe regions. The following conditions
need to be met in order for the system to run properly:
1. The backup domain voltage LDO_B_OUT, the core domain voltage LDO_C_OUT and the RF domain voltage
LDO_RF_OUT need to be within specification. These voltages are supervised by POR_C, POR_B and POR_RF.
2. The I/O voltage VDD_IO needs to be within specification. This voltage is supervised by POR_IO. This supply
monitor has a configurable threshold. If external SQI flash is used the POR_IO threshold has to be set according
to the power supply voltage of the SQI Flash used to ensure that the system only starts when the supply voltage
for the SQI flash is reached. Otherwise, the system may fail to detect the external SQI flash and the SQI flash will
be ignored.
3. The clock domain voltage LDO_X_OUT needs to be within specification. This voltage is supervised by POR_X.
This supply monitor has a configurable threshold. If a TCXO is used the threshold has to be set according to the
supply or enable voltage of the TCXO supplied by LDO_X_OUT.
After release of POR_C the systems waits for 2048 clock cycles to occur before the clock signal is fed into the
core. This ensures system operation begins with a clean stable clock signal.
An additional supply monitor at pin VDD_IO, the VDD_IO_OK, switches the supply of the backup domain from
VDD_IO to V_BCKP, once VDD_IO falls below its operational specification. Thus, a separate supply source (at
V_BCKP) can be used to maintain RTC and backup RAM information even if VDD_IO fails.
2.1.4 Operating Modes
2.1.4.1 Continuous Mode
Continuous Mode uses the acquisition engine at full performance resulting in the shortest possible TTFF and the
highest sensitivity. It searches for all possible satellites until the Almanac is completely downloaded. The receiver
then switches to the tracking engine to reduce power consumption.
Thus, a lower tracking current consumption level will be achieved when:
A valid position is obtained
The entire Almanac has been downloaded
The Ephemeris for each satellite in view is valid
For best GNSS performance use Continuous Mode.
2.1.4.2 Power Save Mode
u-blox 7 GPS/ GNSS receivers include two Power Save Mode operations called ON/OFF and Cyclic tracking that
allow reducing the average current consumption in different ways to match the needs of the specific application.
Both operations can be set and configured by sending the corresponding UBX messages to the receiver. For
more information, please see the u-blox 7 Receiver Description including Protocol Specification [3]
In Power Save Mode, the supply voltages (V_CORE and VDD_IO) must remain inside operating conditions. The
system may shut down an optional external LNA by the ANT_ON signal to optimize the power consumption, see
section 2.6.2.2.
Use of the USB Interface is not recommended with Power Save Mode since the USB standard does not
allow a device to be non-responsive and hence must be continuously active. Thus it is not possible to
take full advantage of Power Save Mode operations in terms of saving current consumption.
Power Save Mode requires the RTC to be maintained. This can be achieved by connecting an external
RTC crystal or deriving the RTC via the main clock using the “single crystal” feature. - See section 2.5.
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2.2 PIOs
There are 17 PIOs, PIO0 to PIO16, available on the UBX-G7020. All the PIOs are supplied by VDD_IO, thus all the
voltage levels of the PIO pins are related to VDD_IO supply voltage. All the inputs have internal pull-up resistors
in normal operation. Thus PIOs can be left open if not used.
The PIOs functions comprise the communication interfaces, antenna supervision, some configuration, the time
pulse and interrupt signals.
PIO
#
Default
Function
I/O
Remarks
Alternative
Functions
0
SQI_D0 or
CFG_FFU2
I/O
I
Data line 0 to external SQI FLASH or reserved configuration pin
In case PIO5 is GND (no SQI flash used) it acts as a reserved configuration pin
1
SQI_D1 or
CFG_DCDC
I/O
I
Data line 1 to external SQI FLASH or configuration pin
In case PIO5 is GND (no SQI flash used) it acts as a configuration pin to enable DCDC
converter
2
SQI_D2 or
CFG_OSC3
I/O
I
Data line 2 to external SQI FLASH or configuration pin
In case PIO5 is GND (no SQI flash used) it acts as an oscillator configuration pin
3
SQI_D3 or
CFG_OSC2
I/O
I
Data line 3 to external SQI FLASH or configuration pin
In case PIO5 is GND (no SQI flash used) it acts as an oscillator configuration pin
4
SQI_CLK or
CFG_OSC1
O
I
Clock for external SQI FLASH or configuration pin
In case PIO5 is GND (no SQI flash used) it acts as an oscillator configuration pin
5
SQI_CS or
CONFIG_SEL
I/O
I
Chip select for external SQI FLASH or configuration enable pin
If low at startup (no SQI flash used) PIO0 to PIO4 become configuration pins
6
TX or
MISO
O
O
UART TX or SPI MISO
Depends on PIO10 (D_SEL) status
TX-ready
7
RX or
MOSI
I
I
UART RX or SPI MOSI
Depends on PIO10 (D_SEL) status
8
SCL or
SCK
O
O
DDC clock or SPI clock
Depends on PIO10 (D_SEL) status
9
SDA or
CS_N
I/O
O
DDC data or SPI chip select
Depends on PIO10 (D_SEL) status
10
D_SEL
I
Communication interface selection pin
Selects the communication interface available on PIO6 to PIO9
11
TIMEPULSE1
O
Time pulse 1 output, 1pps
12
SAFEBOOT_N
I
If low at startup the receiver will start in Safe Boot Mode. Used in production for
setting the Low Level Configuration, programming the SQI flash and testing purposes.
TIMEPULSE2
13
-
I
No function by default, leave open
EXTINT0,
TX-ready
14
-
I
No function by default, leave open
EXTINT1,
ANT_DET,
TX-ready
15
ANT_OK
I
Antenna status of antenna supervisor
ANT_SHORT_N,
UART_TX,
TX-ready
16
ANT_OFF
O
Antenna power control of antenna supervisor
UART_RX,
TX-ready
Table 1: PIO overview
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2.2.1 SQI Flash memory
An SQI (Serial Quad Interface) flash memory can be connected to the SQI interface (PIO0–PIO5) to provide the
following options:
Run firmware out of the SQI flash and have the possibility to update the firmware
Save data logging results
Store the Functional Configuration permanently
Save the Low Level Configuration (system configuration)
Hold AssistNow Offline data
If updating of the firmware is a prime requirement then an SQI flash must be connected.
Some UBX-G7020 features may be only available with a particular Flash Firmware.
The voltage level of the SQI interface follows the VDD_IO level. Thus make sure the SQI Flash is supplied with the
same voltage as VDD_IO of the UBX-G7020. It is recommended to place a decoupling capacitor (C2) close to the
supply pin of the SQI flash.
Make sure that the SQI Flash supply range matches the voltage supplied at VDD_IO.
Figure 6: Connecting a SQI FLASH memory
Not all the SQI flash devices supported by the UBX-G7020 can be used to do logging, see section 3.4.
To run the firmware out of the SQI flash a minimum size of 4Mb is required. A 4Mb device is also sufficient to
save AssistNow Offline information plus the Low Level Configuration and functional configuration data.
However, to run Firmware from the SQI flash and provide space for logging results, a minimal size of 8Mb is
required. If, on the other hand the SQI flash is just used for logging results and the firmware runs out of ROM, a
4Mb SQI flash can provide reasonable space for logged data.
For a list of supported SQI Flash devices please see Table 19.
There is a configurable VDD_IO monitor threshold (POR_IO) to ensure that the UBX-G7020 only starts if the
VDD_IO supply (which is used to supply the SQI flash), is within the supply range of the SQI flash device. This will
ensure that any connected Flash memory will be detected correctly at startup.
The VDD_IO monitor threshold (POR_IO) must be set according to the SQI supply voltage level (VDD_IO)
in the eFuse by the Low Level Configuration, see section 2.10.2!
Place the SQI FLASH close to the UBX-G7020 chip to keep the interface lines short and if possible route them on
inner layers to avoid noise emission. Also make sure that all the lines are not too-long/ too-thick to reduce
capacitance/ time delays.
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At initial start up in production, the UBX-G7020 will not have information about the supply voltage or oscillator
settings required and hence may not be able to start up without this information. Hence an initial power-up
requires starting in Safe Boot Mode in which the receiver runs from an internal ring oscillator. Then the Low
Level Configuration can be set in the eFuse or in the SQI flash. See section 2.2.6 and section 2.10.2.
Make sure the SAFEBOOT_N pin (PIO12) is made available to enter the Safe Boot Mode, a pre-requisite
to program the flash and preset the Low Level Configuration in production.
2.2.2 Configuration pins
If no SQI flash is connected, there is a configuration enabling pin (PIO5) which activates 5 configuration pins
PIO0 to PIO4. These pins allow setting some essential oscillator and power supply (DCDC converter)
configurations.
PIO5 connected to GND will enable configuration pins at PIO0 to PIO4!
PIO0 is reserved and must be left open when no SQI Flash is employed.
All the configuration pins have internal pull-ups. Any left open equates to a logical “1”.
PIO5
Configuration
Remarks
1(open)
Configuration pins disabled
The configuration done by PIO0 to PIO4 is ignored.
0(GND)
Configuration pins enabled
Table 2: Enable configuration pins
PIO1
Configuration
Remarks
1(open)
DCDC converter disabled
0(GND)
DCDC converter enabled
Requires additional circuitry
Table 3: DCDC converter configuration pin
PIO2
PIO3
PIO4
Configuration
Remarks
1(open)
1(open)
1(open)
Crystal 19pF load
0(GND)
1(open)
1(open)
Reserved
1(open)
0(GND)
1(open)
Reserved
0(GND)
0(GND)
1(open)
Reserved
1(open)
1(open)
0(GND)
LDO_X_OUT = 3.01V
LDO_X_OUT supplies and enables the 3V TCXO.
0(GND)
1(open)
0(GND)
LDO_X_OUT = 1.91V
LDO_X_OUT supplies and enables the 1.8V TCXO.
1(open)
0(GND)
0(GND)
LDO_X_OUT = 2.69V
LDO_X_OUT used to enable the 3V TCXO; TCXO supplied directly by
same voltage as used to supply VDD_IO.
0(GND)
0(GND)
0(GND)
LDO_X_OUT = 1.67V
LDO_X_OUT used to enable the 1.8V TCXO; TCXO supplied directly
by same voltage as used to supply VDD_IO.
Table 4: Oscillator configuration pins
For oscillator circuits and recommendations see section 2.4!
PIO0 is reserved for further use. Leave it open.
For further information about the Low Level Configuration of the UBX-G7020 see section 2.10.2.
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2.2.3 Communication interfaces
A UART, SPI and DDC (I2C compatible) interface is available to communicate with a host on the UBX-G7020.
There is also a USB interface available on dedicated pins, see section 2.7.
The UART, SPI and DDC pins are supplied by and operate at VDD_IO voltage levels.
There are 4 pins (PIO6 to PIO9) to provide a UART, DDC and SPI interface for communication with a host CPU.
These 4 PIOs can be configured as either 1 x UART and 1 x DDC or a single SPI interface selectable by the PIO10
(D-SEL pin). Table 5 below provides the port mapping details.
If the SPI port is used for communication to a host CPU, there is the possibility to configure the UBX-G7020 so
that the UART is mapped to PIO15 and PIO16. Thus the UART can be used as a debug interface or a second
communication interface if needed. To remap the UART use the Low Level Configuration, see section 2.10.2 and
u-blox 7 Receiver Description including Protocol Specification [3].
PIO #
PIO10 (D_SEL) = “high”
(left open)
PIO10 (D_SEL) = “Low”
(connected to GND)
PIO10 (D_SEL) = “Low”
(connected to GND) and
UART remapped
PIO6
UART TX
SPI MISO
SPI MISO
PIO7
UART RX
SPI MOSI
SPI MOSI
PIO8
DDC SCL
SPI CLK
SPI CLK
PIO9
DDC SDA
SPI CS
SPI CS
PIO15
ANT_OK
ANT_OK
UART TX
PIO16
ANT_OFF
ANT_OFF
UART RX
Table 5: Communication Interfaces overview
It is not possible to have both the DDC and SPI interfaces active simultaneously for communication with
a host.
For debugging purposes it is recommended to have a second interface independent from the
application available via test-points.
The optional remapped UART interface is not available in Safe Boot Mode, see section 2.2.6.
For each interface, a dedicated pin can be defined to indicate that data is ready to be transmitted. This Tx-ready
pin can be mapped to any unused PIO pin. Each Tx-ready pin is associated with a particular interface and cannot
be shared. If the nominated PIO has another function by default, it needs to be disabled before configuring the
Tx-ready signal to that PIO pin. For configuration of the Tx-ready feature see u-blox 7 Receiver Description
including Protocol Specification [3].
2.2.3.1 UART interface
A UART interface is available for serial communication to a host CPU. The UART interface supports configurable
data rates of which the default is 9600 baud. The signals levels are related to VDD_IO supply voltage. An
interface based on RS232 standard levels (+/- 7 V) can be realized using level shifter ICs such as the Maxim
MAX3232.
Hardware handshake signals and synchronous operation are not supported.
A signal change on the UART RX pin can also be used to wake up the receiver in Power Save Mode (see u-blox 7
Receiver Description including Protocol Specification [3].).
The UART can be permanently remapped by Low Level Configuration to PIO15 and PIO16, see section
2.10.2.
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2.2.3.2 Display Data Channel (DDC) Interface
An I2C compatible Display Data Channel (DDC) interface is available for serial communication with a host CPU.
The PIO8 (SCL) and PIO9 (SDA) pins have internal pull-up resistors sufficient for most applications. However,
depends on the speed of the host and the load on the DDC lines it might happen that additional external pull-up
resistors are necessary.
To make use of DDC interface the PIO10 (D_SEL) has to be left open.
The UBX-G7020 DDC interface provides serial communication with u-blox LEON-G100/G200 wireless
modules from version LEON-G100/G200-05S and above and on all LISA modules.
The TX-ready feature is supported on version LEON FW 7.xx and LISA-U2 01S and above.
For more information about DDC implementation refer to the u-blox 7 Receiver Description including Protocol
Specification [3].
2.2.3.3 SPI Interface
The SPI port provides a serial communication interface with a host CPU.
To make use of the SPI interface, PIO10 (D_SEL) has to be connected to GND.
2.2.3.4 Electromagnetic interference on interface signal lines
Any interface signal line (length > ~3 mm) may pick up high frequency signals and transfer this noise into the
GPS/GNSS receiver. This specifically applies to unshielded lines, lines were the corresponding GND layer is remote
or missing entirely, and lines close to the edges of the printed circuit board. If a GSM signal radiates into an
unshielded high-impedance line, noise in the order of Volts can be generated and eventually not only distort
receiver operation but also damage it permanently.
In such case it is recommended to use feed-thru capacitors with a good GND connection close to the GPS/GNSS
receiver in order to filter such high-frequency noise. See Section 3.19 for component recommendations.
Alternatively, ferrite beads (see Section 3.18) can be used. These work without GND connection but may
adversely affect signal rise time.
EMI protection measures are recommended when RF emitting devices are near the GPS/GNSS receiver. To
minimize the effect of EMI a robust grounding concept is essential. To achieve electromagnetic robustness follow
the standard EMI suppression techniques. Some references are provided in [4] and [5].
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