United Electronic Industries DNA 429-512 User manual

DNx 429-512/566
—
User Manual
12-Channel ARINC 429 Transmitter/Receiver
Interface Layer
for the PowerDNA Cube and PowerDNR RACKtangle
Release 4.5
December 2013
PN Man-DNx-429-512/566-1213
© Copyright 1998-2013 United Electronic Industries, Inc. All rights reserved.

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WARNING!
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COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
Products sold by United Electronic Industries, Inc. are not authorized for use as critical components in
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DNA/DNR-429-512/566 ARINC 429 Layer
Contents i
Tel: [phone] www.ueidaq.com Vers: 4.5
Date: December 2013 DNx-429-ManualTOC.fm
© Copyright 2013
United Electronic Industries, Inc.
Table of Contents
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Organization of Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 The 429-512/566 Interface Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.6 Device Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.6.1 Word Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.6.2 Receiver Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.7.3 Label Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.8.4 Transmitter Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.8.5 Scheduler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.9 Wiring & Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 2 Programming with the High Level API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1 Creating a Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2 Configuring the Resource String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3 Configuring the Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4 Read Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5 Write Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.6 Programming the Output Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.7 Program the Label Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.8 Cleaning-up the Session. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Chapter 3 Programming with the Low-level API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

DNA/DNR-429-512/566 ARINC 429 Layer
Figures ii
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Date: December 2013 DNx-429-ManualLOF.fm
© Copyright 2013
United Electronic Industries, Inc.
List of Figures
1-1 Typical Schematic Diagram for FET Digital Output (DOUT0)....................................... 3
1-2 The DNA-429-512/566 ARINC-429 Layer .................................................................... 4
1-3 DNA/DNR-429-512/566 Logic Block Diagram .............................................................. 6
1-4 ARINC 429 Waveform Characteristics.......................................................................... 7
1-5 General ARINC Word Format ....................................................................................... 8
1-6 Receiver Diagram ....................................................................................................... 11
1-7 Transmitter Block Diagram (Hardware Abstraction Layer) ......................................... 13
1-8 DNx-429-512/566 Pinout Diagram.............................................................................. 17

DNA/DNR-429-512/566 ARINC 429 Layer
Chapter 1 1
Introduction
Tel: [phone] www.ueidaq.com Vers: 4.5
Date: December 2013 DNx-429-Chap1x.fm
© Copyright 2013
United Electronic Industries, Inc.
Chapter 1 Introduction
This document outlines the feature-set of the DNR- and DNA-429-512/566 layer
and its use for synchronous serial-line communications applications.
1.1 Organization
of Manual This 429-512/566 User Manual is organized as follows:
• Introduction
This section provides an overview of the 429-512/566 ARINC interface
board features, device architecture, and connectivity.
• Programming with the High-Level API
This chapter provides an overview of the how to create a session,
configure the session, and format relevant data with the Framework API.
• Programming with the Low-Level API
Describes low-level API commands for configuring and using the 429-
512/566 series layer for serial operating modes.
• Appendix A - Accessories
This appendix provides a list of accessories available for use with the
DNx-429-512/566 serial-line communication interface board.
• Index
This is an alphabetical listing of the topics covered in this manual.

DNA/DNR-429-512/566 ARINC 429 Layer
Chapter 1 2
Introduction
Tel: [phone] www.ueidaq.com Vers: 4.5
Date: December 2013 DNx-429-Chap1x.fm
© Copyright 2013
United Electronic Industries, Inc.
Manual Conventions
To help you get the most out of this manual and our products, please note that
we use the following conventions:
Tips are designed to highlight quick ways to get the job done or to reveal
good ideas you might not discover on your own.
NOTE: Notes alert you to important information.
CAUTION! Caution advises you of precautions to take to avoid injury, data loss,
and damage to your boards or a system crash.
Text formatted in bold typeface generally represents text that should be entered
verbatim. For instance, it can represent a command, as in the following
example: “You can instruct users how to run setup using a command such as
setup.exe.”
Text formatted in fixed typeface generally represents source code or other text
that should be entered verbadim into the source code, initialization, or other file.
Examples of Manual Conventions
Before plugging any I/O connector into the Cube or RACKtangle, be
sure to remove power from all field wiring. Failure to do so may
cause severe damage to the equipment.
Usage of Terms
Throughout this manual, the term “Cube” refers to either a PowerDNA Cube
product or to a PowerDNR RACKtanglerack mounted system, whichever is
applicable. The term DNR is a specific reference to the RACKtangle, DNA to the
PowerDNA I/O Cube, and DNx to refer to both.

DNA/DNR-429-512/566 ARINC 429 Layer
Chapter 1 3
Introduction
Tel: [phone] www.ueidaq.com Vers: 4.5
Date: December 2013 DNx-429-Chap1x.fm
© Copyright 2013
United Electronic Industries, Inc.
1.2 The 429-512/
566 Interface
Board
The DNA- and DNR-429-512/566 layer is a 12-channel ARINC transmit/receive
interface for the Cube/RACKtangle I/O chassis respectively, designed for serial
communication in avionics applications using the ARINC 429 protocol. It has 12
ARINC 429 channels that can be specified in either of two configurations: (1) as
6 TX and 6 RX channels (DNx-429-566), or (2) 12 RX channels (DNx-429-512).
The boards comply with the ARINC 429 specification and can run at either high
speed (100 kHz) or low speed (12.5 kHz). The speed is software-selectable on
a per port pair basis (see page 10). To ensure data integrity, 256-word FIFOs are
provided on every TX and RX channel.
In addition, the DNx-429-566/512 ARINC layer has 3x current sinking (350 mA
max), low-side FET, general purpose digital output with 500 mA resettable fuse.
Software supplied with the boards permits you to select options such as:
•Receive Filter size (1 to 255) or disable
•Source/Destination filter (SDI) enable/disable
•“Forward changed data only” filter enable/disable
•Parity check enable/disable
•Date/Time Stamping enable/disable by label or globally
•Transmit mode – Scheduled or Asynchronous
•Scheduling Table size – Up to 256 labels per channel
•Asynchronous TX Modes –
High priority – transmit immediately regardless of schedule
Standard priority – transmit when no scheduled data is present
FIFO based – transmit when no other data is being sent
With this layer, you can realize the benefits of using a UEI Cube in avionics
applications in any of its forms — PowerDNA, UEILogger, or UEIPAC — with
communications handled by the ARINC 429 protocol.

DNA/DNR-429-512/566 ARINC 429 Layer
Chapter 1 4
Introduction
Tel: [phone] www.ueidaq.com Vers: 4.5
Date: December 2013 DNx-429-Chap1x.fm
© Copyright 2013
United Electronic Industries, Inc.
1.3 Features The common features of the DNx-429-512/566 are listed below:
•12 ARINC 429 channels configured as 6TX/6RX channels
(DNA-429-566) or 12 RX channels (DNA-429-512)
•High Current (350 mA max), Low-Side FET General Purpose Digital
Output with 500 mA resettable fuse
•High Speed (100 kHz) or Low Speed (12.5 kHz), selectable per port pair
•Hardware Label filtering
•Hardware Transmit Scheduler (100 uS timing resolution)
•Automatic timestamping of data, software enabled/disabled
•Tested to withstand 5g Vibration, 50g Shock, -40 to +85°C Temperature,
and Altitude up to 70,000 ft or 21’000 meters.
•Weight of 104 g or 3.7 oz for DNA-429-512/566; 4.1 oz for DNR-429.
•UEI Framework Software API may be used with all popular Windows
programming languages and most real time operating systems such as
RT Linux, RTX, or QNX and graphical applications such as LabVIEW,
MATLAB, DASYLab and any application supporting ActiveX or OPC.
1.4 Indicators A photo of the 429-512/566 unit is illustrated below.
The front panel has two LED indicators:
•RDY: indicates that the layer is receiving power and operational.
•STS: can be set by the user using the low-level framework.
DB-37 (female)
37-pin I/O connector
RDY LED
STS LED
DNA bus
connector
Figure 1-1. The DNA-429-512/566 ARINC-429 Layer

DNA/DNR-429-512/566 ARINC 429 Layer
Chapter 1 5
Introduction
Tel: [phone] www.ueidaq.com Vers: 4.5
Date: December 2013 DNx-429-Chap1x.fm
© Copyright 2013
United Electronic Industries, Inc.
1.5 Specification The technical specification for the 429-512/566 is provided in the table below:
Table 1-1
Channel Configurations
/VNCFSPGDIBOOFMT 
%/" 59BOE39
%/" 59BOE39
"3*/$$PNQMJBODF 'VMMZDPNQMJBOUXJUI"3*/$
%JHJUBMPVUQVUT DVSSFOUTJOLJOH'&5CBTFE
%JHJUBMPVUQVUESJWF N"NBYN"SFTFUUBCMFGVTF
Receive Specifications
%BUBSBUF L)[PSL)[
'*'0TJ[F VQUPCJUXPSETVTFSTFMFDUBCMF
3FDFJWFmMUFSTJ[F UP-BCFMTPSEJTBCMFE
4%*mMUFS FOBCMFEPSEJTBCMFE
/FXEBUBPOMZmMUFS FOBCMFEPSEJTBCMFECZMBCFMPSHMPCBMMZ
1BSJUZDIFDLJOH FOBCMFEPSEJTBCMFE
%BUF5JNFTUBNQJOH FOBCMFEPSEJTBCMFECZMBCFMPSHMPCBMMZ
Transmit Specifications
%BUBSBUF L)[PSL)[
'*'0TJ[F XPSET
Transmit modes 4DIFEVMFEPSBTZODISPOPVT
Scheduler specifications
UJNJOHSFTPMVUJPO NJDSPTFDPOET
UBCMFTJ[F 4DIFEVMFVQUPMBCFMTQFSDIBOOFM
Asynchronous TX modes
)JHIQSJPSJUZ USBOTNJUJNNFEJBUFMZVQPODPNQMFUJPOPGDVSSFOU
USBOTNJTTJPOSFHBSEMFTTPGTDIFEVMF
4UBOEBSEQSJPSJUZ transmit when no scheduled data
'*'0CBTFE USBOTNJUXIFOOPTDIFEVMFETUBOEBSEPSIJHIQSJPSJUZ
EBUBJTCFJOHTFOU
General Specifications
-PPQCBDLUFTUJOH *OUFSOBMMPPQCBDLDPOOFDUJPOTPOUIF%/Y
BMMPXBVUPNBUJDTFMGUFTU
0QFSBUJOHUFNQFSBUVSF UFTUFE¡$UP¡$
7JCSBUJPOIEC 60068-2-6
IEC 60068-2-64
H)[TJOVTPJEBM
HSNT)[CSPBECBOESBOEPN
4IPDLIEC 60068-2-27 HNTIBMGTJOFTIPDLT!PSJFOUBUJPOT
HNTIBMGTJOFTIPDLT!PSJFOUBUJPOT
)VNJEJUZ UPOPODPOEFOTJOH
.5#' 
Power consumption 8BUUNBYJNVN
. DNx-429-512/566 Technical Specifications
* For 429-512 communication configuration (i.e. speed) is shared by every two two ports.
*For 429-566 communication configuration is individually selectable per port/channel.

DNA/DNR-429-512/566 ARINC 429 Layer
Chapter 1 6
Introduction
Tel: [phone] www.ueidaq.com Vers: 4.5
Date: December 2013 DNx-429-Chap1x.fm
© Copyright 2013
United Electronic Industries, Inc.
1.6 Device
Architecture The DNx-429-512/566 Layer has 6 parallel ARINC processors running at
66MHz. Sub-processor DSPs run inside each ARINC processor. A block
diagram of the board is shown in Figure 1-2.
Figure 1-2. DNA/DNR-429-512/566 Logic Block Diagram
As shown in the diagram above, each RX/TX block contains two ARINC
Receivers and one ARINC Transmitter. The ARINC Receiver/Transmitter and
communication protocol functions are handled by Holt (www.holtic.com)
HI-3282 serial transmitter/dual receiver chips (for both the 429-512 and -566)
and associated HI-8585 line drivers (for the 429-566 output only).
Filter bypass
Speed selector, error reporting, etc.
TX0 channel FPGA/DSP block
Speed selector, error reporting, etc.
TX Port
Access Controller
RX0 channel FPGA/DSP block
2RX/1TX ARINC-429 transceiver protocol controllers (FPGA/DSP control/access Block 0)
SDI Filter Label
Acceptance
Filter
RX FIFO
with
Timestamp
ARINC-429 (RX/TX Block 1)
ARINC-429 (RX/TX Block 2)
ARINC-429 (RX/TX Block 3)
ARINC-429 (RX/TX Block 4)
ARINC-429 (RX/TX Block 5)
RX6 channel FPGA/DSP block
data
data
data
control
control
control
status
status
status
ARINC 429
Receiver RX0
ARINC 429
Transmitter TX0
ARINC 429
Receiver RX1
Scheduler
Timebases(2)
FIFO
Timebase
256 x 25
Entries
Scheduler
Commands
256 x 32
Entries
Scheduler
Data 256 x 32
TX FIFO
Low Priority
Bypass Data High Priority
Bypass Data
ARINC Protocol Controller
Standard DNA CLI
– in 2RX configuration, RX6 is same as RX0
– in 1RX/1TX configuration, RX6 is used for loopback control
of TX0 channel
Trigger
Input 0
Output 0
Input 6
loopback
NOTE: Block 0 has 3 ports: TX0, RX0, RX6
Block 1 has 3 ports: TX1, RX1, RX7
Block 2 has 3 ports: TX2, RX2, RX8
Block 3 has 3 ports: TX3, RX3, RX9
Block 4 has 3 ports: TX4, RX4, RX10
Block 5 has 3 ports: TX5, RX5, RX11

DNA/DNR-429-512/566 ARINC 429 Layer
Chapter 1 7
Introduction
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Date: December 2013 DNx-429-Chap1x.fm
© Copyright 2013
United Electronic Industries, Inc.
As stated in the ARINC specification, the following detection levels are required
for the three signal states:
State Differential Voltage
ONE +6.5 V to +13 V
NULL +2.5 V to -2.5 V
ZERO -6.5 V to -13 V
If the received signal for any state is outside the specified range, the chip
rejects the data.
The board can operate at either of two speeds, 100kHz or 12.5kHz, which is
software selectable on a per channel or port pair basis (see page 10). The
transmission medium for an ARINC 429 bus is 78-ohm, twisted, shielded-pair
cable, grounded at both ends and at any break in the cable shield. Each bus
has only one transmitter and up to 20 receivers. Since data transmission is uni-
directional only, transmitters and receivers are on separate ports.
The waveform characteristics must conform to the specifications illustrated in
Figure 1-3.
CD
A First half of pulse 5usec ± 5% B/2 ± 5%
B Full pulse cycle 10 usec ±2.5% 1/bit rate ± 5%
C Pulse Rise Time 1.5 ±0.5 usec 10 ± 5 usec
D Pulse Fall Time 1.5 ±0.5 usec 10 ± 5 usec
Received
Voltage
HI 6.5V to 13 V
NULL -2.5V to +2.5V
LOW -6.5V to -13V
Hi Speed Low Speed
HI
NULL
LOW
TRANSMITTED VOLTAGE
A
B
Figure 1-3. ARINC 429 Waveform Characteristics

DNA/DNR-429-512/566 ARINC 429 Layer
Chapter 1 8
Introduction
Tel: [phone] www.ueidaq.com Vers: 4.5
Date: December 2013 DNx-429-Chap1x.fm
© Copyright 2013
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1.6.1 Word Format Each ARINC-429 BNR word is a 32-bit value containing 5 fields, as shown in
Figure 1-4.
Figure 1-4. General ARINC Word Format
The bits have the following meanings:
•Bit 32 — parity bit, used to determine validity of word
•Bits 31, 30 — Sign/Status Matrix (SSM), indicates status of data
OP [1 1] indicates data is normal
TEST [1 0] indicates data comes from a test source
FAIL [0 0] indicates a hardware failure causing data to be missing
NCD [0 1] indicates data missing because of non-hardware reason
•Bits 11 to 29 — contain the data (bit-field, BCD, BNR, or mixed)
•Bits 9 and 10 — Source/Destination Identifiers (SDI) indicate the
intended receiver or the transmitter sending the data
•Bits 1 to 8 — a label, in octal, identifying the data type
NOTE: Use of SDI and SSM is not mandatory.
Although the order in which bits are transmitted/received is somewhat complex,
the HI-3282 chips handle the decoding automatically. The bits are transmitted on
the ARINC bus in the following order.
8,7,6,5,4,3,2,1, 9,10,11,12, . . . 32
The Label (first 8 bits) is transmitted before the data (MSB first). After the label
is sent, the LSB of each byte is transmitted first.
1.6.1.1 Scheduler
ARINC Data
Format
The Scheduler ARINC Data Format is as shown in the table below.
ARINC data is transferred via the ARINC-429 bus whenever a corresponding
scheduler command entry is set for execution.
ARINC data should be preformatted in a form that is common for industry
protocol controllers such as the Holt HI-3282.
Note that the ARINC serial communication standard numbers bits from 32
(MSB) to 1 (LSB). The UEI DNx-429-566/512 numbers them from 31 to 0, and
the Holt controllers use two 16-bit words with bits numbered from 15 to 0. Also
note that only LABEL, PARITY, SSM, and SDI bits are strictly defined by the
ARINC-429 standard. The rest of the bits may be used as a payload by various
sub-protocols.
SDIDISCRETESPADDATASSMP
LSBMSB
LABEL
132 31 30 29 11 10 9 8
Bit Name Description Reset State
31-0 ADATA ARINC data 0

DNA/DNR-429-512/566 ARINC 429 Layer
Chapter 1 9
Introduction
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© Copyright 2013
United Electronic Industries, Inc.
The table below illustrates the differences in bit numbering for various protocols.
Table 1-2. Differences in Bit Numbering for Various Protocols
Holt
Bit No. DNA Bit No. ARINC Standard
Bit No.
Name Description
15 Word
2
31 29 SIGN Sign Bit
14-0 30-16 28-14 DATA 15 main data bits
15-13 Word
1
15-13 13-11 DATA 3 additional data bits
12-11 12-11 10-9 SDI Source/Destination Identifier,
2-bit field used as an additional
filter, programmed by a direct
write to the HI-3282 configur-
ation word and a write to the
AR566_ARDA0 register.
10-9 10-9 31-30 SSM Sign/Status matrix or data bits.
See ARINC-429 protocol
documentation for details.
8832PARITY Parity bit – auto inserted by the
transmitter and calculated by
the receiver. Normal parity for
the ARINC-429 is “odd”. (Parity
bit should be set if the number
of “1”s in the rest of the bits is
even, and should be cleared if
not.) DNA-429 layers support
even, odd, or no parity modes
(the ARINC standard is “odd”
parity). In “no parity” mode, the
PARITY bit is transmitted to the
bus, but is ignored.
771LABEL Label — This bit is used to
identify data types and
associated parameters. DNA-
429 layers have a very flexible
acceptance filter with an option
to put only “new” data into the
FIFO or to trigger the Scheduler
when the selected label is
received.
When SDI bits are enabled, the
Label Filter functions as a 10-bit
identifier.
662
553
444
335
226
117
008

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For the parity bit above, transmission and reception have different behaviors:
•Transmit: parity can be selected to be Odd, Even, or None.
Selecting Odd/Even enables parity bit insertion into transmitter data bit
32. The parity generator counts the ONES in the 31-bit word. If Odd is
selected, the 32nd bit transmitted will make parity odd. If Even is
selected, the parity is even. The parity bit is automatically set and you
can't "force" it when sending a label. If None is selected, data is inserted
on bit 32 (taking whatever bit 32 you supply).
•Receive: parity bit is is calculated by the chip, the value from the bus is
not used. The receiver parity circuit counts 1’s received, including the
parity bit, ARINC bit 32. If the result is odd, then "0" will appear in bit 32.
When receiving, the received parity bit is matched against the expected
value. If the received data is correct and parity is even, then the parity bit
should be 1 in the received word; if it is 0 it is a parity error. If the parity
is odd it should be 0; and error is 1. If the parity is disabled it sets zero or
one (depending on calculations) and you need to re-calculate parity for
bits 1-31 to deduce the actual value of the transmitted parity bit.
1.6.2 Receiver
Block As indicated in Figure 1-2 on page 6, the RX0 receiver in each Building Block
has a software-selectable label acceptance filter that accepts or rejects
incoming data words. As an option, you can choose to accept only “changed
data”. This option uses the “last received data” memory and places only
“changed” data into the receive FIFO. Unchanged data is discarded. The RX
FIFO can store up to 256 last received ARINC-429 32-bit frames, if
timestamping is not selected. If timestamping is selected, the RX FIFO is limited
to 128 frames and 128 timestamps. If the label filter is not selected, data is
placed directly into the 256-word FIFO.
Each building block shares communication configuration settings. This means
that the RX0, RX6, and TX0 of Building Block 1 share speed settings. Thus on
the 429-512 the pair of receivers (RX0 and RX6) will use the same speed. The
429-566 RX0 and TX0 channel also uses the same speeds.
The receivers are electrically connected in different ways on the 429-512 and
566. On the 429-512 board each of the two receivers is individually addressable.
If the board is a -566 version, however, (one receiver and one transmitter per
channel), the second receiver is used as a loopback controller for the associated
transmitter. To make the Loopback Connection between a TX1 and its
associated loopback RX1 on the -566 version, you must set up a port on the
channel.

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Figure 1-5. Receiver Diagram
Figure 1-5 is a block diagram of an ARINC receiver function. As illustrated,
received data may be placed directly into the 256-word FIFO by writing 0x0 in
the first label entry or may be passed through the label filter and the data change
filter before being accepted. Similarly, the parity checker and last data checker
can also be bypassed, if desired.
DNx ARINC-429 Receiver
ARINC-429 Receiver Hardware
Raw Frame
255 entry
Label Acceptance
Filter
Timestamp Source
Parity Error
Bit Checker
Data Change
Checker
RX FIFO
Trigger
Generator
“Last Data”
Memory
RX Frame Counter (32-bit)
0x0 in the first entry
disables/bypasses filter.
entries skips them in
the verification/
acceptance process.
for the Scheduler.
Available only for
the RX0 receivers.
(256 x 32)
(256 x 32)
Counts one of the following: all frames accepted by the
label filter, parity error-free frames, frames placed into
verifies received
ARINC-429
frame against
“last data” value.
32-bit counter running
from sub-divider for
the 66 MHz clock,
shared across all RX
channels. Resolution
the FIFO, trigger initiator frames, or parity errors.
varies from 1 us to
1 second.
0x0 in subsequent

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1.7.3 Label
Acceptance
Filter
The Label Acceptance Filter is a table with 255 10-bit entries. Table 1-3
describes the format of each entry.
Table 1-3. Label Acceptance Filter
Bit Name Description Reset
State
31-9 RSV Reserved/unused (should be written with 0 for
compatibility with future enhancements)
0
9TE Trigger Enable.
•For RX0 only. A “1” in this bit indicates that a
Scheduler entry with the same index should
be set for execution (scheduled for output on
the ARINC-429 bus). Note that only the
“master” entry in the Scheduler may be
triggered this way.
•For RX1, this bit is ignored.
8ND “New Data Only” flag. In “new data only” mode (set
via RX0 Control Register AR566_Rx, and if this bit is
set, only data that has changed since last reception is
placed into the FIFO and the “last data” memory.
NOTE: For the 566 model, the “new data only” mode
is not available on loopback receivers.
0
7LABEL Acceptance label. If the label matches bits 7-0 of the
received frame, the frame is accepted by the filter.
NOTE:
1. 0x0 in the label and flag fields of first entry (with
index 0) in this table disables filtering, causing
the board to accept all ARINC data. If the FIFO
receiver is programmed to reject frames with par-
ity errors, however, such frames are still rejected.
2. 0x0 in any label other than those with index 0 dis-
ables the entry in the label acceptance filter.
When this occurs, the next entry is processed
instead.
3. Labels may be programmed, enabled, or dis-
abled at any time during operation.
4. For the 566 model, the Label Filter feature is not
available when RX1 is used as a loopback
receiver.
0

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1.8.4 Transmitter
Block As shown in Figure 1-2 on page 6, the TX0 transmitter in each Building Block
contains a TX port access controller function, a Scheduler, a TX FIFO, and low-
and high-priority bypass data memory registers. Data is passed from this block
to the ARINC protocol controller and transmitter hardware for transmission to
designated receivers. A block diagram of the Hardware Abstraction Layer (HAL)
is shown in Figure 1-6.
Figure 1-6. Transmitter Block Diagram (Hardware Abstraction
Layer)
As illustrated in Figure 1-6, a transmitter block consists of a Scheduler, two
independent 16-bit prescalers, a 256-word output FIFO, and an emergency
transfer transmitter with a high- and a low-priority register.
The Scheduler transfers its data to the ARINC bus at a specified time interval
either one time or continuously at user-specified intervals. Scheduled data may
also be transferred in blocks based on a “master/slave” entry scheme. Also, the
Scheduler may be configured to transfer data when a predefined label with index
is received from the label filter.
The Prescalers are used to define the time delay for each master entry in the
schedule and may be disabled, keeping entries in the pause state.
Scheduler (256 entries)
High Priority Data
ARINC HAL
(Hardware Abstraction
Layer) access
engine
Low Priority Data
TX FIFO (256x32)
TX FIFO Timebase with “enable”
100 uS clock
Prescaler 0 (PS0)
with “enable”
Prescaler 1 (PS1)
with “enable”
ARINC-429
Hardware Protocol Controller
Timebase selection (100 uS, PS0,
PS1) is specified inside every entry.
Unconditionally triggers the
schedule-enabled “master” and all
related “slave” entries for
transmission over the ARINC-429
bus.
“Trigger”
from RX0
label filter

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The 256-word output FIFO runs at a lower priority than the Scheduler and may
output data in either of two modes: (1) whenever the interface IC can accept
data and none is available from the Scheduler or (2) on a “paced” mode, based
on user-defined clock intervals.
An Emergency Transfer Transmitter transfers data from the high-priority register
immediately after the current TX operation is completed, and from the low-
priority register only when the data from the Scheduler and high-priority register
are not available.
Transmitter sources are assigned ARINC bus access according to the following
priorities:
1. High-priority Data Register OR*1. FIFO
2. Scheduler Data2. Scheduler Data
3. Low-priority Data Register3. Low-priority Data Register
4. FIFO4. High-priority Data Register
The HAL accepts data based on the priority scheme above and sends
confirmation after the data is accepted for transmission
NOTE: *The Scheduler and FIFO priorities may be interchanged by setting the
FIFOHP bit in the AR566_ACCR register.
1.8.5 Scheduler The Scheduler is programmed using two arrays in the memory address space
dedicated to the Scheduler command and associated ARINC data.Because of
space limitations, the arrays all share the same memory locations and may only
be accessed one block at a time using the A566_TXFSR9 register as a selector.
The TX Scheduler ARINC data area occupies 256 32-bit locations and the
Scheduler Command/Status area occupies another 256 locations in layer
address space. Each command corresponds to one data location (the command
with index 0 corresponds to the data location with the matching index). Both
command and data areas allow read/write access and the command area, when
read, also incorporates status bits. Some of the status bits are “sticky.” To clear
them, the command entry must be re-written. As a general rule, the Scheduler
should be pre-programmed before enabling the ARINC transmitter, but may also
be changed at any time during operation.

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The Scheduler Command/status Format is shown in Figure 1-4 below.
Note that bits 31:22, 19,18 should be reset to 0 for correct operation and for
compatibility with future enhancements.
1.8.5.1 Bit
Descriptions Bit Descriptions for the Scheduler (see Figure 1-4) are as follows:
• PS1, PS0 – Prescaler/clock selector and entry disable flag
•00 (0)Entry disabled. Disabled entries are ignored by the Scheduler
•01 (1)Entry enabled and using 100uS clock as source for time delay
•10 (2)Entry disabled and using Prescaler 0
•11 (3)Entry enabled and using Prescaler 1
•If entry is “slave”, this field should match corresponding master entry
•MA— “Master” Bit. If set, indicates that entry is a “master” and when sched-
uled for output should also schedule all related slave entries for output at the
same time.
•RC— Recyclable Bit. If set, indicates that entry is recyclable. When sched-
uled for output, the internal value for the time delay counter is cleared and the
entry is output again when the time delay expires.
Table 1-4. Scheduler Command/Status Format
Bit Name Description Reset
State
31-25 RSV Reserved 0
24 ECO Status only, sticky,
=1 - Execution Completed Once
0
23 ME Status-only, =1 - Marked for execution 0
22 EO Status only, sticky,
=1 - Execution Overrun
0
21 PS1 PS1,PS0 - Prescaler Source/
Entry Disable: 00-Disabled
01 - 100 uS
10 - Prescaler 0
11 - Prescaler 1
0
20 PS0 0
19 RSV Reserved 0
18 RSV Reserved 0
17 MA =1 – Master Entry
=0 – Slave entry
16 RC =1 –Recyclable Entry
(valid if MA=1)
0
15-0 TD Time Delay for the selected clock
(valid if MA=1)
0

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•TD— 16-bit time delay. Used to set time intervals for output of master entries
(slave entries follow master entries in the schedule). This field is used as a
maximum value for the counter, which increments its value each time the
100uS clock or corresponding prescaler produces output. The actual clock
source is selected by the PS field.
NOTE: Another powerful feature of the DNx-429-566/512 layer is the ability to
generate a “cross-trigger” of the scheduled entry when a selected label
with the same index is accepted by Receiver 0 of the same ARINC
block. This feature, which may be user-enabled, works only for enabled
master entries and may be turned on/off by a dedicated bit in the label
filter. When a cross-trigger is detected, the corresponding entry is used
to set entries in the Scheduler that may be triggered by the receiver, as
clocked by prescaler 0 or 1, but which keep that prescaler disabled. In
such cases, only “cross-triggers” can set an entry for output.
Descriptions of the Status-only bits are as follows:
•ECO— “Execution Complete at Least Once”. If set, this bit indicates that the
entry was output by the ARINC transmitter at least once. This is a sticky bit
that can be cleared only by writing a command to the Scheduler. This com-
mand may change or may stay the same.
NOTE: Writing to the Scheduler command area clears some internal status bits.
It is recommended that you fill all 256 entries with initial information and
that you write 0x0 in all unused entries. The DNA-429-566/512
Scheduler command and data areas are accessible regardless of the
status of the LIOE (1<<31) bit in LCR and may be accessed at any time.
•ME— “Marked for Execution”. This bit is set by the time scheduler for the
entry marked for execution (pending transmission) and is cleared for exe-
cuted (transmitted) entries.
•EO— “Execution Overrun”. This bit indicates that a recyclable entry was
scheduled for execution while the ME bit was still set. If the EO bit is set, it is
likely that data is scheduled in such a way that the ARINC bus does not have
enough capacity to transfer it or that too much of the unscheduled data is
pumped through the transmit FIFO. This bit is a sticky bit that may be cleared
only by writing a command to the Scheduler. The command may change or
be the same. The EO bit also triggers an “execution overrun” interrupt for the
given transmitter.