United Electronic Industries DNA 429-512 User manual

DNx 429-512/566
—
User Manual
12-Channel ARINC 429 Transmitter/Receiver
Interface Layer
for the PowerDNA Cube and PowerDNR RACKtangle
Release 4.5
December 2013
PN Man-DNx-429-512/566-1213
© Copyright 1998-2013 United Electronic Industries, Inc. All rights reserved.

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WARNING!
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COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
Products sold by United Electronic Industries, Inc. are not authorized for use as critical components in
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DNA/DNR-429-512/566 ARINC 429 Layer
Contents i
Tel: [phone] www.ueidaq.com Vers: 4.5
Date: December 2013 DNx-429-ManualTOC.fm
© Copyright 2013
United Electronic Industries, Inc.
Table of Contents
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Organization of Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 The 429-512/566 Interface Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.6 Device Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.6.1 Word Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.6.2 Receiver Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.7.3 Label Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.8.4 Transmitter Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.8.5 Scheduler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.9 Wiring & Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 2 Programming with the High Level API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1 Creating a Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2 Configuring the Resource String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3 Configuring the Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4 Read Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5 Write Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.6 Programming the Output Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.7 Program the Label Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.8 Cleaning-up the Session. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Chapter 3 Programming with the Low-level API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

DNA/DNR-429-512/566 ARINC 429 Layer
Figures ii
Tel: [phone] www.ueidaq.com Vers: 4.5
Date: December 2013 DNx-429-ManualLOF.fm
© Copyright 2013
United Electronic Industries, Inc.
List of Figures
1-1 Typical Schematic Diagram for FET Digital Output (DOUT0)....................................... 3
1-2 The DNA-429-512/566 ARINC-429 Layer .................................................................... 4
1-3 DNA/DNR-429-512/566 Logic Block Diagram .............................................................. 6
1-4 ARINC 429 Waveform Characteristics.......................................................................... 7
1-5 General ARINC Word Format ....................................................................................... 8
1-6 Receiver Diagram ....................................................................................................... 11
1-7 Transmitter Block Diagram (Hardware Abstraction Layer) ......................................... 13
1-8 DNx-429-512/566 Pinout Diagram.............................................................................. 17

DNA/DNR-429-512/566 ARINC 429 Layer
Chapter 1 1
Introduction
Tel: [phone] www.ueidaq.com Vers: 4.5
Date: December 2013 DNx-429-Chap1x.fm
© Copyright 2013
United Electronic Industries, Inc.
Chapter 1 Introduction
This document outlines the feature-set of the DNR- and DNA-429-512/566 layer
and its use for synchronous serial-line communications applications.
1.1 Organization
of Manual This 429-512/566 User Manual is organized as follows:
• Introduction
This section provides an overview of the 429-512/566 ARINC interface
board features, device architecture, and connectivity.
• Programming with the High-Level API
This chapter provides an overview of the how to create a session,
configure the session, and format relevant data with the Framework API.
• Programming with the Low-Level API
Describes low-level API commands for configuring and using the 429-
512/566 series layer for serial operating modes.
• Appendix A - Accessories
This appendix provides a list of accessories available for use with the
DNx-429-512/566 serial-line communication interface board.
• Index
This is an alphabetical listing of the topics covered in this manual.

DNA/DNR-429-512/566 ARINC 429 Layer
Chapter 1 2
Introduction
Tel: [phone] www.ueidaq.com Vers: 4.5
Date: December 2013 DNx-429-Chap1x.fm
© Copyright 2013
United Electronic Industries, Inc.
Manual Conventions
To help you get the most out of this manual and our products, please note that
we use the following conventions:
Tips are designed to highlight quick ways to get the job done or to reveal
good ideas you might not discover on your own.
NOTE: Notes alert you to important information.
CAUTION! Caution advises you of precautions to take to avoid injury, data loss,
and damage to your boards or a system crash.
Text formatted in bold typeface generally represents text that should be entered
verbatim. For instance, it can represent a command, as in the following
example: “You can instruct users how to run setup using a command such as
setup.exe.”
Text formatted in fixed typeface generally represents source code or other text
that should be entered verbadim into the source code, initialization, or other file.
Examples of Manual Conventions
Before plugging any I/O connector into the Cube or RACKtangle, be
sure to remove power from all field wiring. Failure to do so may
cause severe damage to the equipment.
Usage of Terms
Throughout this manual, the term “Cube” refers to either a PowerDNA Cube
product or to a PowerDNR RACKtanglerack mounted system, whichever is
applicable. The term DNR is a specific reference to the RACKtangle, DNA to the
PowerDNA I/O Cube, and DNx to refer to both.

DNA/DNR-429-512/566 ARINC 429 Layer
Chapter 1 3
Introduction
Tel: [phone] www.ueidaq.com Vers: 4.5
Date: December 2013 DNx-429-Chap1x.fm
© Copyright 2013
United Electronic Industries, Inc.
1.2 The 429-512/
566 Interface
Board
The DNA- and DNR-429-512/566 layer is a 12-channel ARINC transmit/receive
interface for the Cube/RACKtangle I/O chassis respectively, designed for serial
communication in avionics applications using the ARINC 429 protocol. It has 12
ARINC 429 channels that can be specified in either of two configurations: (1) as
6 TX and 6 RX channels (DNx-429-566), or (2) 12 RX channels (DNx-429-512).
The boards comply with the ARINC 429 specification and can run at either high
speed (100 kHz) or low speed (12.5 kHz). The speed is software-selectable on
a per port pair basis (see page 10). To ensure data integrity, 256-word FIFOs are
provided on every TX and RX channel.
In addition, the DNx-429-566/512 ARINC layer has 3x current sinking (350 mA
max), low-side FET, general purpose digital output with 500 mA resettable fuse.
Software supplied with the boards permits you to select options such as:
•Receive Filter size (1 to 255) or disable
•Source/Destination filter (SDI) enable/disable
•“Forward changed data only” filter enable/disable
•Parity check enable/disable
•Date/Time Stamping enable/disable by label or globally
•Transmit mode – Scheduled or Asynchronous
•Scheduling Table size – Up to 256 labels per channel
•Asynchronous TX Modes –
High priority – transmit immediately regardless of schedule
Standard priority – transmit when no scheduled data is present
FIFO based – transmit when no other data is being sent
With this layer, you can realize the benefits of using a UEI Cube in avionics
applications in any of its forms — PowerDNA, UEILogger, or UEIPAC — with
communications handled by the ARINC 429 protocol.

DNA/DNR-429-512/566 ARINC 429 Layer
Chapter 1 4
Introduction
Tel: [phone] www.ueidaq.com Vers: 4.5
Date: December 2013 DNx-429-Chap1x.fm
© Copyright 2013
United Electronic Industries, Inc.
1.3 Features The common features of the DNx-429-512/566 are listed below:
•12 ARINC 429 channels configured as 6TX/6RX channels
(DNA-429-566) or 12 RX channels (DNA-429-512)
•High Current (350 mA max), Low-Side FET General Purpose Digital
Output with 500 mA resettable fuse
•High Speed (100 kHz) or Low Speed (12.5 kHz), selectable per port pair
•Hardware Label filtering
•Hardware Transmit Scheduler (100 uS timing resolution)
•Automatic timestamping of data, software enabled/disabled
•Tested to withstand 5g Vibration, 50g Shock, -40 to +85°C Temperature,
and Altitude up to 70,000 ft or 21’000 meters.
•Weight of 104 g or 3.7 oz for DNA-429-512/566; 4.1 oz for DNR-429.
•UEI Framework Software API may be used with all popular Windows
programming languages and most real time operating systems such as
RT Linux, RTX, or QNX and graphical applications such as LabVIEW,
MATLAB, DASYLab and any application supporting ActiveX or OPC.
1.4 Indicators A photo of the 429-512/566 unit is illustrated below.
The front panel has two LED indicators:
•RDY: indicates that the layer is receiving power and operational.
•STS: can be set by the user using the low-level framework.
DB-37 (female)
37-pin I/O connector
RDY LED
STS LED
DNA bus
connector
Figure 1-1. The DNA-429-512/566 ARINC-429 Layer

DNA/DNR-429-512/566 ARINC 429 Layer
Chapter 1 5
Introduction
Tel: [phone] www.ueidaq.com Vers: 4.5
Date: December 2013 DNx-429-Chap1x.fm
© Copyright 2013
United Electronic Industries, Inc.
1.5 Specification The technical specification for the 429-512/566 is provided in the table below:
Table 1-1
Channel Configurations
/VNCFSPGDIBOOFMT 
%/" 59BOE39
%/" 59BOE39
"3*/$$PNQMJBODF 'VMMZDPNQMJBOUXJUI"3*/$
%JHJUBMPVUQVUT DVSSFOUTJOLJOH'&5CBTFE
%JHJUBMPVUQVUESJWF N"NBYN"SFTFUUBCMFGVTF
Receive Specifications
%BUBSBUF L)[PSL)[
'*'0TJ[F VQUPCJUXPSETVTFSTFMFDUBCMF
3FDFJWFmMUFSTJ[F UP-BCFMTPSEJTBCMFE
4%*mMUFS FOBCMFEPSEJTBCMFE
/FXEBUBPOMZmMUFS FOBCMFEPSEJTBCMFECZMBCFMPSHMPCBMMZ
1BSJUZDIFDLJOH FOBCMFEPSEJTBCMFE
%BUF5JNFTUBNQJOH FOBCMFEPSEJTBCMFECZMBCFMPSHMPCBMMZ
Transmit Specifications
%BUBSBUF L)[PSL)[
'*'0TJ[F XPSET
Transmit modes 4DIFEVMFEPSBTZODISPOPVT
Scheduler specifications
UJNJOHSFTPMVUJPO NJDSPTFDPOET
UBCMFTJ[F 4DIFEVMFVQUPMBCFMTQFSDIBOOFM
Asynchronous TX modes
)JHIQSJPSJUZ USBOTNJUJNNFEJBUFMZVQPODPNQMFUJPOPGDVSSFOU
USBOTNJTTJPOSFHBSEMFTTPGTDIFEVMF
4UBOEBSEQSJPSJUZ transmit when no scheduled data
'*'0CBTFE USBOTNJUXIFOOPTDIFEVMFETUBOEBSEPSIJHIQSJPSJUZ
EBUBJTCFJOHTFOU
General Specifications
-PPQCBDLUFTUJOH *OUFSOBMMPPQCBDLDPOOFDUJPOTPOUIF%/Y
BMMPXBVUPNBUJDTFMGUFTU
0QFSBUJOHUFNQFSBUVSF UFTUFE¡$UP¡$
7JCSBUJPOIEC 60068-2-6
IEC 60068-2-64
H)[TJOVTPJEBM
HSNT)[CSPBECBOESBOEPN
4IPDLIEC 60068-2-27 HNTIBMGTJOFTIPDLT!PSJFOUBUJPOT
HNTIBMGTJOFTIPDLT!PSJFOUBUJPOT
)VNJEJUZ UPOPODPOEFOTJOH
.5#' 
Power consumption 8BUUNBYJNVN
. DNx-429-512/566 Technical Specifications
* For 429-512 communication configuration (i.e. speed) is shared by every two two ports.
*For 429-566 communication configuration is individually selectable per port/channel.

DNA/DNR-429-512/566 ARINC 429 Layer
Chapter 1 6
Introduction
Tel: [phone] www.ueidaq.com Vers: 4.5
Date: December 2013 DNx-429-Chap1x.fm
© Copyright 2013
United Electronic Industries, Inc.
1.6 Device
Architecture The DNx-429-512/566 Layer has 6 parallel ARINC processors running at
66MHz. Sub-processor DSPs run inside each ARINC processor. A block
diagram of the board is shown in Figure 1-2.
Figure 1-2. DNA/DNR-429-512/566 Logic Block Diagram
As shown in the diagram above, each RX/TX block contains two ARINC
Receivers and one ARINC Transmitter. The ARINC Receiver/Transmitter and
communication protocol functions are handled by Holt (www.holtic.com)
HI-3282 serial transmitter/dual receiver chips (for both the 429-512 and -566)
and associated HI-8585 line drivers (for the 429-566 output only).
Filter bypass
Speed selector, error reporting, etc.
TX0 channel FPGA/DSP block
Speed selector, error reporting, etc.
TX Port
Access Controller
RX0 channel FPGA/DSP block
2RX/1TX ARINC-429 transceiver protocol controllers (FPGA/DSP control/access Block 0)
SDI Filter Label
Acceptance
Filter
RX FIFO
with
Timestamp
ARINC-429 (RX/TX Block 1)
ARINC-429 (RX/TX Block 2)
ARINC-429 (RX/TX Block 3)
ARINC-429 (RX/TX Block 4)
ARINC-429 (RX/TX Block 5)
RX6 channel FPGA/DSP block
data
data
data
control
control
control
status
status
status
ARINC 429
Receiver RX0
ARINC 429
Transmitter TX0
ARINC 429
Receiver RX1
Scheduler
Timebases(2)
FIFO
Timebase
256 x 25
Entries
Scheduler
Commands
256 x 32
Entries
Scheduler
Data 256 x 32
TX FIFO
Low Priority
Bypass Data High Priority
Bypass Data
ARINC Protocol Controller
Standard DNA CLI
– in 2RX configuration, RX6 is same as RX0
– in 1RX/1TX configuration, RX6 is used for loopback control
of TX0 channel
Trigger
Input 0
Output 0
Input 6
loopback
NOTE: Block 0 has 3 ports: TX0, RX0, RX6
Block 1 has 3 ports: TX1, RX1, RX7
Block 2 has 3 ports: TX2, RX2, RX8
Block 3 has 3 ports: TX3, RX3, RX9
Block 4 has 3 ports: TX4, RX4, RX10
Block 5 has 3 ports: TX5, RX5, RX11