Xaoc Devices Drezno II User manual
DREZNO
binary
conversion
komputor ii
Model of 1989
operator’s manual rev. 1989/2.0
2
SALUT
Thank you for purchasing this Xaoc Devices
product. Drezno II is a component of
the Leibniz Binary Subsystem, a family of 8-bit
signal processing devices offering compre-
hensive manipulation of signals and voltages
in the digital domain. Drezno II is the input/
output front-end of the system consisting of an
analog-to-digital converter (ADC) and a digi-
tal-to-analog converter (DAC). In other words,
it converts from continuous analog signals to a
stream of digital numbers from 0 to 255 (the
binary data) and from a stream of digital num-
bers to an analog signal. These numbers are
transmitted using eight parallel binary (two-
state, on/off) signals that may be gates, clocks,
rhythms, etc. Even on its own, Drezno II can be
used for waveshaping of analog signals and
voltages based on their binary representation.
The two halves of the module may be used en-
tirely independently or linked through the data
ribbon cable, possibly with other Leibniz mod-
ules installed between the ADC and the DAC.
Drezno II is an upgraded version of the orig-
inal Drezno released in 2017. It uses new
converters of much higher resolution, which
-
curacy down to the lowest bit. It can be used
for quantizing pitch voltages. Potentiometer
ranges are factory calibrated for the chromat-
ic scale within 10Vpp (128 semitone steps)
and 20Vpp (256 semitone steps).
To better understand the device and avoid
common pitfalls, we strongly advise the user
to read through the entire manual before us-
ing the module.
INSTALLATION
Drezno II requires 12hp worth of free space in
the Eurorack cabinet. Always turn the power
off before plugging the module into the bus
board using the supplied 16-wire ribbon ca-
ble, paying close attention to power cable pin-
out and orientation. The red stripe indicates
the negative rail and should match the arrow
head or -12v mark on the bus board and the
unit. Drezno II is internally secured against
-
ping the 16-pin header may cause serious
damage to other components of your system
because it will short-circuit the +12V and +5V
power lines.
Besides power, you need to pay attention to
1). For standalone operation (using Drezno
II without any additional Leibniz modules),
bridge the out and in headers with the sup-
plied 10-wire ribbon data cable. For expand-
ing your Leibniz setup, use the additional ca-
bles included with your other modules in the
subsystem. The general rule is to connect the
out header of Drezno II to the in header of
some other module that will receive the ADC
data (e.g., Rostock, Poczdam, Jena) and to
connect the out header of some other mod-
ule that provides data (e.g., Ostankino, Erfurt,
Jena, etc.) to the in header of Drezno II. avoid
plugging out to out. Observe the arrow-
head or dot indicating the red stripe orien-
module
explained
3
binary code
Binary numbers are like common decimal numbers, except they don't use 10 different digits (from
0 to 9) but just two (0 and 1), called bits. For example, 203 in the decimal system means “two times
a hundred plus a three,” while 101 in the binary system means “one times a four plus a one.” Why
four? Because in a 3-digit binary (base-2) number, the digits represent 22=4, 21=2, and 20=1, just
like in the 3-digit decimal (base-10) number they represent 102=100, 101=10, and 100=1.
example, in an 8-bit system, the highest bit represents 27=128, and the lowest bit represents 20=1.
Since there are eight bits, and each can have only two values, there are 2*2*2*2*2*2*2*2 = 28=256
combinations possible, from 0 (code 00000000) to 255 (code 11111111).
digit. Thus, manipulating individual bits may have a huge impact on the value (when bit 7 is
affected) or be barely noticeable (when bit 0 is affected), and vice versa: small changes in signal
amplitude often affect only the lower bits, while the highest bits react mostly to big changes.
MADE IN THE EU
XAOCDEVICES.COM
lipsk drezno
Observe the cable orientation. Do not mistake expander headers for power
cord headers; this would destroy the module and void the warranty!
connecting
drezno ii to
other leibniz
components,
e.g. lipsk
4
drezno ii
interface
controls
overview
1 8
410
3
511
13
72
6 9
12
5
tation on the Leibniz header of each module
(not always pointing in the same direction).
Incorrectly plugged cables will result in en-
tirely erroneous operation.
warning: never plug power into the
10-pin leibniz data headers, as this
would heavily damage your Drezno II and
jeopardize other modules connected to it.
The module should be fastened by mounting
the supplied screws before powering up.
MODULE OVERVIEW
can work independently or as a linked pair.
The adc input 1accepts CV and audio sig-
nals. There are eight A/D bit outputs 2,
representing each of the eight bits (7 down
to 0) with a 5V gate signal. In addition, bit
outputs' activity is indicated by the corre-
sponding set of eight yellow adc activity
map LEDs 3.
The illuminated gain 4and offset 5slid-
ers allow you to adapt the range of the input
analog signal to the A/D converter's dynamic
range. The sliders' bi-color LEDs indicate sig-
nal amplitude (gain), clipping (offset), and
polarity (both). The colors are used accord-
ing to industrial standards: red represents
positive, and green represents negative val-
ues. The converter chip expects only positive
voltages, so for bipolar input signals, set the
offset slider in the upper position, which will
add some voltage to shift everything above 0V.
With gain set to max, a 10Vpp input signal
might need to be attenuated (depending on
the desired result).
The A/D converter is clocked internally at a
very high rate (near 2MHz), which helps to
avoid aliasing for audio rate signals, but it also
means the binary output signals may change
at extreme rates. The adc clock input 6
allows you to override the internal clock with
your own clock, which is necessary when you
want to slow down the rate both at the front
panel jacks and in the Leibniz data output. It
accepts gate, trigger, and clock signals, and re-
acts to the rising edge.
The DAC section mirrors the ADC section.
There are eight D/A bit inputs 7, accept-
ing 5V gate signals representing each of the
bits numbered from 7 to 0. The dac output
8produces a CV or audio signal based on the
input code. The dac clock input 9expects
gate/trigger signals and is normalled to the
clock delivered via the ribbon cable connect-
ed to the Leibniz in data socket at the back of
the module. Therefore, even though the DAC
clock by default follows the ADC clock, it can
be replaced by a clock produced by any Leib-
niz module, and it can be overridden by any
signal patched through the panel socket.
The DAC section also features gain 10 and
offset 11 sliders which set the level and shift
of the dac output signal. Similarly, their
bi-color LEDs indicate the amplitude and po-
larity of the output signal (gain) and warn
against possible clipping at the output stage
6
01010111
00111110
00110101
00101011
00111001
01011100
10000000
the principle of a/d conversion
(offset). To achieve a bipolar output signal,
set the offset slider to a lower position, sub-
tracting some voltage from the positive-only
output of the D/A converter and making it
swing around 0V.
The D/A converter is calibrated and offers
precise 1/12V steps when the gain slider is at
maximum. A range of 256 semitones is equiv-
alent to over 20 octaves or over 20Vpp, which
may sometimes be impractical. The dac range
miniature switch 12 selects between this full
range and a narrower 10+ octave range (128
bit and scaling everything down by 1/2.
The illuminated link button 13 connects the
data arriving at the Leibniz in header at the
back as normalization signals for the bit in-
puts. Patching any cable into any DAC binary
input breaks its normalization and overrides
it with the external signal. However, with no
signals patched to the inputs, the converter re-
ceives either the bits from the Leibniz data ca-
ble (when link is engaged) or just 00000000
(when link is off). This arrangement allows
you to replace only a few bits from the in-
coming data or disconnect the DAC from the
Leibniz source entirely and use only the front
panel jacks.
THE PRINCIPLE OF OPERATION
The ADC section of Drezno II converts analog
signals to digital numbers. This process con-
sists of sampling the voltage at each clock
cycle followed by quantization of the sampled
is compared to a set of discrete levels, which
are numbered from 0 to 255. For example, if
10001111
10010110
10101101
10011011
10001010
10010011
Voltage Code
Time Time
the principle
of operation
quantizersample &
hold
Input signal Output data
ADC clock
7
input sawtooth signal and resulting individual bit signals
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
7
6
5
4
3
2
1
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
5
0
-5
the converter is scaled to the -5V to 5V range,
and 0V is being quantized, it falls exactly at
the middle of the scale, resulting in 128. The
number is expressed using eight bits of bina-
ry code. For example, 128 is represented as
10000000. In other words, bit 7 is set to 1, and
the remaining bits are 0.
The physical representation of these bits is
eight parallel gate signals (binary 0=0V, bina-
ry 1=5V). In our example, 5V is at the highest
bit output (bit 7), and 0V is at all the lower
outputs. The same signals are delivered to the
pins of the Leibniz out header at the back
of the module and transmitted alongside the
clock to other modules through the Leibniz
data ribbon cable. It is possible to connect a
chain of multiple Leibniz modules connected
in series or even build a complex system with
data splits and loops.
Feeding a time-varying signal to the ADC in-
put of Drezno II results in the bit outputs
instant, their combined state represents the
corresponding value of the input signal at
that time. For example, observe that when
the analog wave reaches its maximum, all bit
changes the slowest since it only shows wheth-
er the signal is above or below the middle of
the range, while the lowest bits may change
very quickly.
Please keep in mind that there is always some
noise in every analog part of the circuit; hence
the input signal is not perfectly clean. That
means the transitions between binary 0's
and 1's may not be singular, especially with a
high-frequency clock. We recommend using a
slower ADC clock when you need more stable
8
gates or triggers from the bit outputs or
want a slow stream of data.
The DAC section of Drezno II converts digital
numbers to voltages. It features a clock-driv-
en data latch that holds the recent combina-
tion of bits during conversion. The clock for
the D/A converter is supplied from the dac
clock input at the front panel, which in turn
is normalled to the clock received from the
Leibniz in header. This may be the same as
the adc clock
substituted in other Leibniz modules.
The data fed to the converter is sourced di-
rectly from the front panel bit inputs. Each
individual signal is one bit of the 8-bit code,
and their combined state determines the
input number (as described in the "Binary
Code" infobox). For example, if there is an
active 5V gate at input 7and 0V at all the re-
maining inputs, the code is 10000000, which
means 128 in the decimal system. This is the
middle number of the 0...255 range of num-
bers and thus will be converted to the middle
voltage of the current range of output volt-
ages (determined by the dac range switch
and the dac offset and gain sliders).
The bit inputs jacks are optionally nor-
malled to the signals received from the Leib-
niz in header at the back of the module (pro-
vided link is active). Please note the D/A
converter will not produce any analog signal
if there is no Leibniz cable connected and no
signals are patched into the jacks. Also, note
that the output value is not updated until a
new clock impulse occurs after the change
of bits.
input sinusoidal signal and resulting individual bit signals
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
5
0
-5
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
7
6
5
4
3
2
1
0
9
THE CONVERSION CLOCKS AND TIMING
Clocks are essential in digital systems. They
cycle, the old value is passed to the next stage
of a chain of devices, and a new value is tak-
en from the preceding stage. All the logic or
arithmetic processing inside digital circuits
occurs between the edges of the clock signal.
If the frequency is too high, it may cause data
loss, processing errors, and glitches. On the
other hand, a pipeline of processing stages
yields some inevitable latency.
The internal clock of Drezno II is nearly 2MHz,
which helps handle wideband signals without
aliasing while minimizing latency. It is used as
the sampling clock of the A/D converter, and it
is also fed to the Leibniz out header; hence any
subsequent Leibniz module may operate syn-
chronously with this clock. It can be replaced by
any external clock signal (or even some irregular
pattern of triggers or gates) patched to the adc
clock input. Consider that each rising edge of
the clock signal spawns a new process of sam-
pling and then converting the sampled signal
value, which both take some time (about 380ns).
Therefore, the digital code resulting from this
conversion is not instantly available. For this
reason, Drezno II delays the clock's rising edge
by about 450ns (to account for conversion time
+ propagation) before sending it to the Leib-
subsequent device (or Drezno II's DAC section)
receives the code representing the most recent
sample without waiting for the next clock cycle.
-
nal slow clock is patched to the adc clock input.
Please keep in mind that the above solution
only compensates for the conversion latency.
It will not magically help if your clock's rising
edge arrives after the change of input signal.
VOLTAGE RANGES, GAINS, AND OFFSETS
The input sensitivity and output voltage range
of Drezno II are adjustable with gain and
offset sliders. Note that the calibrated scales
are only valid when these potentiometers are
set at the extreme positions. With the ADC
gain set to max, the input range is optimized
for 10Vpp. For example, with offset addition-
ally set to min (for unipolar signals), an input
clocks
and timing
delaying of adc clock to acommodate the time needed for a/d conversion
ADC clock
Leibniz data
Leibniz clock
clock cycle
data latency (380ns)
new sample data valid
added clock delay (450ns)
10
CV=0V generates a binary code 00000000,
CV=5V yields 10000000, and CV=+10V gener-
ates 11111111. Similarly, when offset is set
to max (for bipolar signals), an input CV=-5V
generates a binary code 00000000, CV=0V
yields 10000000, and CV=+5V generates
11111111. If your signal is hotter, it will cause
clipping in the A/D converter unless attenuat-
ed. In general, clipping is not dangerous, but
will not yield correct binary code. Use clipping
indicators in the offset slider as a guide for
optimum range settings.
The DAC section has two range options select-
ed with the slider switch. When set to high,
it can generate voltages exceeding 20Vpp.
With DAC gain set to max, a single change of
(one semitone in the V/oct scale). Since there
are 255 steps, the voltage range is 21.25Vpp.
This is only possible if negative voltages are
allowed. For example, setting the offset slider
to minimum yields 0V at the output when the
input code is 10000000, -10.67V for 00000000,
and +10.58V when the code is 11111111.
There is nothing wrong with clipping when it
is used intentionally. For example, setting the
offset slider to max yields 0V for the input
code of 00000000 and 10.58V for input code
10000000. Higher binary numbers theoretical-
ly yield voltages that cannot be handled in Eu-
rorack; hence they are clipped. The LED in the
offset slider shaft is lit whenever the range
of -10V to +10V is exceeded. When the switch
is set to low, the DAC section halves its output
In other words, a 1/12V step corresponds to
the input binary number changing by 2. There
are 127 such steps, and the voltage range is
thus 10.58Vpp which may be bipolar or unipo-
lar. For example, setting the offset slider to
minimum produces 0V at the output with the
input code 1000000x, 0000000x yields -5.33V,
and 1111111x yields 5.25V. Setting the offset
slider to max produces unipolar voltages: 0V
for code 0000000x, +5.33V for 1000000x, and
+10.58V for 1111111x. The obvious applica-
tion of these calibrated ranges is to produce
pitch voltages. However, this is not the only
use of the DAC section.
When generating audio signals with Drezno
II, you may need a lower amplitude but full
resolution (no ignored bits). In such a case, set
dac range to high, and DAC gain to a mod-
erate value. It may then be necessary to adjust
the offset slider for bipolar output.
PATCH EXAMPLES
• When used standalone (with a loop cable in-
stalled at the back), processing of signals and
voltages through ADC+DAC of Drezno II causes
only a subtle 8-bit quantization effect. Modify-
ing the binary representation creates various
discontinuities in the transfer function, depend-
ing on which bits are affected. Some radical de-
formations of a CV or audio signal are achieved
by cross-patching individual bit outputs and
bit inputs
signal waveforms can be obtained by applying
this to control voltages from LFOs, envelope gen-
erators, and even sequencers.
11
• Generating trigger patterns: feeding an LFO
or any repeating CV into the ADC yields gate
patterns (produced from the bit outputs)
that can be used for drum sequencing. Using
a clock frequency pulse wave as the ADC clock
allows for synchronizing the changes on indi-
vidual outputs.
• Generating melodies: the calibrated DAC
section can produce V/oct voltages for driv-
ing a VCO. Use the same ADC input as above
and set the ADC gain low to constrain the
pitch variations within a desired range.
Substitute the DAC clock with gates from a
sequencer or any other clock source for in-
teresting variations.
• Feeding the bit inputs with various combi-
nations of gate signals (e.g., taken from binary
counters like Xaoc Devices Erfurt, frequency
dividers, or free-running oscillators) allows
for synthesizing many interesting waveshapes
or CV sequences at the DAC output.
• Square wave folder/frequency multiplier:
when a continuous waveform is fed into the
ADC, individual binary outputs deliver pulse
times per input period, depending on the
level of details they represent. The average
frequency of each individual input is twice
as high as the frequency of the input above it,
resulting in extremely fast waveforms at the
note: only input
signals with linear slopes like a sawtooth or
triangle yield uniform density signals at the
• Drezno II can be combined with other logic
modules (like AND, OR, XOR, etc.), operating
on individual bits or whole 8-bit numbers. In
general, all low-level mathematical opera-
tions may be performed on signals and con-
trol voltages in this way.
CONNECTIVITY
Drezno II connects to all modules compatible
with the Leibniz Binary Subsystem: Lipsk,
Gera, Jena, Erfurt, Poczdam, Rostock, Ostanki-
no II, and Odessa.
ACCESSORY
Our Coal Mine black panels are available for
all Xaoc Devices modules. Sold separately. Ask
your favorite retailer. •
0 0.2 0.4 0.6 0.8 1
link on
link off
original signal
example wave deformantion result-
ing from cross-patching bits 7 and
6, and replacing bit 6 with bit 4
EASTERN BLOC TECHNOLOGIES MADE IN THE EUROPEAN UNION
ALL RIGHTS RESERVED. CONTENT COPYRIGHT ©2023 XAOC DEVICES. COPYING, DISTRIBUTION, OR COM-
MERCIAL USE IN ANY WAY IS STRICTLY PROHIBITED AND REQUIRES WRITTEN PERMISSION FROM XAOC
DEVICES. SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT PRIOR NOTICE. EDITING BY BRYAN NOLL.
WARRANTY TERMS
XAOC DEVICES WARRANTS THIS PRODUCT TO BE FREE OF DEFECTS IN MATERIALS OR WORKMANSHIP
AND TO CONFORM WITH THE SPECIFICATIONS AT THE TIME OF SHIPMENT FOR ONE YEAR FROM THE
DATE OF PURCHASE. DURING THAT PERIOD, ANY MALFUNCTIONING OR DAMAGED UNITS WILL BE
REPAIRED, SERVICED, AND CALIBRATED ON A RETURN-TO-FACTORY BASIS. THIS WARRANTY DOES NOT
COVER ANY PROBLEMS RESULTING FROM DAMAGES DURING SHIPPING, INCORRECT INSTALLATION OR
POWER SUPPLY, IMPROPER WORKING ENVIRONMENT, ABUSIVE TREATMENT, OR ANY OTHER OBVIOUS
USER-INFLICTED FAULT.
LEGACY SUPPORT
IF SOMETHING GOES WRONG WITH A XAOC PRODUCT AFTER THE WARRANTY PERIOD IS OVER, THERE IS
NO NEED TO WORRY, AS WE’RE STILL HAPPY TO HELP! THIS APPLIES TO ANY DEVICE, WHEREVER AND
WHENEVER ORIGINALLY ACQUIRED. HOWEVER, IN SPECIFIC CASES, WE RESERVE THE RIGHT TO CHARGE
FOR LABOR, PARTS, AND TRANSIT EXPENSES WHERE APPLICABLE.
RETURN POLICY
THE DEVICE INTENDED FOR REPAIR OR REPLACEMENT UNDER WARRANTY NEEDS TO BE SHIPPED IN
THE ORIGINAL PACKAGING ONLY AND MUST INCLUDE A COMPLETED RMA FORM. XAOC DEVICES CAN
NOT TAKE ANY RESPONSIBILITY FOR DAMAGES CAUSED DURING TRANSPORT. SO BEFORE SENDING
UNSOLICITED PARCEL WILL BE REJECTED AND RETURNED!
GENERAL INQUIRIES
FOR USER FEEDBACK SUGGESTIONS, DISTRIBUTION TERMS, AND JOB POSITIONS, FEEL FREE TO CON-
FORMATION ABOUT THE CURRENT PRODUCT LINE, USER MANUALS, FIRMWARE UPDATES, TUTORIALS,
AND MERCHANDISE.
FEATURES
Universal
analog-to-digital
and digital-to-an-
alog converter
for processing
analog signals in
the 8-bit digital
domain
Suitable for
audio and CV
processing with
no aliasing
Component of the
Leibniz Binary
Subsystem
Accurate convert-
ers with calibrat-
ed voltage ranges
Independent ADC
and DAC
SPECIFICATION
Eurorack syn-
thesizer format
compatible
12hp, 31mm deep
(including the
ribbon cable and
bracket)
Current draw:
+70mA/-40mA
Reverse power
protection
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