rtd FPGA35S6 Series User manual

RTD Embedded Technologies, Inc.
AS9100 and ISO 9001 Certified
FPGA35S6046HR
FPGA35S6101HR
FPGA Module
User’s Manual
BDM-610010048 Rev. D

RTD Embedded Technologies, Inc.
103 Innovation Boulevard
State College, PA 16803 USA
Telephone: [phone]
Fax: [phone]
www.rtd.com
[email protected]
[email protected]

RTD Embedded Technologies, Inc. | www.rtd.com iii FPGA35S6046/FPGA35S6101 User’s Manual
Revision History
Rev A Initial Release
Rev B Updated pictures. Added User ID jumpers. Added configuration flash, PCI vendor and device ID.
Rev C Changed Solder jumper from B1 to B2 in sections 3.3.1 and 4.3.3
Rev D Fixed Table 19. RS-422 and RS-485 modes were incorrect.
Advanced Analog I/O, Advanced Digital I/O, aAIO, aDIO, a2DIO, Autonomous SmartCal, “Catch the Express”, cpuModule, dspFramework, dspModule, expressMate, ExpressPlatform, HiDANplus, “MIL Value for
COTS prices”, multiPort, PlatformBus, and PC/104EZ are trademarks, and “Accessing the Analog World”, dataModule, IDAN, HiDAN, RTD, and the RTD logo are registered trademarks of RTD Embedded
Technologies, Inc (formerly Real Time Devices, Inc.). PS/2 is a trademark of International Business Machines Inc. PCI, PCI Express, and PCIe are trademarks of PCI-SIG. PC/104, PC/104-Plus, PCI-104, PCIe/104,
PCI/104-Express and 104 are trademarks of the PC/104 Embedded Consortium. All other trademarks appearing in this document are the property of their respective owners.
Failure to follow the instructions found in this manual may result in damage to the product described in this manual, or other components of the system. The procedure set forth in this manual shall only be performed
by persons qualified to service electronic equipment. Contents and specifications within this manual are given without warranty, and are subject to change without notice. RTD Embedded Technologies, Inc. shall not
be liable for errors or omissions in this manual, or for any loss, damage, or injury in connection with the use of this manual.
Copyright © 2021 by RTD Embedded Technologies, Inc. All rights reserved.

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Table of Contents
1Introduction 7
1.1 Product Overview........................................................................................................................................................................ 7
1.2 Board Features ........................................................................................................................................................................... 7
1.3 Ordering Information................................................................................................................................................................... 9
1.4 Contact Information .................................................................................................................................................................... 9
1.4.1 Sales Support 9
1.4.2 Technical Support 9
2Specifications 10
2.1 Operating Conditions ................................................................................................................................................................ 10
2.2 Electrical Characteristics .......................................................................................................................................................... 10
3Board Connection 11
3.1 Board Handling Precautions ..................................................................................................................................................... 11
3.2 Physical Characteristics............................................................................................................................................................ 11
3.3 Connectors and Jumpers.......................................................................................................................................................... 12
3.3.1 External I/O Connectors 12
CN3: Xilinx JTAG Programming Header 12
CN8: High Speed Digital I/O Connector 13
CN9: Digital I/O Connector 14
CN10, CN11, CN12, CN13: RS-232/422/485 Transceiver Connectors 14
3.3.2 Bus Connectors 15
CN1(Top) & CN2(Bottom): PCIe Connector 15
3.3.3 Jumpers 15
JP4, JP5, JP6: Pull up/Pull down Jumper 15
JP1: Embedded Programmer Enable 15
JP8: User ID Jumper 15
3.3.1 Solder Jumper 15
B2: Pull up Voltage 15
3.4 Steps for Installing .................................................................................................................................................................... 16
4IDAN Connections 17
4.1 Module Handling Precautions................................................................................................................................................... 17
4.2 Physical Characteristics............................................................................................................................................................ 17
4.3 Connectors and Jumpers.......................................................................................................................................................... 18
P2: RS-232/422/485 Transceiver Connector 18
P3: Digital I/O Connector 18
P4: High Speed Digital I/O Connector 20
4.3.1 Bus Connectors 22
CN1(Top) & CN2(Bottom): PCIe Connector 22
4.3.2 Jumpers 22
JP4, JP5, JP6: Pull up/Pull down Jumper 22
JP1: Embedded Programmer Enable 22
JP8: User ID Jumper 22
4.3.3 Solder Jumper 22
B2: Pull up Voltage 22
4.4 Steps for Installing .................................................................................................................................................................... 23
5Functional Description 24
5.2 Configuration Flash................................................................................................................................................................... 24
5.3 Oscillator................................................................................................................................................................................... 24
5.4 EEPROM .................................................................................................................................................................................. 24

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5.5 DDR2 SRAM............................................................................................................................................................................. 24
5.6 Digital I/O .................................................................................................................................................................................. 25
5.8 Embedded Digilent® USB JTAG Programmer......................................................................................................................... 26
6Register Address Space 27
6.1 Identifying the Board................................................................................................................................................................. 27
6.2 BAR0 –FPGA Example Register Map ..................................................................................................................................... 27
6.2.1 R_ID (Read) 27
6.2.2 R_STATUS (Read) 28
6.2.3 R_EEPROM (Read/Write) 28
6.2.4 R_USER_ID (Read) 28
6.2.5 R_PORT1_IN (Read) 28
6.2.6 R_PORT1_OUT (Write) 28
6.2.7 R_PORT1_DIR (Read/Write) 28
6.2.8 R_PORT2L_IN (Read) 28
6.2.9 R_PORT2L_OUT (Write) 28
6.2.10 R_PORT2L_DIR (Read/Write) 28
6.2.11 R_PORT2H_IN (Read) 28
6.2.12 R_PORT2H_OUT (Write) 28
6.2.13 R_PORT2H_DIR (Read/Write) 29
6.2.14 R_DDR_RD_DATA (Read) 29
6.2.15 R_DDR_WR_DATA (Read/Write) 29
6.2.16 R_DDR_ADDR (Read/Write) 29
6.2.17 R_DDR_STATUS (Read) 30
6.2.18 R_COM1_OUT (Read/Write) 30
6.2.19 R_COM1_IN (Read) 31
6.2.20 R_COM2_OUT (Read/Write) 31
6.2.21 R_COM2_IN (Read) 31
6.2.22 R_COM3_OUT (Read/Write) 32
6.2.23 R_COM3_IN (Read) 32
6.2.24 R_COM4_OUT (Read/Write) 33
6.2.25 R_COM4_IN (Read) 33
7Troubleshooting 34
8Additional Information 35
8.1 PC/104 Specifications............................................................................................................................................................... 35
8.2 PCI and PCI Express Specification .......................................................................................................................................... 35
8.3 Serial Port Transceivers ........................................................................................................................................................... 35
9Limited Warranty 36

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Table of Figures
Figure 1: Board Dimensions ................................................................................................................................................................................... 11
Figure 2: Board Connections .................................................................................................................................................................................. 12
Figure 3: Example 104™Stack............................................................................................................................................................................... 16
Figure 4: IDAN Dimensions .................................................................................................................................................................................... 17
Figure 5: Example IDAN System ............................................................................................................................................................................ 23
Figure 6: FPGA35S6 Block Diagram...................................................................................................................................................................... 24
Figure 7: CN9 Digital I/O Circuitry .......................................................................................................................................................................... 25
Figure 8: Serial Port Transceiver............................................................................................................................................................................ 25
Table of Tables
Table 1: Ordering Options ........................................................................................................................................................................................ 9
Table 2: Operating Conditions ................................................................................................................................................................................ 10
Table 3: Electrical Characteristics .......................................................................................................................................................................... 10
Table 4: CN3 Programming Header ....................................................................................................................................................................... 12
Table 5: CN8 I/O Pin Assignments ......................................................................................................................................................................... 13
Table 6: CN9 I/O Pin Assignments ......................................................................................................................................................................... 14
Table 7: CN10, CN11, CN12, CN13 I/O Pin Assignments ..................................................................................................................................... 14
Table 8: Pull up/Pull down Jumper options ............................................................................................................................................................ 15
Table 9: JP1 –Embedded Programmer Enable..................................................................................................................................................... 15
Table 10: JP8 –User ID Jumper ............................................................................................................................................................................ 15
Table 11: B2 Pull up Voltage .................................................................................................................................................................................. 15
Table 12: P2 Pin Assignments................................................................................................................................................................................ 18
Table 13: P3 Pin Assignments................................................................................................................................................................................ 19
Table 14: P4 Pin Assignments................................................................................................................................................................................ 20
Table 15: Pull up/Pull down Jumper options .......................................................................................................................................................... 22
Table 16: JP1 –Embedded Programmer Enable................................................................................................................................................... 22
Table 17: JP8 –User ID Jumper ............................................................................................................................................................................ 22
Table 18: B2 Pull up Voltage .................................................................................................................................................................................. 22
Table 19: Transceiver Configuration....................................................................................................................................................................... 26
Table 20: Identifying the FPGA35S6 ...................................................................................................................................................................... 27
Table 21: FPGA Example Register Map................................................................................................................................................................. 27

RTD Embedded Technologies, Inc. | www.rtd.com 7FPGA35S6046/FPGA35S6101 User’s Manual
1Introduction
1.1 Product Overview
The FPGA35S6 series of FPGA boards are designed to provide a platform to create any digital I/O that is required for
your application. It interfaces with the PCIe bus and features a Xilinx Spartan 6 FPGA with a 27 MHz oscillator and
1Gb of DDR2 SDRAM. The FPGA35S6046 and FPGA35S6101 provide 32 RS-232/422/485 I/O, 24 5V tolerant I/O
and 40 3.3V tolerant high speed I/O.
1.2 Board Features
•Xilinx Spartan 6 System level features
oXC6SLX45T (FPGA35S6046HR)
▪43,661 Logic Cells
▪2,489 kb of internal RAM
•116 18Kb (2088 Kb Max) Block RAM
•401 kB Distributed RAM
▪XCF16PFSG48C Configuration Flash
oXC6SLX100T (FPGA35S6101HR)
▪101,261 Logic Cells
▪5,800 kb of internal RAM
•268 18Kb (4,824 Kb Max) Block RAM
•976 kB Distributed RAM
▪XCF32PFSG48C Configuration Flash
oRAM hierarchical memory:
▪Each block RAM has two independent ports
▪Programmable Data Width
oIntegrated Endpoint block for PCI Express
oIntegrated Memory Controller
▪1 Gb of DDR2 SDRAM
▪Supports access rates of up to 800Mb/s
oDedicated carry logic for high-speed arithmetic
oAbundant logic resources with increased logic capacity
▪Optional shift register or distributed RAM support
▪Efficient 6-input LUTs
▪LUT with dual flip-flops
oFour dedicated DLLs for advanced clock control
▪Phase shift input clock by 0, 90, 180, 270
▪Multiply input clock by 2 to 32
▪Divide input clock by 1 to 32
•Digital I/O Connectors
o32 RS-232/422/485 I/O
▪Four connectors
▪Exar SP338EER1-L Transceivers
▪Each connector can support a single full RS-232 port or two TX/RX only ports
▪Up to 1 Mbps in RS-232 mode
▪Up to 20 Mbps in RS-422/485 mode
▪ESD Protected
o24 5V tolerant Digital I/O
▪Selectable pull-up/pull-down per byte
▪Pull-up can be 3.3V or 5V
▪ESD Protected
▪Can be used as LVDS Input/Output or LVTTL Input/Output
o40 3.3V tolerant High-Speed I/O
▪ESD Protected
▪Can be used as LVDS Input or LVTTL Input/Output
•Fully supported by Xlinx development system
oISE WebPACK (free download from http://www.xilinx.com)
oISE Design Suite
•Embedded Digilent® USB JTAG Programmer
oAllows programming from the host computer

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oCompatible with Xilinx tools, including iMpact and ChipScope
•PCI Express Bus:
oPCIe/104 Universal Board
▪Interfaces with Type 1 or Type 2 bus
▪No re-population
oProvides 2.5 Gbps in each direction
oIn-band interrupts and messages
oMessage Signaled Interrupt (MSI) support

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1.3 Ordering Information
The FPGA35S6 series of FPGA boards is available in the following options:
Table 1: Ordering Options
Part Number
Description
FPGA35S6046HR
PCIe/104 Spartan-6 XC6SLX45T User Programmable FPGA Module
FPGA35S6101HR
PCIe/104 Spartan-6 XC6SLX100T User Programmable FPGA Module
IDAN-FPGA35S6046HR
PCIe/104 Spartan-6 XC6SLX45T User Programmable FPGA Module in IDAN enclosure
IDAN-FPGA35S6101HR
PCIe/104 Spartan-6 XC6SLX100T User Programmable FPGA Module in IDAN enclosure
A Starter Kit is available for any of the options, which includes the appropriate programming cable. Contact RTD Sales for more information.
The FPGA35S6 is a general use FPGA module, allowing you to design your own FPGA. It has support for custom oscillator and larger Xilinx
Spartan 6 FPGAs. Please contact RTD Embedded Technologies for more information on custom FPGA35S6 products and custom FPGA
designs.
The Intelligent Data Acquisition Node (IDAN™) building block can be used in just about any combination with other IDAN building blocks to
create a simple but rugged 104™ stack. This module can also be incorporated in a custom-built RTD HiDAN™ or HiDANplus High Reliability
Intelligent Data Acquisition Node. Contact RTD sales for more information on our high reliability systems.
1.4 Contact Information
1.4.1 SALES SUPPORT
For sales inquiries, you can contact RTD Embedded Technologies sales via the following methods:
Phone: [phone] Monday through Friday, 8:00am to 5:00pm (EST).
E-Mail: [email protected]
1.4.2 TECHNICAL SUPPORT
If you are having problems with you system, please try the steps in the Troubleshooting section of this manual.
For help with this product, or any other product made by RTD, you can contact RTD Embedded Technologies technical support via the
following methods:
Phone: [phone] Monday through Friday, 8:00am to 5:00pm (EST).
E-Mail: [email protected]

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2Specifications
2.1 Operating Conditions
Table 2: Operating Conditions
Symbol
Parameter
Test Condition
Min
Max
Unit
Vcc5
5V Supply Voltage
4.75
5.25
V
Vcc3
3.3V Supply Voltage
n/a
n/a
V
Vcc12
12V Supply Voltage
n/a
n/a
V
Ta
Operating Temperature
-40
+85
C
Ts
Storage Temperature
-40
+85
C
RH
Relative Humidity
Non-Condensing
0
90%
%
MTBF
Mean Time Before Failure
Telcordia Issue 2
30°C, Ground benign, controlled
TBD
Hours
2.2 Electrical Characteristics
Table 3: Electrical Characteristics
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
P
Power Consumption(1)
Vcc5 = 5.0V
2.5
W
Icc
5V Input Supply Current(1)
Active
500
mA
PCIe/104 Bus
Differential Output Voltage
0.8
1.2
V
DC Differential TX Impedance
80
120
Ω
Differential Input Voltage
0.175
1.2
V
DC Differential RX Impedance
80
120
Ω
Electrical Idle Detect Threshold
65
175
mV
Serial Transceivers
VIH
Input High Voltage
RS-232 mode
2.0
1.5
+15
V
VIL
Input Low Voltage
RS-232 mode
-15
1.2
0.6
V
VOH
Output High Voltage
RS-232 mode
5.0
5.5
7.0
V
VOL
Output Low Voltage
RS-232 mode
-7.0
-5.5
-5.0
V
VTH
Input Differential Threshold
RS-422/485 mode
-200
-125
-50
mV
RIN
Input Resistance
RS-422/485 mode
TERM = 0
-7V ≤ VIN ≤ 12V
96
kΩ
RTERM
Termination Resistance
RS-422/485 mode
TERM = 1
-7V ≤ VIN ≤ 12V
100
120
155
Ω
VOD
Output Differential Voltage
RS-422/485 mode
RL=100Ω (RS-422)
RL=54Ω (RS-485)
2.0
1.5
V
VCM
Driver Common Mode Output Voltage
RS-422/485 mode
3.0
V
Digital I/O
VIH
Input High Voltage
CN9
2.0
5.5
V
VIH
Input High Voltage
CN8
2.0
3.6
V
VIL
Input Low Voltage
CN8,CN9
-0.5
0.8
V
VOH
Output High Voltage
IO= -12mA CN8,CN9
2.6
3.3
V
VOL
Output Low Voltage
IO= 12mA CN8,CN9
0
0.4
V
5V Output
CN8,CN9
200
mA
DDR2 Interface
Access Rate(2)
250
800
Mb/s
Note: (1): Typical power consumption based on RTD’s FPGA example.
(2): Proving by design, not production tested.
For additionally electrical characteristic of the Spartan 6 I/O refer to http://www.xilinx.com

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3Board Connection
3.1 Board Handling Precautions
To prevent damage due to Electrostatic Discharge (ESD), keep your board in its antistatic bag until you are ready to install it into your system.
When removing it from the bag, hold the board at the edges, and do not touch the components or connectors. Handle the board in an antistatic
environment, and use a grounded workbench for testing and handling of your hardware.
3.2 Physical Characteristics
•Weight: Approximately 63.5 g (0.14 lbs.)
•Dimensions: 90.17 mm L x 95.89 mm W (3.550 in L x 3.775 in W)
Figure 1: Board Dimensions

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3.3 Connectors and Jumpers
Figure 2: Board Connections
3.3.1 EXTERNAL I/O CONNECTORS
CN3: Xilinx JTAG Programming Header
Connector CN3 provides a connection to the Xilinx JTAG programming header. The pin assignment for CN3 is shown below. This connector
header mates with the Xilinx OEM programming cable.
Table 4: CN3 Programming Header
3.3V VRef
2
1
GND
TMS
4
3
GND
TCK
6
5
GND
TDO
8
7
GND
TDI
10
9
GND
N/C
12
11
GND
N/C
14
13
GND
JP4, JP5 & JP6:
Pull up/Pull down
Jumper
B2 on bottom side
CN11: RS-232/422/485
CN12: RS-232/422/485
CN13: RS-232/422/485
JP1: Embedded
Programmer
Enable
JP8: User ID
Jumper
CN3:
Programming
Header
CN1 & CN2: PCIe Connector
CN8: High Speed Digital I/O
CN10: RS-232/422/485
CN9: Digital I/O

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CN8: High Speed Digital I/O Connector
Connector CN8 provides 40 digital I/O lines, along with a +5V pin and ground pins. These signals are 3.3V tolerant. The signal names reflect
the signal names I n the Xilinx UCF file with the device pin out.
CN8 is attached to Bank 1, and supports any of the Spartan 6 I/O Standards that use a 3.3V VCCO and no reference voltage. This includes
LVTTL, LVCMOS33 input and output, and LVDS_33 input. LVDS output is not supported in Bank 1.
Table 5: CN8 I/O Pin Assignments
Port2_n[0]
2
1
Port2_p[0]
Port2_n[1]
4
3
Port2_p[1]
Port2_n[2]
6
5
Port2_p[2]
Port2_n[3]
8
7
Port2_p[3]
GND
10
9
GND
Port2_n[4]
12
11
Port2_p[4]
Port2_n[5]
14
13
Port2_p[5]
Port2_n[6]
16
15
Port2_p[6]
Port2_n[7]
18
17
Port2_p[7]
GND
20
19
GND
Port2_n[8]
22
21
Port2_p[8]
Port2_n[9]
24
23
Port2_p[9]
Port2_n[10]
26
25
Port2_p[10]
Port2_n[11]
28
27
Port2_p[11]
GND
30
29
GND
Port2_n[12]
32
31
Port2_p[12]
Port2_n[13]
34
33
Port2_p[13]
Port2_n[14]
36
35
Port2_p[14]
Port2_n[15]
38
37
Port2_p[15]
GND
40
39
GND
Port2_n[16]
42
41
Port2_p[16]
Port2_n[17]
44
43
Port2_p[17]
Port2_n[18]
46
45
Port2_p[18]
Port2_n[19]
48
47
Port2_p[19]
GND
50
49
+5V

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CN9: Digital I/O Connector
Connector CN9 provides 24 digital I/O lines, along with a +5V pin and ground pins. All I/O have pull up/pull down resistors that are controlled by
jumper options, also shown in the table. These signals are 5V tolerant. The signal names reflect the signal names in the Xilinx UCF file with the
device pin out.
CN9 is attached to Bank 0, and supports any of the Spartan 6 I/O Standards that use a 3.3V VCCO and no reference voltage. This includes
LVTTL, LVCMOS33, and LVDS_33 input and output.
Table 6: CN9 I/O Pin Assignments
GND
2
1
port1_p[0]
JP4
GND
4
3
port1_n[0]
GND
6
5
port1_p[1]
GND
8
7
port1_n[1]
GND
10
9
port1_p[2]
GND
12
11
port1_n[2]
GND
14
13
port1_p[3]
GND
16
15
port1_n[3]
GND
18
17
port1_p[4]
JP5
GND
20
19
port1_n[4]
GND
22
21
port1_p[5]
GND
24
23
port1_n[5]
GND
26
25
port1_p[6]
GND
28
27
port1_n[6]
GND
30
29
port1_p[7]
GND
32
31
port1_n[7]
JP6
GND
34
33
port1_p[8]
GND
36
35
port1_n[8]
GND
38
37
port1_p[9]
GND
40
39
port1_n[9]
GND
42
41
port1_p[10]
GND
44
43
port1_n[10]
GND
46
45
port1_p[11]
GND
48
47
port1_n[11]
GND
50
49
+5V
CN10, CN11, CN12, CN13: RS-232/422/485 Transceiver Connectors
These connectors each provide configurable RS-232/422/485 transceivers. The pin configuration and associated FPGA signals are shown in
the Table below. For other modes, and information on how to configure the port, see Section 5.7 on page 25. The signal names reflect the
signal names in the Xilinx UCF file with the device pin out.
CN10 is associated with the “com1” signals, CN11 with the “com2” signals, CN12 with the “com3” signals, and CN13 with the “com4” signals.
These signals are attached to Bank 2 of the FPGA, and should be configured as LVCMOS33.
Table 7: CN10, CN11, CN12, CN13 I/O Pin Assignments
com?_dsr (RX)
2
1
com?_dcd (RX)
com?_rtd (TX)
4
3
com?_rxd (RX)
com?_cts (RX)
6
5
com?_txd (TX)
com?_ri (RX)
8
7
com?_dtr (TX)
GND
10
9
GND

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3.3.2 BUS CONNECTORS
CN1(Top) & CN2(Bottom): PCIe Connector
The PCIe connector is the connection to the system CPU. The position and pin assignments are compliant with the PCI/104-Express
Specification. (See PC/104 Specifications on page 35)
The FPGA35S6 is a “Universal” board, and can connect to either a Type 1 or Type 2 PCIe/104 connector.
3.3.3 JUMPERS
JP4, JP5, JP6: Pull up/Pull down Jumper
JP4, JP5, and JP6 are 3-pin two position jumpers that are used to set pull up or pull downs options on the I/O signal lines of CN9. Refer to
Table 6 to determine which I/O pins are effected by each jumper.
Table 8: Pull up/Pull down Jumper options
Setting
Description
1-2
I/O is pulled up to 3.3V or 5V (Set by B1 and B2)
2-3
I/O is pulled down to GND
No Jumper
I/O has no pull up/pull down
JP1: Embedded Programmer Enable
This jumper is used to enable the embedded programmer to the JTAG chain. See Section 5.8 on page 26 for more details. The board can be
programmed from and external programmer with this jumper in either position.
Table 9: JP1 –Embedded Programmer Enable
Setting
Description
1-2
Enabled embedded programmer
2-3 or
open
Disables embedded programmer
JP8: User ID Jumper
The User ID Jumper is a four position, user defined jumper block. The jumpers can be read by the FPGA. An installed jumper results in a logic
low, and an open jumper results in a logic high.
Table 10: JP8 –User ID Jumper
Position
Description
1-2
User ID bit 0
3-4
User ID bit 1
5-6
User ID bit 2
7-8
User ID bit 3
3.3.1 SOLDER JUMPER
B2: Pull up Voltage
Solder jumper B2 is used to set the pull up voltage for JP4, JP5 and JP6.
Table 11: B2 Pull up Voltage
Setting
Description
1-2
Sets Pull up voltage to 3.3V
2-3
Sets Pull up voltage to 5V

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3.4 Steps for Installing
1. Always work at an ESD protected workstation, and wear a grounded wrist-strap.
2. Turn off power to the PC/104 system or stack.
3. Select and install stand-offs to properly position the module on the stack.
4. Remove the module from its anti-static bag.
5. Check that pins of the bus connector are properly positioned.
6. Check the stacking order; make sure all of the busses used by the peripheral cards are connected to the cpuModule.
7. Hold the module by its edges and orient it so the bus connector pins line up with the matching connector on the stack.
8. Gently and evenly press the module onto the PC/104 stack.
9. If any boards are to be stacked above this module, install them.
10. Attach any necessary cables to the PC/104 stack.
11. Re-connect the power cord and apply power to the stack.
12. Boot the system and verify that all of the hardware is working properly.
Figure 3: Example 104™Stack

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4IDAN Connections
4.1 Module Handling Precautions
To prevent damage due to Electrostatic Discharge (ESD), keep your module in its antistatic bag until you are ready to install it into your system.
When removing it from the bag, hold the module by the aluminum enclosure, and do not touch the components or connectors. Handle the
module in an antistatic environment, and use a grounded workbench for testing and handling of your hardware.
4.2 Physical Characteristics
•Weight: Approximately 0.42 Kg (0.92 lbs.)
•Dimensions: 152mm L x 130mm W x 34mm H (5.983" L x 5.117" W x 1.339" H)
Figure 4: IDAN Dimensions
1.339”
[34mm]
5.983”
[152mm]
5.117”
[130mm]
Front
Back

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4.3 Connectors and Jumpers
P2: RS-232/422/485 Transceiver Connector
Connector Part #: Adam Tech DE37SD Mating Connector: Adam Tech DE37PD
Connector P2 provides configurable RS-232/422/485 transceivers. The pin configuration and associated FPGA signals are shown in the Table
below. The signal names reflect the signal names in the Xilinx UCF file with the device pin out. For other modes, and information on how to
configure the port, see Section 5.7 on page 25.
These signals are attached to Bank 2 of the FPGA, and should be configured as LVCMOS33.
Table 12: P2 Pin Assignments
IDAN P2 Pin
RS-232 Signal
Board Pin
Row 1
Row 2
1
com1_dcd
CN10.1
20
com1_dsr
CN10.2
2
com1_rxd
CN10.3
21
com1_rtd
CN10.4
3
com1_txd
CN10.5
22
com1_cts
CN10.6
4
com1_dtr
CN10.7
23
com1_ri
CN10.8
5
GND
CN10.9
24
com2_dcd
CN11.1
6
com2_dsr
CN11.2
25
com2_rxd
CN11.3
7
com2_rtd
CN11.4
26
com2_txd
CN11.5
8
com2_cts
CN11.6
27
com2_dtr
CN11.7
9
com2_ri
CN11.8
28
GND
CN11.9
10
com3_dcd
CN12.1
29
com3_dsr
CN12.2
11
com3_rxd
CN12.3
30
com3_rtd
CN12.4
12
com3_txd
CN12.5
31
com3_cts
CN12.6
13
com3_dtr
CN12.7
32
com3_ri
CN12.8
14
GND
CN12.9
33
com4_dcd
CN13.1
15
com4_dsr
CN13.2
34
com4_rxd
CN13.3
16
com4_rtd
CN13.4
35
com4_txd
CN13.5
17
com4_cts
CN13.6
36
com4_dtr
CN13.7
18
Com4_ri
CN13.8
37
GND
CN13.9
19
n.c.
n.c.
P3: Digital I/O Connector
Connector Part #: VALCONN HDB-62S Mating Connector: VALCONN HDB-62P
Connector P3 provides 24 digital I/O lines, along with a +5V pin and ground pins. All I/O have pull up/pull down resistors that are controlled by
jumper options, also shown in the table. These signals are 5V tolerant. The signal names reflect the signal names I n the Xilinx UCF file with
the device pin out.

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P3 is attached to Bank 0, and support any of the Spartan 6 I/O Standards that use a 3.3V VCCO and no reference voltage. This includes
LVTTL, LVCMOS33, and LVDS_33 input and output.
Connector P3 also provides a connection to the Xilinx JTAG programming header. This connector header mates with the Xilinx OEM
programming cable through an adapter cable. The adapter cable is provided when purchasing the Starter Kit.
Table 13: P3 Pin Assignments
IDAN P3 Pin
Signal
Pull
Jmpr
C9 Pin
Row 1
Row 2
Row 3
1
port1_p[0]
JP4
1
22
GND
2
43
port1_n[0]
3
2
GND
4
23
port1_p[1]
5
44
GND
6
3
port1_n[1]
7
24
GND
8
45
port1_p[2]
9
4
GND
10
25
port1_n[2]
11
46
GND
12
5
port1_p[3]
13
26
GND
14
47
port1_n[3]
15
6
GND
16
27
port1_p[4]
JP5
17
48
GND
18
7
port1_n[4]
19
28
GND
20
49
port1_p[5]
21
8
GND
22
29
port1_n[5]
23
50
GND
24
9
port1_p[6]
25
30
GND
26
51
port1_n[6]
27
10
GND
28
31
port1_p[7]
29
52
GND
30
11
port1_n[7]
31
32
GND
32
53
port1_p[8]
JP6
33
12
GND
34
33
port1_n[8]
35
54
GND
36
13
port1_p[9]
37
34
GND
38
55
port1_n[9]
39
14
GND
40
35
port1_p[10]
41
56
GND
42
15
port1_n[10]
43
36
GND
44
57
port1_p[11]
45
16
GND
46
37
port1_n[11]
47
58
GND
48
17
+5V
49
38
GND
50
59
Reserved
18
jtag_vref
CN3.2
39
GND
CN3.3

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Table 13: P3 Pin Assignments
IDAN P3 Pin
Signal
Pull
Jmpr
C9 Pin
Row 1
Row 2
Row 3
60
jtag_tms
CN3.4
19
GND_TCK
CN3.5
40
jtag_tck
CN3.6
61
GND
CN3.7
20
jtag_tdo
CN3.8
41
GND
CN3.9
62
jtag_tdi
CN3.10
21
Reserved
42
Reserved
P4: High Speed Digital I/O Connector
Connector Part #: VALCONN HDB-62S Mating Connector: VALCONN HDB-62P
Connector P4 provides 40 digital I/O lines, along with a +5V pin and ground pins. These signals are 3.3V tolerant. The signal names reflect the
signal names I n the Xilinx UCF file with the device pin out.
P4 is attached to Bank 1, and supports any of the Spartan 6 I/O Standards that use a 3.3V VCCO and no reference voltage. This includes
LVTTL, LVCMOS33 input and output, and LVDS_33 input. LVDS output is not supported in Bank 1.
Table 14: P4 Pin Assignments
IDAN P4 Pin
Signal
C8 Pin
Row 1
Row 2
Row 3
1
Port2_p[0]
1
22
Port2_n[0]
2
43
Port2_p[1]
3
2
Port2_n[1]
4
23
Port2_p[2]
5
44
Port2_n[2]
6
3
Port2_p[3]
7
24
Port2_n[3]
8
45
GND
9
4
GND
10
25
Port2_p[4]
11
46
Port2_n[4]
12
5
Port2_p[5]
13
26
Port2_n[5]
14
47
Port2_p[6]
15
6
Port2_n[6]
16
27
Port2_p[7]
17
48
Port2_n[7]
18
7
GND
19
28
GND
20
49
Port2_p[8]
21
8
Port2_n[8]
22
29
Port2_p[9]
23
50
Port2_n[9]
24
9
Port2_p[10]
25
30
Port2_n[10]
26
51
Port2_p[11]
27
10
Port2_n[11]
28
31
GND
29
52
GND
30
11
Port2_p[12]
31
32
Port2_n[12]
32
53
Port2_p[13]
33
12
Port2_n[13]
34