Xilinx XC4000 Series User manual

September 18, 1996 (Version 1.04) 4-5
XC4000-Series Features
Note: XC4000-Series devices described in this data sheet
include the XC4000E, XC4000EX, XC4000L, and
XC4000XL. This information does not apply to the older
Xilinx families: XC4000, XC4000A, XC4000D or XC4000H.
For information on these devices, see the Xilinx W
EB
LINX
at http://www.xilinx.com.
• Third Generation Field-Programmable Gate Arrays
- Select-RAM
TM
memory: on-chip ultra-fast RAM with
- synchronous write option
- dual-port RAM option
- Fully PCI compliant (speed grades -3 and faster)
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- 8 global low-skew clock or signal distribution
networks
• System Performance to 66 MHz
• Flexible Array Architecture
• Systems-Oriented Features
- IEEE 1149.1-compatible boundary scan logic
support
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12-mA sink current per XC4000E output (4 mA per
XC4000L output)
• Configured by Loading Binary File
- Unlimited reprogrammability
• Readback Capability
• Backward Compatible with XC4000 Devices
•XACT
step Development System runs on '386/'486/
Pentium-type PC, Sun-4, and Hewlett-Packard 700
series
- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
- RAM/ROM compiler
Low-VoltageVersions Available
• Low-Voltage Devices Function at 3.0 - 3.6 Volts
• XC4000L: Low-Voltage Versions of XC4000E devices
• XC4000XL: Low-Voltage Versions of XC4000EX
devices
Additional XC4000EX/XL Features
• Highest Capacity — Over 130,000 Usable Gates
• Additional Routing Over XC4000E
- almost twice the routing capacity for high-density
designs
• Buffered Interconnect for Maximum Speed
• New Latch Capability in Configurable Logic Blocks
• Improved VersaRing
TM
I/O Interconnect for Better Fixed
Pinout Flexibility
• Flexible New High-Speed Clock Network
- 8 additional Early Buffers for shorter clock delays
- 4 additional FastCLK
TM
buffers for fastest clock input
- Virtually unlimited number of clock signals
• Optional Multiplexer or 2-input Function Generator on
Device Outputs
• High-Speed Parallel Express
TM
Configuration Mode
• Improved I/O Setup and Clock-to-Output with FastCLK
and Global Early Buffers
• 4 Additional Address Bits in Master Parallel
Configuration Mode
Introduction
XC4000-Series high-performance, high-capacity Field Pro-
grammable Gate Arrays (FPGAs) provide the benefits of
custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
The result of eleven years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased speed,
abundant routing resources, and new, sophisticated soft-
ware to achieve fully automated implementation of com-
plex, high-density, high-performance designs.
The XC4000 Series currently has 19 members, as shown
in Table 1.
XC4000 Series
Field Programmable Gate Arrays
September 18, 1996 (Version 1.04) Product Specification


XC4000 Series Field Programmable Gate Arrays
4-6 September 18, 1996 (Version 1.04)
* Max values ofTypical Gate Range include 20-30% of CLBs used as RAM.
Note: Throughout the functional descriptions in this docu-
ment, references to the XC4000E device family include the
XC4000L, and references to the XC4000EX device family
include the XC4000XL, unless explicitly stated otherwise.
References to the XC4000 Series include the XC4000E,
XC4000EX, XC4000L, and XC4000XL families. All func-
tionality in low-voltage families is the same as in the corre-
sponding 5-Volt family, except where numerical references
are made to timing, power, or current-sinking capability.
Description
XC4000-Series devices are implemented with a regular,
flexible, programmable architecture of Configurable Logic
Blocks (CLBs), interconnected by a powerful hierarchy of
versatile routing resources, and surrounded by a perimeter
of programmable Input/Output Blocks (IOBs). They have
generous routing resources to accommodate the most
complex interconnect patterns.
The devices are customized by loading configuration data
into internal memory cells. The FPGA can either actively
read its configuration data from an external serial or byte-
parallel PROM (master modes), or the configuration data
can be written into the FPGA from an external device
(slave, peripheral and Express modes).
XC4000-Series FPGAs are supported by powerful and
sophisticated software, covering every aspect of design
from schematic or behavioral entry, floorplanning, simula-
tion, automatic block placement and routing of intercon-
nects, to the creation, downloading, and readback of the
configuration bit stream.
Because Xilinx FPGAs can be reprogrammed an unlimited
number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hard-
ware must be adapted to different user applications.
FPGAs are ideal for shortening design and development
cycles, and also offer a cost-effective solution for produc-
tion rates well beyond 5,000 systems per month.For lowest
high-volume unit cost, a design can first be implemented in
the XC4000E or XC4000EX, then migrated to one of Xilinx’
compatible HardWire mask-programmed devices.
Table 2 shows density and performance for a few common
circuit functions that can be implemented in XC4000-Series
devices.
Table 1: XC4000-Series Field Programmable Gate Arrays
Device
Max Logic
Gates
(No RAM)
Max.RAM
Bits
(No Logic)
Typical
Gate Range
(Logic and RAM)* CLB Matrix
Total
Logic
Blocks
Number
of
Flip-Flops
Max.
Decode
Inputs
per side Max. User I/O
XC4003E 3,000 3,200 2,000 - 5,000 10 x 10 100 360 30 80
XC4005E/L 5,000 6,272 3,000 - 9,000 14 x 14 196 616 42 112
XC4006E 6,000 8,192 4,000 - 12,000 16 x 16 256 768 48 128
XC4008E 8,000 10,368 6,000 - 15,000 18 x 18 324 936 54 144
XC4010E/L 10,000 12,800 7,000 - 20,000 20 x 20 400 1,120 60 160
XC4013E/L 13,000 18,432 10,000 - 30,000 24 x 24 576 1,536 72 192
XC4020E 20,000 25,088 13,000 - 40,000 28 x 28 784 2,016 84 224
XC4025E 25,000 32,768 15,000 - 45,000 32 x 32 1,024 2,560 96 256
XC4028EX/XL 28,000 32,768 18,000 - 50,000 32 x 32 1,024 2,560 96 256
XC4036EX/XL 36,000 41,472 22,000 - 65,000 36 x 36 1,296 3,168 108 288
XC4044EX/XL 44,000 51,200 27,000 - 80,000 40 x 40 1,600 3,840 120 320
XC4052XL 52,000 61,952 33,000 - 100,000 44 x 44 1,936 4,576 132 352
XC4062XL 62,000 73,728 40,000 - 130,000 48 x 48 2,304 5,376 144 384
Larger Devices Available in the First Half of 1997

September 18, 1996 (Version 1.04) 4-7
Note: 1.Most functions are faster in XC4000EX due to faster carry logic, direct connects, and other additional interconnect.
Taking Advantage of Reconfiguration
FPGA devices can be reconfigured to change logic function
while resident in the system. This capability gives the sys-
tem designer a new degree of freedom not available with
any other type of logic.
Hardware can be changed as easily as software. Design
updates or modifications are easy, and can be made to
products already in the field. An FPGA can even be recon-
figured dynamically to perform different functions at differ-
ent times.
Reconfigurable logic can be used to implement system
self-diagnostics, create systems capable of being reconfig-
ured for different environments or operations, or implement
multi-purpose hardware for a given application. As an
added benefit, using reconfigurable FPGA devices simpli-
fies hardware design and debugging and shortens product
time-to-market.
Table 2: Density and Performance for Several Common Circuit Functions in XC4000E
1
Design Class Function CLBs Used XC4000E-3 XC4000E-2 Units
Memory
256 x 8 Single Port (read/modify/write) 72 63 80 MHz
32 x 16 bit FIFO
simultaneous read/write
MUXed read/write 48 32 63 63 80 80 MHz MHz
Logic
9 bit Shift Register (with enable) 5 170 200 MHz
16 bit Pre-Scaled Counter 8 142 170 MHz
16 bit Loadable Counter 8 65 76 MHz
16 bit Accumulator 9 65 76 MHz
8 bit, 16 tap FIR Filter sample rate
parallel
serial 400 68 55 8.1 65 10 MHz MHz
8 x 8 Parallel Multiplier
single stage, register to register 73 37 30 ns
16 bit Address Decoder (internal decode) 3 4.7 3.9 ns
9 bit Parity Checker 1 4.3 2.7 ns

XC4000 Series Field Programmable Gate Arrays
4-8 September 18, 1996 (Version 1.04)
XC4000E and XC4000EX Families
Compared to the XC4000
For readers already familiar with the XC4000 family of Xil-
inx Field Programmable Gate Arrays, the major new fea-
tures in the XC4000-Series devices are listed in this
section. The biggest advantages of XC4000E and
XC4000EX devices are significantly increased system
speed, greater capacity, and new architectural features,
particularly Select-RAM memory. The XC4000EX devices
also offer many new routing features, including special
high-speed clock buffers that can be used to capture input
data with minimal delay.
Any XC4000E device is pinout- and bitstream-compatible
with the corresponding XC4000 device. An existing
XC4000 bitstream can be used to program an XC4000E
device. However, since the XC4000E includes many new
features, an XC4000E bitstream cannot be loaded into an
XC4000 device.
Most XC4000EX devices have no corresponding XC4000
devices, because of the larger CLB arrays. The XC4028EX
has the same array size as the XC4025 and XC4025E, but
is not bitstream-compatible. However, the XC4025,
XC4025E, and XC4028EX are all pinout-compatible.
Improvements in XC4000E and XC4000EX
Increased System Speed
Delays in FPGA-based designs are layout dependent.
There is a rule of thumb designers can consider—the sys-
tem clock rate should not exceed one third to one half of the
specified toggle rate. Critical portions of a design, such as
shift registers and simple counters, can run faster—approx-
imately two thirds of the specified toggle rate.
XC4000E and XC4000EX devices can run at synchronous
system clock rates of up to 66 MHz, and internal perfor-
mance can exceed 150 MHz. This increase in performance
over the previous families stems from improvements in both
device processing and system architecture. XC4000-
Series devices use a sub-micron triple-layer metal process.
In addition, many architectural improvements have been
made, as described below.
PCI Compliance
XC4000-Series -3 and faster speed grades are fully PCI
compliant. XC4000E and XC4000EX devices can be used
to implement a one-chip PCI solution.
Carry Logic
The speed of the carry logic chain has increased dramati-
cally. Some parameters, such as the delay on the carry
chain through a single CLB (T
BYP
), have improved by as
much as 50% from XC4000 values. See “Fast Carry Logic”
on page 21 for more information.
Select-RAM Memory: Edge-Triggered, Synchronous
RAM Modes
The RAM in any CLB can be configured for synchronous,
edge-triggered, write operation. The read operation is not
affected by this change to an edge-triggered write.
Dual-Port RAM
A separate option converts the 16x2 RAM in any CLB into a
16x1 dual-port RAM with simultaneous Read/Write.
The function generators in each CLB can be configured as
either level-sensitive (asynchronous) single-port RAM,
edge-triggered (synchronous) single-port RAM, edge-trig-
gered (synchronous) dual-port RAM, or as combinatorial
logic.
Configurable RAM Content
The RAM content can now be loaded at configuration time,
so that the RAM starts up with user-defined data.
H Function Generator
In XC4000-Series devices, the H function generator is
more versatile than in the XC4000.Its inputs can come not
only from the F and G function generators but also from up
to three of the four control input lines. The H function gen-
erator can thus be totally or partially independent of the
other two function generators, increasing the maximum
capacity of the device.
IOB Clock Enable
The two flip-flops in each IOB have a common clock enable
input, which through configuration can be activated individ-
ually for the input or output flip-flop or both. This clock
enable operates exactly like the EC pin on the XC4000
CLB. This new feature makes the IOBs more versatile, and
avoids the need for clock gating.
Output Drivers
The output pull-up structure defaults to a TTL-like totem-
pole. This driver is an n-channel pull-up transistor, pulling
to a voltage one transistor threshold belowVcc, just like the
XC4000 outputs. Alternatively, XC4000-Series devices can
be globally configured with CMOS outputs, with p-channel
pull-up transistors pulling toVcc.Also, the configurable pull-
up resistor in the XC4000 Series is a p-channel transistor
that pulls to Vcc, whereas in the XC4000 it is an n-channel
transistor that pulls to a voltage one transistor threshold
below Vcc.
InputThresholds
The input thresholds can be globally configured for either
TTL (1.2 V threshold) or CMOS (2.5 V threshold), just like
XC2000 and XC3000 inputs.The two global adjustments of
input threshold and output level are independent of each
other.

September 18, 1996 (Version 1.04) 4-9
Global Signal Access to Logic
There is additional access from global clocks to the F and G
function generator inputs.
Configuration Pin Pull-Up Resistors
During configuration, the three mode pins, M0, M1, and
M2, have weak pull-up resistors.For the most popular con-
figuration mode, Slave Serial, the mode pins can thus be
left unconnected.
The three mode inputs can be individually configured with
or without weak pull-up or pull-down resistors after configu-
ration.
The PROGRAM input pin has a permanent weak pull-up.
Soft Start-up
Like the XC3000A, XC4000-Series devices have “Soft
Start-up.” When the configuration process is finished and
the device starts up, the first activation of the outputs is
automatically slew-rate limited. This feature avoids poten-
tial ground bounce when all outputs are turned on simulta-
neously. Immediately after start-up, the slew rate of the
individual outputs is, as in the XC4000 family, determined
by the individual configuration option.
XC4000 and XC4000A Compatibility
Existing XC4000 bitstreams can be used to configure an
XC4000E device. XC4000A bitstreams must be recom-
piled for use with the XC4000E due to improved routing
resources, although the devices are pin-for-pin compatible.
Additional Improvements in XC4000EX
Only
Increased Routing
New interconnect in the XC4000EX includes twenty-two
additional vertical lines in each column of CLBs and twelve
new horizontal lines in each row of CLBs. The twelve
“Quad Lines” in each CLB row and column include optional
repowering buffers for maximum speed. Additional high-
performance routing near the IOBs enhances pin flexibility.
Faster Input and Output
A fast, dedicated early clock sourced by global clock buffers
is available for the IOBs. To ensure synchronization with
the regular global clocks, a Fast Capture latch driven by the
early clock is available. The input data can be initially
loaded into the Fast Capture latch with the early clock, then
transferred to the input flip-flop or latch with the low-skew
global clock. A programmable delay on the input can be
used to avoid hold-time requirements. See “IOB Input Sig-
nals” on page 24 for more information.
Latch Capability in CLBs
Storage elements in the XC4000EX CLB can be configured
as either flip-flops or latches. This capability makes the
FPGA highly synthesis-compatible.
IOB Output MUX From Output Clock
A multiplexer in the IOB allows the output clock to select
either the output data or the IOB clock enable as the output
to the pad. Thus, two different data signals can share a sin-
gle output pad, effectively doubling the number of device
outputs without requiring a larger, more expensive pack-
age. This multiplexer can also be configured as an AND-
gate to implement a very fast pin-to-pin path. See “IOB
Output Signals” on page 27 for more information.
Express Configuration Mode
A new slave configuration mode accepts parallel data input.
Data is processed in parallel, rather than serialized inter-
nally. Therefore, the data rate is eight times that of the six
conventional configuration modes.
Additional Address Bits
Larger devices require more bits of configuration data. A
daisy chain of several large XC4000EX devices may
require a PROM that cannot be addressed by the eighteen
address bits supported in the XC4000E. The XC4000EX
family therefore extends the addressing in Master Parallel
configuration mode to 22 bits.

XC4000 Series Field Programmable Gate Arrays
4-10 September 18, 1996 (Version 1.04)
Table 3: CLB Count of Selected XC4000-Series Soft Macros
7400 Equivalents CLBs Barrel Shifters CLBs Multiplexers CLBs
‘138
‘139
‘147
‘148
‘150
‘151
‘152
‘153
‘154
‘157
‘158
‘160
‘161
‘162
‘163
‘164
‘165s
‘166
‘168
‘174
‘194
‘195
‘280
‘283
‘298
‘352
‘390
‘518
‘521
5
2
5
6
5
3
3
2
16
2
2
5
6
8
8
4
9
5
7
3
5
3
3
8
2
2
3
3
3
brlshft4
brlshft8 4 13 m2-1e m4-1e
m8-1e
m16-1e
1
1
3
5
4-Bit Counters
cd4cd
cd4cle
cd4rle
cb4ce
cb4cle
cb4re
3
5
6
3
6
5
Registers
rd4r
rd8r
rd16r
2
4
8
8- and 16-Bit Counters Shift Registers
cb8ce
cb8re
cc16ce
cc16cle
cc16cled
6
10
9
9
21
sr8ce
sr16re 4 8
Decoders
d2-4e
d3-8e
d4-16e
2
4
16
Identity Comparators
comp4
comp8
comp16
1
2
5Explanation of counter nomenclature
cb = binary counter
cd = BCD counter
cc = cascadable binary counter
d = bidirectional
l = loadable
e = clock enable
r = synchronous reset
c = asynchronous clear
Magnitude Comparators
compm4
compm8
compm16
4
9
20
Explanation of RAM nomenclature
s = single-port edge-triggered
d = dual-port edge-triggered
no extension = level-sensitive
RAMs
ram16x4
ram16x4s
ram16x4d
2
2
4

September 18, 1996 (Version 1.04) 4-11
Detailed Functional Description
XC4000-Series devices achieve high speed through
advanced semiconductor technology and improved archi-
tecture. The XC4000E and XC4000EX support system
clock rates of up to 66 MHz and internal performance in
excess of 150 MHz. Compared to older Xilinx FPGA fami-
lies, XC4000-Series devices are more powerful. They offer
on-chip edge-triggered and dual-port RAM, clock enables
on I/O flip-flops, and wide-input decoders. They are more
versatile in many applications, especially those involving
RAM. Design cycles are faster due to a combination of
increased routing resources and more sophisticated soft-
ware.
Basic Building Blocks
Xilinx user-programmable gate arrays include two major
configurable elements: configurable logic blocks (CLBs)
and input/output blocks (IOBs).
• CLBs provide the functional elements for constructing
the user’s logic.
• IOBs provide the interface between the package pins
and internal signal lines.
Three other types of circuits are also available:
• 3-State buffers (TBUFs) driving horizontal longlines are
associated with each CLB.
• Wide edge decoders are available around the periphery
of each device.
• An on-chip oscillator is provided.
Programmable interconnect resources provide routing
paths to connect the inputs and outputs of these config-
urable elements to the appropriate networks.
The functionality of each circuit block is customized during
configuration by programming internal static memory cells.
The values stored in these memory cells determine the
logic functions and interconnections implemented in the
FPGA.
Each of these available circuits is described in this section.
Configurable Logic Blocks (CLBs)
Configurable Logic Blocks implement most of the logic in
an FPGA. The principal CLB elements are shown in
Figure 1. The number of CLBs needed to implement
selected soft macros is shown in Table 3.
Two 4-input function generators (F and G) offer unrestricted
versatility. Most combinatorial logic functions need four or
fewer inputs. However, a third function generator (H) is pro-
vided. The H function generator has three inputs. Either
zero, one, or both of these inputs can be the outputs of F
and G; the other input(s) are from outside the CLB. The
CLB can, therefore, implement certain functions of up to
nine variables, like parity check or expandable-identity
comparison of two sets of four inputs.
Each CLB contains two storage elements that can be used
to store the function generator outputs. However, the stor-
age elements and function generators can also be used
independently. These storage elements can be configured
as flip-flops in both XC4000E and XC4000EX devices; in
the XC4000EX they can optionally be configured as
latches. DIN can be used as a direct input to either of the
two storage elements. H1 can drive the other through the H
function generator. Function generator outputs can also
drive two outputs independent of the storage element out-
puts. This versatility increases logic capacity and simplifies
routing.
Thirteen CLB inputs and four CLB outputs provide access
to the function generators and storage elements. These
inputs and outputs connect to the programmable intercon-
nect resources outside the block.
Function Generators
Four independent inputs are provided to each of two func-
tion generators (F1 - F4 and G1 - G4). These function gen-
erators, with outputs labeled F’and G’, are each capable of
implementing any arbitrarily defined Boolean function of
four inputs. The function generators are implemented as
memory look-up tables. The propagation delay is therefore
independent of the function implemented.
A third function generator, labeled H’, can implement any
Boolean function of its three inputs. Two of these inputs
can optionally be the F’ and G’ functional generator out-
puts. Alternatively, one or both of these inputs can come
from outside the CLB (H2, H0). The third input must come
from outside the block (H1).
Signals from the function generators can exit the CLB on
two outputs. F’ or H’ can be connected to the X output. G’
or H’can be connected to theY output.
A CLB can be used to implement any of the following func-
tions:
• any function of up to four variables, plus any second
function of up to four unrelated variables, plus any third
function of up to three unrelated variables
1
• any single function of five variables
• any function of four variables together with some
functions of six variables
• some functions of up to nine variables.
1. When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only two
unregistered function generator outputs are available from the CLB.

XC4000 Series Field Programmable Gate Arrays
4-12 September 18, 1996 (Version 1.04)
Implementing wide functions in a single block reduces both
the number of blocks required and the delay in the signal
path, achieving both increased capacity and speed.
The versatility of the CLB function generators significantly
improves system speed. In addition, the design-software
tools can deal with each function generator independently.
This flexibility improves cell usage.
Flip-Flops
The CLB can pass the combinatorial output(s) to the inter-
connect network, but can also store the combinatorial
results or other incoming data in one or two flip-flops, and
connect their outputs to the interconnect network as well.
The two edge-triggered D-type flip-flops have common
clock (K) and clock enable (EC) inputs. Either or both clock
inputs can also be permanently enabled. Storage element
functionality is described in Table 4.
Latches (XC4000EX only)
The CLB storage elements can also be configured as
latches. The two latches have common clock (K) and clock
enable (EC) inputs. Storage element functionality is
described in Table 4.
Clock Input
Each flip-flop can be triggered on either the rising or falling
clock edge. The clock pin is shared by both storage ele-
ments. However, the clock is individually invertible for each
storage element. Any inverter placed on the clock input is
automatically absorbed into the CLB.
LOGIC
FUNCTION
OF
G1-G4
G4
G3
G2
G1
G'
LOGIC
FUNCTION
OF
F1-F4
F4
F3
F2
F1
F'
LOGIC
FUNCTION
OF
F', G',
AND
H1
H'
DIN
F'
G'
H'
DIN
F'
G'
H'
G'
H'
H'
F'
S/R
CONTROL
D
EC RD
Bypass
Bypass
SD YQ
XQ
Q
S/R
CONTROL
D
EC RD
SD Q
1
1
K
(CLOCK)
Multiplexer Controlled
by Configuration Program
Y
X
DIN/H2
H1SR/H0EC
X6692
C1• • • C44

Figure 1: Simplified Block Diagram of XC4000-Series CLB (RAM and Carry Logic functions not shown)
Table 4: CLB Storage Element Functionality
(active rising edge is shown)
Mode K EC SR D Q
Power-Up or
GSR XXXXSR
Flip-Flop XX1XSR __/ 1* 0* D D
0X0*XQ
Latch 11*0*XQ
01*0*DD
Both X 0 0* X Q
Legend:
X
__/
SR
0*
1*
Don’t care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)

September 18, 1996 (Version 1.04) 4-13
Clock Enable
The clock enable signal (EC) is active High. The EC pin is
shared by both storage elements. If left unconnected for
either, the clock enable for that storage element defaults to
the active state. EC is not invertible within the CLB.
Set/Reset
An asynchronous storage element input (SR) can be con-
figured as either set or reset. This configuration option
determines the state in which each flip-flop becomes oper-
ational after configuration. It also determines the effect of a
Global Set/Reset pulse during normal operation, and the
effect of a pulse on the SR pin of the CLB. All three set/
reset functions for any single flip-flop are controlled by the
same configuration data bit.
The set/reset state can be independently specified for each
flip-flop. This input can also be independently disabled for
either flip-flop.
The set/reset state is specified by using the INIT attribute,
or by placing the appropriate set or reset flip-flop library
symbol.
SR is active High. It is not invertible within the CLB.
Global Set/Reset
A separate Global Set/Reset line (not shown in Figure 1)
sets or clears each storage element during power-up,
reconfiguration, or when a dedicated Reset net is driven
active. This global net (GSR) does not compete with other
routing resources;it uses a dedicated distribution network.
Each flip-flop is configured as either globally set or reset in
the same way that the local set/reset (SR) is specified.
Therefore, if a flip-flop is set by SR, it is also set by GSR.
Similarly, a reset flip-flop is reset by both SR and GSR.
GSR can be driven from any user-programmable pin as a
global reset input. To use this global net, place an input
pad and input buffer in the schematic or HDL code, driving
the GSR pin of the STARTUP symbol. (See Figure 2.) A
specific pin location can be assigned to this input using a
LOC attribute or property, just as with any other user-pro-
grammable pad. An inverter can optionally be inserted
after the input buffer to invert the sense of the Global Set/
Reset signal.
Alternatively, GSR can be driven from any internal node.
Data Inputs and Outputs
The source of a storage element data input is programma-
ble. It is driven by any of the functions F’, G’, and H’, or by
the Direct In (DIN) block input.The flip-flops or latches drive
the XQ andYQ CLB outputs.
Two fast feed-through paths are available, as shown in
Figure 1. A two-to-one multiplexer on each of the XQ and
YQ outputs selects between a storage element output and
any of the control inputs. This bypass is sometimes used
by the automated router to repower internal signals.
Control Signals
Multiplexers in the CLB map the four control inputs (C1 - C4
in Figure 1) into the four internal control signals (H1, DIN/
H2, SR/H0, and EC). Any of these inputs can drive any of
the four internal control signals.
When the logic function is enabled, the four inputs are:
• EC — Enable Clock
• SR/H0 — Asynchronous Set/Reset or H function
generator Input 0
• DIN/H2 — Direct In or H function generator Input 2
• H1 — H function generator Input 1.
When the memory function is enabled, the four inputs are:
• EC — Enable Clock
• WE — Write Enable
• D0 — Data Input to F and/or G function generator
• D1 — Data input to G function generator (16x1 and
16x2 modes) or 5th Address bit (32x1 mode).
Using FPGA Flip-Flops and Latches
The abundance of flip-flops in the XC4000 Series invites
pipelined designs.This is a powerful way of increasing per-
formance by breaking the function into smaller subfunc-
tions and executing them in parallel, passing on the results
through pipeline flip-flops.This method should be seriously
considered wherever throughput is more important than
latency.
To include a CLB flip-flop, place the appropriate library
symbol. For example, FDCE is a D-type flip-flop with clock
enable and asynchronous clear. The corresponding latch
symbol (for the XC4000EX only) is called LDCE.
In XC4000-Series devices, the flip flops can be used as
registers or shift registers without blocking the function gen-
erators from performing a different, perhaps unrelated task.
This ability increases the functional capacity of the devices.
The CLB setup time is specified between the function gen-
erator inputs and the clock input K. Therefore, the specified
CLB flip-flop setup time includes the delay through the
function generator.
PAD
IBUF
GSR
GTS
CLK DONEIN
Q1Q4
Q2
Q3
STARTUP
X5260
Figure 2: Schematic Symbols for Global Set/Reset

XC4000 Series Field Programmable Gate Arrays
4-14 September 18, 1996 (Version 1.04)
Using Function Generators as RAM
Optional modes for each CLB make the memory look-up
tables in the F’ and G’ function generators usable as an
array of Read/Write memory cells. Available modes are
level-sensitive (similar to the XC4000/A/H families), edge-
triggered, and dual-port edge-triggered. Depending on the
selected mode, a single CLB can be configured as either a
16x2, 32x1, or 16x1 bit array.
Supported CLB memory configurations and timing modes
for single- and dual-port modes are shown in Table 5.
XC4000-Series devices are the first programmable logic
devices with edge-triggered (synchronous) and dual-port
RAM accessible to the user. Edge-triggered RAM simpli-
fies system timing. Dual-port RAM doubles the effective
throughput of FIFO applications. These features can be
individually programmed in any XC4000-Series CLB.
Advantages of On-Chip and Edge-Triggered RAM
The on-chip RAM is extremely fast. The read access time
is the same as the logic delay. The write access time is
slightly slower. Both access times are much faster than
any off-chip solution, because they avoid I/O delays.
Edge-triggered RAM, also called synchronous RAM, is a
feature never before available in a Field Programmable
Gate Array. The simplicity of designing with edge-triggered
RAM, and the markedly higher achievable performance,
add up to a significant improvement over existing devices
with on-chip RAM.
Three application notes are available from Xilinx that dis-
cuss edge-triggered RAM: “
XC4000E Edge-Triggered and
Dual-Port RAM Capability, ” “ Implementing FIFOs in
XC4000E RAM, ” and “ Synchronous and Asynchronous
FIFO Designs .” All three application notes apply to both
XC4000E and XC4000EX RAM.
RAM Configuration Options
The function generators in any CLB can be configured as
RAM arrays in the following sizes:
• Two 16x1 RAMs: two data inputs and two data outputs
with identical or, if preferred, different addressing for
each RAM
• One 32x1 RAM: one data input and one data output.
One F or G function generator can be configured as a 16x1
RAM while the other function generators are used to imple-
ment any function of up to 5 inputs.
Additionally, the XC4000-Series RAM may have either of
two timing modes:
• Edge-Triggered (Synchronous): data written by the
designated edge of the CLB clock. WE acts as a true
clock enable.
• Level-Sensitive (Asynchronous): an external WE signal
acts as the write strobe.
The selected timing mode applies to both function genera-
tors within a CLB when both are configured as RAM.
The number of read ports is also programmable:
• Single Port: each function generator has a common
read and write port
• Dual Port: both function generators are configured
together as a single 16x1 dual-port RAM with one write
port and two read ports. Simultaneous read and write
operations to the same or different addresses are
supported.
RAM configuration options are selected by placing the
appropriate library symbol.
Choosing a RAM Configuration Mode
The appropriate choice of RAM mode for a given design
should be based on timing and resource requirements,
desired functionality, and the simplicity of the design pro-
cess. Recommended usage is shown in Table 6.
The difference between level-sensitive, edge-triggered,
and dual-port RAM is only in the write operation. Read
operation and timing is identical for all modes of operation.
Table 5: Supported RAM Modes
16
x
1
16
x
2
32
x
1
Edge-
Triggered
Timing
Level-
Sensitive
Timing
Single-Port √√√ √ √
Dual-Port √√
Table 6: RAM Mode Selection
Level-
Sensitive Edge- Triggered
Dual-Port
Edge-
Triggered
Use for New
Designs? No Yes Yes
Size (16x1,
Registered) 1/2 CLB 1/2 CLB 1 CLB
Simultaneous
Read/Write No No Yes
Relative
Performance X2X
2X (4X
effective)

September 18, 1996 (Version 1.04) 4-15
G'
4

G1• • • G4
F1• • • F4
C1• • • C4
WRITE
DECODER

1 of 16
DIN
16-LATCH
ARRAY
X6752
4

4

MUX
F'
WRITE
DECODER

1 of 16
DIN
16-LATCH
ARRAY
READ
ADDRESS
READ
ADDRESS
WRITE PULSE
LATCH
ENABLE
LATCH
ENABLE
K
(CLOCK)
WE D1D0EC
WRITE PULSE
MUX
4
4

Figure 3: 16x2 (or 16x1) Edge-Triggered Single-Port RAM
G'
4

G1• • • G4
F1• • • F4
C1• • • C4
WRITE
DECODER

1 of 16
DIN
16-LATCH
ARRAY
X6754
4

4

MUX
F'
WRITE
DECODER

1 of 16
DIN
16-LATCH
ARRAY
READ
ADDRESS
READ
ADDRESS
WRITE PULSE
LATCH
ENABLE
LATCH
ENABLE
K
(CLOCK)
WE D1/A4D0
EC
EC
WRITE PULSE
MUX
4
4

H'
Figure 4: 32x1 Edge-Triggered Single-Port RAM (F and G addresses are identical)

XC4000 Series Field Programmable Gate Arrays
4-16 September 18, 1996 (Version 1.04)
RAM Inputs and Outputs
The F1-F4 and G1-G4 inputs to the function generators act
as address lines, selecting a particular memory cell in each
look-up table.
The functionality of the CLB control signals changes when
the function generators are configured as RAM. The DIN/
H2, H1, and SR/H0 lines become the two data inputs (D0,
D1) and the Write Enable (WE) input for the 16x2 memory.
When the 32x1 configuration is selected, D1 acts as the
fifth address bit and D0 is the data input.
The contents of the memory cell(s) being addressed are
available at the F’and G’ function-generator outputs. They
can exit the CLB through its X andY outputs, or can be cap-
tured in the CLB flip-flop(s).
Configuring the CLB function generators as Read/Write
memory does not affect the functionality of the other por-
tions of the CLB, with the exception of the redefinition of the
control signals. In 16x2 and 16x1 modes, the H’ function
generator can be used to implement Boolean functions of
F’, G’, and D1, and the D flip-flops can latch the F’, G’, H’, or
D0 signals.
Single-Port Edge-Triggered Mode
Edge-triggered (synchronous) RAM simplifies timing
requirements. XC4000-Series edge-triggered RAM timing
operates like writing to a data register. Data and address
are presented. The register is enabled for writing by a logic
High on the write enable input, WE. Then a rising or falling
clock edge loads the data into the register, as shown in
Figure 5.
Complex timing relationships between address, data, and
write enable signals are not required, and the external write
enable pulse becomes a simple clock enable. The active
edge ofWCLK latches the address, input data, andWE sig-
nals. An internal write pulse is generated that performs the
write. See Figure 3 and Figure 4 for block diagrams of a
CLB configured as 16x2 and 32x1 edge-triggered, single-
port RAM.
The relationships between CLB pins and RAM inputs and
outputs for single-port, edge-triggered mode are shown in
Table 7.
The Write Clock input (WCLK) can be configured as active
on either the rising edge (default) or the falling edge. It
uses the same CLB pin (K) used to clock the CLB flip-flops,
but it can be independently inverted. Consequently, the
RAM output can optionally be registered within the same
CLB either by the same clock edge as the RAM, or by the
opposite edge of this clock. The sense of WCLK applies to
both function generators in the CLB when both are config-
ured as RAM.
The WE pin is active-High and is not invertible within the
CLB.
Note: The pulse following the active edge of WCLK (T
WPS
in Figure 5) must be less than one millisecond wide. For
most applications, this requirement is not overly restrictive;
however, it must not be forgotten. Stopping WCLK at this
point in the write cycle could result in excessive current and
even damage to the larger devices if many CLBs are con-
figured as edge-triggered RAM.
Table 7: Single-Port Edge-Triggered RAM Signals
RAM Signal CLB Pin Function
D D0 or D1
(16x2, 16x1)
D0 (32x1)
Data In
A[3:0] F1-F4 or
G1-G4 Address
A[4] D1 (32x1) Address
WE WE Write Enable
WCLK K Clock
SPO
(Data Out) F’ or G’ Single Port Out (Data Out)
X6461
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT OLD NEW
TDSS TDHS
TASS TAHS
TWSS
TWPS
TWHS
TWOS
TILO
TILO
Figure 5: Edge-Triggered RAM WriteTiming

September 18, 1996 (Version 1.04) 4-17
Dual-Port Edge-Triggered Mode
In dual-port mode, both the F and G function generators
are used to create a single 16x1 RAM array with one write
port and two read ports. The resulting RAM array can be
read and written simultaneously at two independent
addresses. Simultaneous read and write operations at the
same address are also supported.
Dual-port mode always has edge-triggered write timing, as
shown in Figure 5.
Figure 6 shows a simple model of an XC4000-Series CLB
configured as dual-port RAM. One address port, labeled
A[3:0], supplies both the read and write address for the F
function generator. This function generator behaves the
same as a 16x1 single-port edge-triggered RAM array. The
RAM output, Single Port Out (SPO), appears at the F func-
tion generator output. SPO, therefore, reflects the data at
address A[3:0].
The other address port, labeled DPRA[3:0] for Dual Port
Read Address, supplies the read address for the G function
generator. The write address for the G function generator,
however, comes from the address A[3:0]. The output from
this 16x1 RAM array, Dual Port Out (DPO), appears at the
G function generator output. DPO, therefore, reflects the
data at address DPRA[3:0].
Therefore, by using A[3:0] for the write address and
DPRA[3:0] for the read address, and reading only the DPO
output, a FIFO that can read and write simultaneously is
easily generated. Simultaneous access doubles the effec-
tive throughput of the FIFO.
The relationships between CLB pins and RAM inputs and
outputs for dual-port, edge-triggered mode are shown in
Table 8. See Figure 7 for a block diagram of a CLB config-
ured in this mode.
Note: The pulse following the active edge of WCLK (T
WPS
in Figure 5) must be less than one millisecond wide. For
most applications, this requirement is not overly restrictive;
however, it must not be forgotten. Stopping WCLK at this
point in the write cycle could result in excessive current and
even damage to the larger devices if many CLBs are con-
figured as edge-triggered RAM.
Table 8: Dual-Port Edge-Triggered RAM Signals
WE WE
DDQ
DQ
D
DPRA[3:0]
A[3:0]
AR[3:0]
AW[3:0]
WE
D
AR[3:0]
AW[3:0]
RAM16X1D Primitive
F Function Generator
G Function Generator
DPO (Dual Port Out)
Registered DPO
SPO (Single Port Out)
Registered SPO
WCLK
X6755
Figure 6: XC4000-Series Dual-Port RAM, Simple
Model
RAM Signal CLB Pin Function
D D0 Data In
A[3:0] F1-F4 Read Address for F,
Write Address for F and G
DPRA[3:0] G1-G4 Read Address for G
WE WE Write Enable
WCLK K Clock
SPO F’ Single Port Out
(addressed by A[3:0])
DPO G’ Dual Port Out
(addressed by
DPRA[3:0])

XC4000 Series Field Programmable Gate Arrays
4-18 September 18, 1996 (Version 1.04)
G'
G1• • • G4
F1• • • F4
WRITE
DECODER

1 of 16
DIN
16-LATCH
ARRAY
X6748
4

4

MUX
F'
WRITE
DECODER

1 of 16
DIN
16-LATCH
ARRAY
READ
ADDRESS
READ
ADDRESS
WRITE PULSE
LATCH
ENABLE
LATCH
ENABLE
K
(CLOCK) WRITE PULSE
MUX
4
4

C1• • • C44

WE D1D0EC
Figure 7: 16x1 Edge-Triggered Dual-Port RAM

September 18, 1996 (Version 1.04) 4-19
Single-Port Level-SensitiveTiming Mode
Note: Edge-triggered mode is recommended for all new
designs. Level-sensitive mode, also called asynchronous
mode, is still supported for XC4000-Series backward-com-
patibility with the XC4000 family.
Level-sensitive RAM timing is simple in concept but can be
complicated in execution. Data and address signals are
presented, then a positive pulse on the write enable pin
(WE) performs a write into the RAM at the designated
address. As indicated by the “level-sensitive” label, this
RAM acts like a latch. During theWE High pulse, changing
the data lines results in new data written to the old address.
Changing the address lines whileWE is High results in spu-
rious data written to the new address—and possibly at
other addresses as well, as the address lines inevitably do
not all change simultaneously.
The user must generate a carefully timed WE signal. The
delay on theWE signal and the address lines must be care-
fully verified to ensure thatWE does not become active until
after the address lines have settled, and thatWE goes inac-
tive before the address lines change again. The data must
be stable before and after the falling edge of WE.
In practical terms,WE is usually generated by a 2X clock. If
a 2X clock is not available, the falling edge of the system
clock can be used. However, there are inherent risks in this
approach, since the WE pulse must be guaranteed inactive
before the next rising edge of the system clock. Several
older application notes are available from Xilinx that dis-
cuss the design of level-sensitive RAMs. These application
notes include XAPP031, “
Using the XC4000 RAM Capabil-
ity ,” and XAPP042, “ High-Speed RAM Design in XC4000 .”
However, the edge-triggered RAM available in the XC4000
Series is superior to level-sensitive RAM for almost every
application.
Figure 8 shows the write timing for level-sensitive, single-
port RAM.
The relationships between CLB pins and RAM inputs and
outputs for single-port level-sensitive mode are shown in
Table 9.
Figure 9 and Figure 10 show block diagrams of a CLB con-
figured as 16x2 and 32x1 level-sensitive, single-port RAM.
Initializing RAM at Configuration
Both RAM and ROM implementations of the XC4000-
Series devices are initialized during configuration. The ini-
tial contents are defined via an INIT attribute or property
attached to the RAM or ROM symbol, as described in the
schematic library guide.
If not defined, all RAM contents are initialized to all zeros,
by default.
RAM initialization occurs only during configuration. The
RAM content is not affected by Global Set/Reset.
Table 9: Single-Port Level-Sensitive RAM Signals
RAM Signal CLB Pin Function
D D0 or D1 Data In
A[3:0] F1-F4 or
G1-G4 Address
WE WE Write Enable
O F’ or G’ Data Out
WC
T
ADDRESS
WRITE ENABLE
DATA IN
AS
TWP T
DS
TDH
T
REQUIRED
AH
T
X6462
Figure 8: Level-Sensitive RAMWriteTiming

XC4000 Series Field Programmable Gate Arrays
4-20 September 18, 1996 (Version 1.04)
Enable

G'
4

G1• • • G4
F1• • • F4
WRITE
DECODER

1 of 16
DIN
16-LATCH
ARRAY
X6746
4
READ ADDRESS

MUX
Enable

F'
WRITE
DECODER

1 of 16
DIN
16-LATCH
ARRAY
4
READ ADDRESS

MUX
4

C1• • • C44

WE D1D0EC
Figure 9: 16x2 (or 16x1) Level-Sensitive Single-Port RAM
Enable

WRITE
DECODER

1 of 16
DIN
16-LATCH
ARRAY
X6749
4
READ ADDRESS

MUX
Enable

WRITE
DECODER

1 of 16
DIN
16-LATCH
ARRAY
4
READ ADDRESS

MUX
G'
4

G1• • • G4
F1• • • F4
C1• • • C44

F'
WE D1/A4D0EC
4

H'
Figure 10: 32x1 Level-Sensitive Single-Port RAM (F and G addresses are identical)

September 18, 1996 (Version 1.04) 4-21
Fast Carry Logic
Each CLB F and G function generator contains dedicated
arithmetic logic for the fast generation of carry and borrow
signals. This extra output is passed on to the function gen-
erator in the adjacent CLB. The carry chain is independent
of normal routing resources.
Dedicated fast carry logic greatly increases the efficiency
and performance of adders, subtractors, accumulators,
comparators and counters. It also opens the door to many
new applications involving arithmetic operation, where the
previous generations of FPGAs were not fast enough or too
inefficient. High-speed address offset calculations in
microprocessor or graphics systems, and high-speed addi-
tion in digital signal processing are two typical applications.
The two 4-input function generators can be configured as a
2-bit adder with built-in hidden carry that can be expanded
to any length. This dedicated carry circuitry is so fast and
efficient that conventional speed-up methods like carry
generate/propagate are meaningless even at the 16-bit
level, and of marginal benefit at the 32-bit level.
This fast carry logic is one of the more significant features
of the XC4000 Series, speeding up arithmetic and counting
into the 70 MHz range.
The carry chain in XC4000E devices can run either up or
down. At the top and bottom of the columns where there
are no CLBs above and below, the carry is propagated to
the right. (See Figure 11.) In order to improve speed in the
high-capacity XC4000EX devices, which can potentially
have very long carry chains, the carry chain travels upward
only, as shown in Figure 12. This restriction should have lit-
tle impact, because the smallest XC4000EX device, the
XC4028EX, can accommodate a 64-bit carry chain in a sin-
gle column. Additionally, standard interconnect can be
used to route a carry signal in the downward direction.
Figure 13 on page 22 shows an XC4000E CLB with dedi-
cated fast carry logic. The carry logic in the XC4000EX is
similar, except that COUT exits at the top only, and the sig-
nal CINDOWN does not exist. As shown in Figure 13, the
carry logic shares operand and control inputs with the func-
tion generators. The carry outputs connect to the function
generators, where they are combined with the operands to
form the sums.
Figure 14 and Figure 15 on page 23 show the details of the
carry logic for the XC4000E and the XC4000EX respec-
tively. These diagrams show the contents of the box
labeled “CARRY LOGIC” in Figure 13. As shown, the
XC4000EX carry logic eliminated a multiplexer to reduce
delay on the pass-through carry chain. Additionally, the
multiplexer on the G4 path now has a memory-programma-
ble input, which permits G4 to directly connect to COUT.
G4 thus becomes an additional high-speed initialization
path for carry-in.
The dedicated carry logic is discussed in detail in Xilinx
document XAPP 013: “ Using the Dedicated Carry Logic in
XC4000 .” This discussion also applies to XC4000E
devices, and to XC4000EX devices when the minor logic
changes are taken into account.
The fast carry logic can be accessed by placing special
library symbols, or by using Xilinx Relationally Placed Mac-
ros (RPMs) that already include these symbols.
X6687
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
Figure 11: Available XC4000E Carry Propagation
Paths
X6610
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
Figure 12: Available XC4000EX Carry Propagation
Paths (dotted lines use general interconnect)

XC4000 Series Field Programmable Gate Arrays
4-22 September 18, 1996 (Version 1.04)
DQ
S/R
EC
YQ
Y
DIN
H
G
F
G
H
DQ
S/R
EC
XQ
DIN
H
G
F
H
X
H
F
G
G4
G3
G2
G1
F
F3
F2
F1
F4
F
CARRY
G
CARRY
CCDOWN
CARRY
LOGIC
D
CC UP K S/R EC
H1
X6699
OUT
IN
OUT IN
IN
COUT0
Figure 13: Fast Carry Logic in XC4000E CLB (shaded area not present in XC4000EX)

September 18, 1996 (Version 1.04) 4-23
Figure 14: Detail of XC4000E Dedicated Carry Logic
01
01
M
M
0
1
01
M
0
1
M
10
M
M0
3
M
1
M
I
G1
G4
F2
F1
F3
COUT
G2
G3
F4
CINUP
CIN DOWN
X2000
TO
FUNCTION
GENERATORS
M
M
M
COUT0
Figure 15: Detail of XC4000EX Dedicated Carry Logic (shaded areas show differences from XC4000E carry logic)
M
M
M
M
M
01
01
0
1
1
0
1
0
3
1
0
M
M
M
M
M
F4
G3
G2
G1
G4
F2
F1
F3
M
TO
FUNCTION
GENERATORS
COUT
COUT0
CIN UP X6701

XC4000 Series Field Programmable Gate Arrays
4-24 September 18, 1996 (Version 1.04)
Input/Output Blocks (IOBs)
User-configurable input/output blocks (IOBs) provide the
interface between external package pins and the internal
logic. Each IOB controls one package pin and can be con-
figured for input, output, or bidirectional signals.
Figure 16 shows a simplified block diagram of the
XC4000E IOB. A more complete diagram of the XC4000E
IOB can be found inFigure 42 on page 51, in the “Boundary
Scan” section. Figure 42 includes the boundary scan logic
in the IOB.
Figure 17 shows a simplified block diagram of the
XC4000EX IOB. The XC4000EX IOB contains some spe-
cial features not included in the XC4000E IOB. These fea-
tures are highlighted in Figure 17, and discussed
throughout this section. When XC4000EX special features
are discussed, they are clearly identified in the text. Any
feature not so identified is present in both XC4000E and
XC4000EX devices.
IOB Input Signals
Two paths, labeled I1 and I2 in Figure 16 and Figure 17,
bring input signals into the array. Inputs also connect to an
input register that can be programmed as either an edge-
triggered flip-flop or a level-sensitive latch.
The choice is made by placing the appropriate library sym-
bol. For example, IFD is the basic input flip-flop (rising
edge triggered), and ILD is the basic input latch (transpar-
ent-High). Variations with inverted clocks are available, and
some combinations of latches and flip-flops can be imple-
mented in a single IOB, as described in the
XACT Libraries
Guide .
The inputs can be globally configured for either TTL (1.2V,
default) or CMOS thresholds, using an option in the Make-
Bits program. There is a slight hysteresis of about 300mV.
The output levels are also configurable; the two global
adjustments of input threshold and output level are inde-
pendent.
Inputs of the low-voltage devices must be configured as
CMOS at all times. They can be driven by the outputs of all
5-Volt XC4000-Series devices, provided that the 5-Volt out-
puts are in TTL mode. They can also be driven by any TTL
output that does not exceed 3.7 V. 5-Volt XC3000-family
device outputs, for example, are TTL-compatible, but since
the output voltage can exceed 3.7 V, they cannot be used to
drive an XC4000L or XC4000XL input.
The inputs of XC4000-Series 5-Volt devices can be driven
by the outputs of any 3.3-Volt device, if the 5-Volt inputs are
in TTL mode.
Supported sources for XC4000-Series device inputs are
shown in Table 10.
Registered Inputs
The I1 and I2 signals that exit the block can each carry
either the direct or registered input signal.
The input and output storage elements in each IOB have a
common clock enable input, which, through configuration,
can be activated individually for the input or output flip-flop,
or both. This clock enable operates exactly like the EC pin
on the XC4000-Series CLB. It cannot be inverted within
the IOB.
The storage element behavior is shown in Table 11.
Table 11: Input Register Functionality
(active rising edge is shown)
1. Acceptable for XC4000XL if the designated 5-Volt
supply pad (VTT) is tied to 5V.
Table 10:Supported Sources for XC4000-Series Device
Inputs
Source
XC4000-Series Inputs
3.3V,
CMOS 5V, TTL 5V, CMOS
Any device, Vcc = 3.3 V,
CMOS outputs √√
Unreli-
able
Data
XC4000-Series, Vcc = 5 V,
TTL outputs √√
Any device, Vcc = 5 V,
TTL outputs (Voh ≤3.7 V) √√
Any device, Vcc = 5 V,
CMOS outputs Danger1√√
Mode Clock Clock
Enable DQ
Power-Up or
GSR XXXSR
Flip-Flop __/ 1* D D
0XXQ
Latch 1 1* X Q
01*DD
Both X 0 X Q
Legend:
X
__/
SR
0*
1*
Don’t care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)