Xilinx Kintex UltraScale FPGA KCU1250 User manual

KCU1250 Board
User Guide
UG1057 (v1.0) December 19, 2014

KCU1250 User Guide www.xilinx.com 2
UG1057 (v1.0) December 19, 2014
Revision History
The following table shows the revision history for this document.
Date Version Revision
12/19/2014 1.0 Initial Xilinx release.

KCU1250 User Guide www.xilinx.com 3
UG1057 (v1.0) December 19, 2014
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: KCU1250 Board Features and Operation
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
UltraScale FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
System Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
USB to Dual-UART Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
300 MHz LVDS Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Differential SMA MRCC Pin Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SuperClock-2 Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
User LEDs (Active-High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
User DIP Switches (Active-High) and I/O Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
User Push Buttons (Active-High). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
MGT Transceivers and Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FPGA Mezzanine Card HPC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
System Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
I2C Bus Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Appendix A: Default Jumper Settings
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Appendix B: VITA 57.1 FMC Connector Pinouts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Appendix C: Master Constraints File Listing
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
KCU1250 Board XDC Listing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Appendix D: System Controller
Main Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
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UG1057 (v1.0) December 19, 2014
Appendix F: Regulatory and Compliance Information
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Declaration of Conformity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Appendix F: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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KCU1250 User Guide www.xilinx.com 5
UG1057 (v1.0) December 19, 2014
Chapter 1
KCU1250 Board Features and Operation
Introduction
This user guide describes the components, features, and operation of the KCU1250
UltraScale™ FPGA GTH transceiver characterization board. The KCU1250 board provides the
hardware environment for characterizing and evaluating the GTH transceivers on an
UltraScale XCKU040-2FFVA1156E FPGA. The KCU1250 board schematic, bill-of-material
(BOM), layout files, and reference designs are available at the Kintex® UltraScale FPGA
KCU1250 Characterization Kit website.
FPGA Compatibility
The KCU1250 board is shipped with the Kintex UltraScale XCKU040-2FFVA1156E FPGA. The
board also supports other Kintex UltraScale device densities (XCKU035, XCKU060, and
XCKU075) in the pin-compatible FFVA1156 package. However, certain GTH transceivers that
are available in larger density devices are not available in the XCKU040 device (for example,
GTH QUAD_131 and GTH QUAD_132).
KCU1250 Board Features
• UltraScale XCKU040-2FFVA1156E FPGA
• BullsEye cable access to all 20 GTH transceivers on the UltraScale
XCKU040-2FFVA1156E FPGA
• Onboard power supplies for all necessary voltages
• Power connectors for optional use of external power supplies
• Digilent USB JTAG programming port
• System controller (Zynq-7000 AP SoC XC7Z010-CLG225)
• MGT power module supporting UltraScale FPGA GTH transceiver power requirements
• A fixed, 300 MHz 2.5V LVDS oscillator wired to multi-region clock capable (MRCC)
inputs
• Two pairs of differential MRCC inputs with SMA connectors
• SuperClock-2 module supporting programmable clock outputs
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KCU1250 User Guide www.xilinx.com 6
UG1057 (v1.0) December 19, 2014
Chapter 1: KCU1250 Board Features and Operation
• Samtec BullsEye connector pads for the FPGA GTH transceivers and reference clocks
• General purpose DIP switches, LEDs, pushbuttons, and test I/O
• Three VITA 57.1 FPGA mezzanine card (FMC) high pin count (HPC) connectors
• USB to dual-UART bridge
•I2Cbus
• PMBus connectivity to the boards digital power supplies
• Active cooling for the FPGA
The KCU1250 board block diagram is shown in Figure 1-1.
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Figure 1-1: KCU1250 Board Block Diagram
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KCU1250 User Guide www.xilinx.com 7
UG1057 (v1.0) December 19, 2014
Chapter 1: KCU1250 Board Features and Operation
Detailed Description
Figure 1-2 shows the KCU1250 board. Each numbered feature referenced in Figure 1-2 is
described in Table 1- 1 and in subsequent sections.
CAUTION! The KCU1250 board can be damaged by electrostatic discharge (ESD). Follow standard ESD
prevention measures when handling the board
CAUTION! Do not remove the rubber feet from the board. The feet provide clearance to prevent short
circuits on the back side of the board
IMPORTANT: Figure 1-2 is for reference only and might not reflect the current revision of the board.
X-Ref Target - Figu re 1-2
Figure 1-2: KCU1250 Board Features
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Send Feedback

KCU1250 User Guide www.xilinx.com 8
UG1057 (v1.0) December 19, 2014
Chapter 1: KCU1250 Board Features and Operation
Tab le 1- 1 describes the callouts in Figure 1-2.
Table 1-1: KCU1250 Board Features and Operation
Figure
1-2
Callout
Reference Designator Feature Description
1 U1 UltraScale XCKU040-2FFVA1156E FPGA, page 18
2 SW1 Power switch, page 10
3 J28 12V mini-fit connector, page 9
4J37, J38, J39, J40, J41, J42, J43 GTH transceiver connector pads Q224, Q225, Q226, Q227, Q228
page 28
5 U80 Digilent USB JTAG connector (micro-B receptacle), page 18
6J2 Platform USB JTAG connector (alternate access for programming
cables), page 18
7 J10 SD card connector (back-side of board), page 18
8 SW13 System controller configuration DIP switches, page 21
9 SW4 System controller power on reset (SYS_POR) button, page 20
10 J36 SuperClock-2 module, page 24
11 U42 300 MHz LVDS oscillator, page 23
12 DS17 FPGA DONE status LED, page 25
13 DS3 FPGA INIT status LED, page 25
14 SW7 FPGA PROGRAM pushbutton, page 27
15 DS18 12V system power status LED, page 14
16 DS4, DS5, DS6, DS7, DS8, DS9,
DS10, DS28, DS13, DS14, DS15
Status LEDS for FPGA logic, transceiver and utility power
17 SW2 Power regulation inhibitor switch for onboard regulators, page 13
18 J5, J25, J26, J27 External power supply connectors, page 13 and page 14
19 J46, J124 MGT transceiver power supply module, page 15
20 J21 FPGA and utility rails PMBUS connector, page 14
21 J4 MGT rails PMBUS connector, page 13
22 J1 Connector for USB to dual-UART bridge (mini-B receptacle), page 23
23 J99 Power connector for active heatsink, page 16
24 DS19, DS20, DS21, DS22, DS23,
DS24, DS25, DS26
User LEDs (active-High), page 25
25 SW8, SW9 User pushbuttons (active-High), page 27
26 SW3 User DIP switches (active-High), page 26
27 J95 User I/O header, page 27
28 JA2 FMC1 connector, page 35
29 JA3 FMC2 connector page 38
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KCU1250 User Guide www.xilinx.com 9
UG1057 (v1.0) December 19, 2014
Chapter 1: KCU1250 Board Features and Operation
Power Management
12V Input Power
The KCU1250 board receives 12V main power through J28 (callout 3, Figure 1-2) using the
12V AC adapter included with the KCU1250 board characterization kit. J28 is a 6-pin (2 x 3),
right angle, mini-fit connector.
CAUTION! When supplying 12V through J28, use only the power supply provided for use with this
board (Xilinx part number 3800033).
CAUTION! Do NOT use a 6-pin, PC ATX power supply connector with J28. The pinout of the 6-pin, PC
ATX connector is not compatible with J28 and the board will be damaged if an attempt is made to
power it from a PC ATX power supply connector.
12V power can also be provided through:
• Connector J73 (callout 31, Figure 1-2), which accepts an ATX hard drive 4-pin power
plug
• Connector J27 (callout 18, Figure 1-2), which can be connected to a bench-top power
supply
CAUTION! Because connector J73 provides no reverse polarity protection, use a power supply with a
current limit set at 6A maximum.
30 JA4 FMC3 connector page 41
31 J73 ATX power connector page 9
32 J83, J84, J85, J86 SMA connectors to differential MRCC pins on FPGA, page 23
33 U38 System controller
34 J3 System controller JTAG connector
35 DS1, DS12, DS16, DS27 System controller status LEDs
36 SW5, SW6, SW10, SW11, SW12 System controller GPIO pushbuttons
37 J36 JTAG chain select
Table 1-1: KCU1250 Board Features and Operation (Cont’d)
Figure
1-2
Callout
Reference Designator Feature Description
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UG1057 (v1.0) December 19, 2014
Chapter 1: KCU1250 Board Features and Operation
CAUTION! Do NOT apply 12V power to more than a single input source. For example, do not apply
power to J73 and J27 at the same time.
CAUTION! The KCU1250 board uses a P-channel MOSFET power switch (FDS6681Z, reference
designator Q1) that is rated for 20A @ 12V. It is critical that the power consumed by the DUT and
peripheral circuitry does not exceed this limit.
Power Switch
The KCU1250 board main power is turned on or off using the SW1 switch (callout 2,
Figure 1-2). When the switch is in the on position, power is applied to the board and the
green LED DS18 illuminates (callout 15, Figure 1-2).
Onboard Power Regulation
Figure 1-3 shows the onboard power supply architecture.
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UG1057 (v1.0) December 19, 2014
Chapter 1: KCU1250 Board Features and Operation
X-Ref Target - Figu re 1-3
Figure 1-3: KCU1250 Board Power Supply Block Diagram
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Send Feedback

KCU1250 User Guide www.xilinx.com 12
UG1057 (v1.0) December 19, 2014
Chapter 1: KCU1250 Board Features and Operation
The KCU1250 board uses power regulators and PMBus compliant digital PWM system
controllers from Maxim Integrated to supply the FPGA logic and utilities voltages listed in
Tab le 1- 2. The board can also be configured to use an external bench power supply for each
voltage. See Using External Power Sources.
Table 1-2: Onboard Power System Devices
Device Part
Number
Reference
Designator Description Power Rail Net Name Voltage
FPGA Logic
Maxim
MAX15301 U23 InTune Digital Point of Load (PoL) Controller, 36A VCCINT 0.95V
Maxim
MAX15301 U24 InTune Digital Point of Load (PoL) Controller, 8A VCCAUX 1.8V
Maxim
MAX15301 U26 InTune Digital Point of Load (PoL) Controller, 4A VCCBRAM 0.95V
Maxim
MAX15301 U27 InTune Digital Point of Load (PoL) Controller, 7A VCCO_HP 1.8V
Maxim
MAX15301 U28 InTune Digital Point of Load (PoL) Controller, 4A VCCO_HR 1.8V
Utility
Maxim
MAX15301 U31 InTune Digital Point of Load (PoL) Controller, 10A UTIL_5V0 5.0V
Maxim
MAX15301 U30 InTune Digital Point of Load (PoL) Controller, 10A UTIL_3V3 3.3V
Maxim
MAX15301 U29 InTune Digital Point of Load (PoL) Controller, 3A UTIL_2V5 2.5V
MGT Transceivers (monitoring only)
INA226 U50 Current shunt and power monitor with I2C
interface MGTAVCC 1.0V
INA226 U51 Current shunt and power monitor with I2C
interface MGTAVTT 1.2V
INA226 U52 Current shunt and power monitor with I2C
interface MGTVCCAUX 1.8V
System Controller
Maxim
MAX15053 U13 Fixed LDO regulator SYS_1V0 1.0V
Maxim
MAX15027 U33 Fixed LDO regulator VCC_1V2 1.2V
Maxim
MAX15027 U25 Fixed LDO regulator VCC_1V8 1.8V
Notes:
1. The output voltages of the Max15301 can be reprogrammed using the Maxim InTune Digital Power Tool [Ref 5].
However, extreme caution must be taken when attempting to modify any of the onboard regulators. An incorrectly
programmed regulator can damage onboard components.
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UG1057 (v1.0) December 19, 2014
Chapter 1: KCU1250 Board Features and Operation
Using External Power Sources
Each power rail for the FPGA logic and MGT transceivers has an associated Euro-Mag
spring-clamp terminal block (callout 18, Figure 1-2), which can be used to provide power
from an external source (Tabl e 1-3).
CAUTION! Do NOT apply power to any of the FPGA logic external power supply connectors without
first disabling the associated regulator or regulators. Failing to disable the regulator can damage the
board.
Each onboard FPGA logic regulator can be disabled using its respective power regulation
inhibitor dip switch (callout 17, Figure 1-2). A regulator is disabled when the power
regulation inhibitor switch is set to the on position. Table 1 - 3 lists external power
connectors for the different power rails.
Table 1-3: FPGA Logic and MGT Transceiver Rails
Power Rail
Net Name
External Supply
Connector
Power Regulation
Jumper
FPGA Logic
VCCINT
J25
J22
VCCAUX J23
VCCBRAM J20
VCCO_HP J19
VCCO_HR J18
MGT Transceiver
MGTAVCC
J26
NA
MGTAVTT NA
MGTVCCAUX NA
Notes:
1. The MGT power module must be removed before providing external power to
any of the transceiver rails (see MGT Transceiver Power Module, page 15)
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KCU1250 User Guide www.xilinx.com 14
UG1057 (v1.0) December 19, 2014
Chapter 1: KCU1250 Board Features and Operation
Default Jumper and Switch Positions
A list of jumpers and switches and their required positions for normal board operation is
provided in Appendix A, Default Jumper Settings.
Monitoring Voltage and Current
Voltage and current monitoring and control for the Maxim power system is available
through either the KCU1250 system controller or via the Maxim PowerTool™ software
graphical user interface.
The KCU1250 system controller is the simplest and most convenient way to monitor the
voltage and current values for the power rails listed in Tabl e 1-3. For details on how to use
this built-in feature, see Power Monitoring Data Menu in Appendix D.
The KCU1250 board includes these PMBus connectors:
• J21 (callout 20, Figure 1-2), for use with the Maxim USB-to-PMBus interface dongle
(MAXPOWERTOOL002 [Ref 8]) and the InTune Digital Power GUI.
•J4(callout21,Figure 1-2) is used to connect to the MGT power module PMBus using
the vendor's application tool (for example, Texas Instruments USB-to-GPIO interface
adaptor (EVM-P960 [Ref 9]) and the Fusion Digital Power GUI).
The onboard Maxim power controllers (U23, U24, U26, U27, U28, U29, U30, and U31) by
default are isolated from the MGT power modules PMBus. However, the two interfaces can
be linked by removing J8 next to the MGT power module PMBus connector J4. This
configuration is required when using a Maxim MGT power module to allow for monitoring
and controlling both FPGA power rails and the transceiver power rails using the Maxim
InTune Digital Power GUI.
X-Ref Target - Figure 1-4
Figure 1-4:
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KCU1250 User Guide www.xilinx.com 15
UG1057 (v1.0) December 19, 2014
Chapter 1: KCU1250 Board Features and Operation
More information about the power system components used on the KCU1250 board is
available from the Maxim Integrated InTune digital power website [Ref 5].
MGT Transceiver Power Module
The KCU1250 board includes one MGT transceiver power module (callout 19, Figure 1-2).
The MGT power modules supply the MGTAVCC, MGTAVTT, and MGTVCCAUX power rails,
which connect to the FPGA MGT transceivers. MGT power modules from third-party vendors
are provided with the KCU1250 board for evaluation (Maxim Integrated MAXIM001 and
Texas Instruments PMP9463 [Ref 5]). Either one of the modules can be plugged into J46 and
J124 on the outlined and labeled power module locations shown in Figure 1-5.
Tab le 1-4 lists the nominal voltage values for MGTAVCC, MGTAVTT, and MGTVCCAUX power
rails. It also lists the maximum current rating for each rail supplied by MGT modules
included with the KCU1250 board.
The MGT transceiver power rails can also be supplied externally. The external supply
connectors are described in Table 1-3.
CAUTION! The MGT Power Module MUST be removed when providing external power to the MGT
transceiver rails.
Information about the available MGT power modules included with the KCU1250 board
characterization kit is available from the vendor websites [Ref 5].
X-Ref Target - Figure 1-5
Figure 1-5: Mounting Location, MGT Power Module
Table 1-4: MGT Power Modules
MGT Transceiver
Rail Net Name Nominal Voltage Maximum Current
Rating
MGTAVCC 1.0V 12A
MGTAVTT 1.2V 20A
MGTVCCAUX 1.8V 2.5A
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KCU1250 User Guide www.xilinx.com 16
UG1057 (v1.0) December 19, 2014
Chapter 1: KCU1250 Board Features and Operation
Active Heatsink Power Connector
An active heat sink (Figure 1-6) is provided for the FPGA (callout 23, Figure 1-2). A 12V fan
is affixed to the heat sink and is powered from the 3-pin friction lock header J99
(Figure 1-7).
X-Ref Target - Figure 1-6
Figure 1-6: Active FPGA Heat Sink
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KCU1250 User Guide www.xilinx.com 17
UG1057 (v1.0) December 19, 2014
Chapter 1: KCU1250 Board Features and Operation
The fan power connections are detailed in Table 1-6:
Figure 1-7 shows the heat sink fan power connector J99.
Table 1-5: Fan Power Connections
Fan Wire Header Pin
Black J99.1 - GND
Red J99.2 - 12V
Blue J99.3 - NC
X-Ref Target - Figure 1-7
Figure 1-7: Heat Sink Fan Power Connector J99
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KCU1250 User Guide www.xilinx.com 18
UG1057 (v1.0) December 19, 2014
Chapter 1: KCU1250 Board Features and Operation
UltraScale FPGA
The KCU1250 board is populated with the UltraScale XCKU040-2FFVA1156E FPGA at U1
(callout 1, Figure 1-2). For further information on UltraScale FPGAs, see UltraScale
Architecture and Product Overview (DS890) [Ref 1].
FPGA Configuration
The FPGA is configured though one of these options:
• Digilent embedded USB JTAG connector (callout 5, Figure 1-2)
• Platform cable USB JTAG cable connector (callout 6, Figure 1-2)
• SD card using the Zynq-7000 AP SoC system controller in 8-bit SelectMAP mode
(callout 7, Figure 1-2)
The KCU1250 board includes an embedded USB-to-JTAG configuration module (Digilent
U80), which allows a host computer to access the JTAG chain using a standard A to micro-B
USB cable. Alternatively, a JTAG connector (J2) is available to access the JTAG chain using
the Xilinx platform cable USB II configuration cable. Additionally, the FPGA can be
configured from an SD card installed in J10 with the help of the system controller U38,
which reads a predefined bit file from the SD card and configures the FPGA in 8-bit
SelectMAP configuration mode. See FPGA CONFIG Menu.
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KCU1250 User Guide www.xilinx.com 19
UG1057 (v1.0) December 19, 2014
Chapter 1: KCU1250 Board Features and Operation
The JTAG chain of the KCU1250 board is shown in Figure 1-8. By default, only the UltraScale
FPGA is part of the chain (J6 jumper uninstalled). Installing the J6 jumper enables an 8-bit
bus transceiver (U69, SN74AVC8T245) and adds the FMC interfaces to the chain.
PROGRAM Pushbutton
Pressing the PROGRAM pushbutton SW7 (callout 14, Figure 1-2) asserts the active-Low
program pin of the FPGA.
X-Ref Target - Figure 1-8
Figure 1-8: JTAG Chain
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KCU1250 User Guide www.xilinx.com 20
UG1057 (v1.0) December 19, 2014
Chapter 1: KCU1250 Board Features and Operation
DONE LED
The DONE LED DS17 (callout 12, Figure 1-2) indicates the state of the DONE pin of the
FPGA. When the DONE pin is High, DS17 lights up indicating the FPGA is successfully
configured.
INIT LED
The dual-color INIT LED DS3 (callout 13, Figure 1-2) indicates the FPGA initialization status.
During FPGA initialization, the INIT LED illuminates RED. When FPGA initialization has
completed, the LED illuminates GREEN.
System Controller
The KCU1250 board utilizes a Xilinx XC7Z010-CLG225 Zynq-7000 AP SoC U38 (callout 33,
Figure D-1) system controller that can be used to:
• Configure the FPGA using predefined selection of configuration bit files on an SD card
using 8-bit SelectMAP configuration
• Select the output frequencies of the SuperClock-2 module
• Monitor the onboard power system (PMBus)
See Appendix D, System Controller for information on the system controller menu options.
System Controller Reset
The SYS_POR pushbutton SW4 (callout 9, Figure 1-2) asserts the active-Low system
controller Power-On Reset (SYS_POR). When SYS_POR is reasserted, the system controller is
reconfigured using the controller design stored on an attached SPI flash.
System Controller Status LEDs
DS1, DS12, DS16, and DS27 (callout 35, Figure 1-2) show the system controller INIT_B,
DONE, STATUS, and ERROR status, respectively.
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