Xilinx Spartan-3A DSP FPGA Series Use and care manual

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Revision history
Revision Date Comments
0.1 June, 2007 Preliminary version.
0.2 July, 2007 Added appendix 1.
0.3 July, 2007 Updated version for final review.
1.0 August, 2007
•Updated FMC information
•Updated support information
•Adjusted page numbering to meet specifications.
•FPGA pinout for DDR2 inteface added
•FPGA pinout for USB/System ACE inteface added
1.1 September, 2007
•Known issues section added
•Limitation of DDR2 clock rate to 133 MHz
•Soft Touch connector not compliant with Agilent probes
•FMC connector is in violation of some rules of the standard
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Version 1.1
First edition, August, 2007

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Introduction
5
Introduction
Congratulations on the purchase of the XtremeDSP Spartan-3A DSP Development Board.
Outstanding features and potential applications
The XtremeDSP Spartan-3A DSP Development Board uses, as its name implies, the new Spartan-3A DSP series
of FPGAs from the Xilinx XtremeDSP product line. These devices offer developers great flexibility, a wide
range of peripherals, and a cost-efficient solution to accelerate the development of new products. It is ideally
suited for consumer-oriented wireless and multimedia video applications where cost-effective solutions are
essential.
Document organization
This document is organized as follows:
Hardware overview presents the major hardware elements of the XtremeDSP Spartan-3A DSP Development
Board, including connectors and various other components.
Configuration options presents the methods of configuring the XtremeDSP Spartan-3A DSP Development
Board.
Known issues introduces the issues remaining with the XtremeDSP Spartan-3A DSP Development Board at the
time of release.
Specifications outlines the major specifications of the XtremeDSP Spartan-3A DSP Development Board.
Conventions
In a procedure containing several steps, the operations that the user has to execute are numbered (1, 2, 3…). The
diamond (♦) is used to indicate a procedure containing only one step, or secondary steps. Lowercase letters (a, b,
c…) can also be used to indicate secondary steps in a complex procedure.
The abbreviation NC is used to indicate no connection.
Capitals are used to identify any term marked as is on an instrument, such as the names of connectors, buttons,
indicator lights, etc. Capitals are also used to identify key names of the computer keyboard.
All terms used in software, such as the names of menus, commands, dialog boxes, text boxes, and options, are
presented in bold font style.
The abbreviation N/A is used to indicate something that is not applicable or not available at the time of press.
Note
The screen captures in this document are taken from the software version available at the time of press. For this
reason, they may differ slightly from what appears on your screen, depending on the software version that you
are using. Furthermore, the screen captures may differ from what appears on your screen if you use different
appearance settings.

XtremeDSP Spartan-3A DSP Development Board - Technical reference guide - v1.1
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Additional support resources
All the necessary information regarding the XtremeDSP Spartan-3A DSP Development Board is available on the
Xilinx Web site at www.xilinx.com/s3adsp_db.
Xilinx is firmly committed to providing the highest level of customer service and product support. If you
experience any difficulties when using the XtremeDSP Spartan-3A DSP Development Board or if it fails to
operate as described, we suggest that you first consult the present document, then, if you are still in need of
assistance, you can visit the Xilinx Web site and search the database of silicon and software questions and
answers, or open a technical support case in WebCase at www.xilinx.com/support.

Table of contents
7
Table of contents
Introduction ........................................................................................................................................................... 5
Outstanding features and potential applications.................................................................................................... 5
Document organization ......................................................................................................................................... 5
Conventions........................................................................................................................................................... 5
Additional support resources................................................................................................................................. 6
List of figures and tables ....................................................................................................................................... 9
Hardware overview......................................................................................................................11
XtremeDSP Spartan-3A DSP Development Board block diagram..................................................................... 11
XtremeDSP Spartan-3A DSP Development Board parts and functions.............................................................. 12
Top ......................................................................................................................................................... 12
Bottom ........................................................................................................................................................ 26
FMC expansion connector................................................................................................................................... 29
DDR2 memory .................................................................................................................................................... 30
DDR2 memory expansion........................................................................................................................... 30
DDR2 clock signal...................................................................................................................................... 30
DDR2 signaling .......................................................................................................................................... 30
MIG compatibility ...................................................................................................................................... 30
I2C bus addressing............................................................................................................................................... 30
Configuration options..................................................................................................................31
JTAG configuration............................................................................................................................................. 31
Board flash memory configuration...................................................................................................................... 32
SPI flash memory configuration.......................................................................................................................... 32
Specifications................................................................................................................................33
General specifications ......................................................................................................................................... 33
Maximum power consumption............................................................................................................................ 33
FPGA .................................................................................................................................................................. 33
Memory............................................................................................................................................................... 33
Connectors and interfaces ................................................................................................................................... 34
Known issues.................................................................................................................................35
Appendix 1 Clock generator programming..............................................................................37
Installing the clock generator software................................................................................................................ 37
Generating an SVF file........................................................................................................................................ 37
Downloading to the XtremeDSP Spartan-3A DSP Development Board ............................................................ 40

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List of figures and tables
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List of figures and tables
Figure 1 XtremeDSP Spartan-3A DSP Development Board block diagram ..............................................................11
Figure 2 XtremeDSP Spartan-3A DSP Development Board top view ....................................................................... 12
Figure 3 XtremeDSP Spartan-3A DSP Development Board power supply diagram ................................................. 19
Figure 4 XtremeDSP Spartan-3A DSP Development Board bottom view................................................................. 26
Figure 5 XtremeDSP Spartan-3A DSP Development Board JTAG chain.................................................................. 31
Figure 6 IDT Programmable Clock ............................................................................................................................ 37
Figure 7 Detailed I/O configuration of the 5V9885.................................................................................................... 38
Figure 8 Assigning the register settings...................................................................................................................... 39
Figure 9 Programming the XtremeDSP Spartan-3A DSP Development Board with iMPACT ................................. 40
Table 1 FPGA USB/System ACE interface pinout..................................................................................................... 13
Table 2 Ethernet PHY default configuration .............................................................................................................. 14
Table 3 Soft Touch connector pin assignments .......................................................................................................... 15
Table 4 FMC expansion connector pin assignments (1)............................................................................................. 16
Table 5 FMC expansion connector pin assignments (2)............................................................................................. 17
Table 6 Mictor pin assignments.................................................................................................................................. 18
Table 7 FPGA I/O bank voltage rail........................................................................................................................... 20
Table 8 Clock generator default settings..................................................................................................................... 20
Table 9 I2C FPGA pin assignments ............................................................................................................................ 20
Table 10 User-defined button FPGA pin assignments................................................................................................ 21
Table 11 Serial port FPGA pin assignments............................................................................................................... 22
Table 12 Reset connection.......................................................................................................................................... 22
Table 13 Configuration jumpers ................................................................................................................................. 22
Table 14 User-defined DIP switch FPGA pin assignments ........................................................................................ 23
Table 15 User-defined LED FPGA pin assignments .................................................................................................. 23
Table 16 Configuration DIP switch functions ............................................................................................................ 23
Table 17 Configuration modes ................................................................................................................................... 24
Table 18 Status LED signals....................................................................................................................................... 24
Table 19 Audio connectors ......................................................................................................................................... 25
Table 20 FPGA DDR2 interface pinout...................................................................................................................... 27
Table 21 I2C slave device addresses ........................................................................................................................... 30
Table 22 FMC standard rule and recommendation violations .................................................................................... 35
Table 23 Register configuration.................................................................................................................................. 39

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Hardware overview
11
Hardware overview
This chapter presents an overview the XtremeDSP Spartan-3A DSP Development Board by describing its parts
and functions.
XtremeDSP Spartan-3A DSP Development Board block diagram
The XtremeDSP Spartan-3A DSP Development Board can be represented by the following block diagram:
Figure 1 XtremeDSP Spartan-3A DSP Development Board block diagram

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XtremeDSP Spartan-3A DSP Development Board parts and functions
Physically, the XtremeDSP Spartan-3A DSP Development Board is laid out as follows:
Top
2113 5 9 12 13 14 15
17
18
192025 22
27 2628
29
31
33
32
21
10
16
81 4 7
6
35
34
23
36
24
30
Figure 2 XtremeDSP Spartan-3A DSP Development Board top view
1. USB controller
A Cypress CY7C67300 embedded USB host controller provides Hi-speed USB connectivity for the board.
The USB controller supports host and peripheral modes of operation (see 2and 3). The USB controller also
has two serial interface engines (SIE) that can be used independently. SIE1 is connected to the USB host port
(3). SIE2 is connected to the USB peripheral port (2).
The USB controller is equipped with an internal microprocessor to assist in processing USB commands. The
firmware for this processor may be stored in its dedicated I2C EEPROM (U41) or can be downloaded from a
host computer through the USB peripheral port (below). Jumper JP1 can be installed (shorting pins 1 and 2)
to prevent the USB controller from executing firmware stored in the I2C EEPROM.
The FPGA pins used for the USB interface are shared with the System ACE interface. See the FPGA pinout
in the table below.

Hardware overview
13
Table 1 FPGA USB/System ACE interface pinout
FPGA pin Description FPGA pin Description
AE13 sysace_clk_in (System ACE only) AD21 sace_usb_a_1
AE23 sace_mpce (System ACE only) AA17 sace_usb_a_2
AA18 sysace_mpirq (System ACE only) AE21 sace_usb_a_3
W17 usb_csn (USB only) V16 sace_usb_a_4
AD22 usb_hpi_int (USB only) AC20 sace_usb_a_5
AC21 sace_usb_oen AD20 sace_usb_a_6
V17 sace_usb_wen U16 sace_usb_a_7
AF4 sace_usb_a_0 AF20 sace_usb_a_8
W9 sace_usb_a_1 AE20 sace_usb_a_9
Y9 sace_usb_a_2 AC19 sace_usb_a_10
AE3 sace_usb_a_3 AF19 sace_usb_a_11
AF3 sace_usb_a_4 AE19 sace_usb_a_12
V15 sace_usb_a_5 AD19 sace_usb_a_13
U15 sace_usb_a_6 AC16 sace_usb_a_14
Y17 sace_usb_a_0 AB16 sace_usb_a_15
2. USB peripheral port
Type B connector. Used to connect peripheral USB devices to the XtremeDSP Spartan-3A DSP Development
Board.
3. USB host port
Type A connector. Used to connect a host device to the XtremeDSP Spartan-3A DSP Development Board.
4. AC’97 SoundaMAX codec
Analog Devices AD1981B. The device supports 16-bit stereo audio and sampling rates up to 48 kHz. The
sampling rate for recording and playback may also be different.
Note
The codec’s reset is shared with the reset signal of the flash memory devices. It is designed to be asserted
when the development board is turned on or reset.
5. DVI connector
The DVI connector is used to connect an external video monitor (DVI or VGA) to the XtremeDSP Spartan-
3A DSP Development Board.
Note
The VGA monitor can be connected to the development board with a DVI-to-VGA adaptor (sold separately).
6. Display controller device
The DVI circuitry uses a Chrontel CH7301C capable of 24-bit color and 1600 × 1200-pixel resolution. The
display controller device drives the digital and analog signals to the DVI connector (5). The display controller
device is controlled through the I2C bus.
The DVI connector supports the I2C protocol, allowing the development board to read a monitor’s
configuration parameters. The parameters can then be read by the FPGA through the I2C bus. See I2C bus
addressing for details.

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7. Board flash PROM
Xilinx XCF32P. This flash PROM is used to program the development board’s FPGA. The flash PROM can
hold up to two distinct configuration images (up to four compressed configuration images) that can be
accessed through the configuration DIP switches. You must use the same configuration DIP switches to
configure the FPGA from the platform flash PROM. See 33 for details.
8. Ethernet PHY
Marvell Alaska 88E1111 PHY device. This PHY supports 10Base-T, 100Base-TX, and 1000Base-T
(Gigabit) Ethernet. The PHY is connected to the board’s Ethernet connector (9). The Ethernet PHY is
initialized under its default configuration when the development board is turned on or reset. Jumper JP2
selects whether the PHY’s default is RGMII mode (pins 2-3) or GMII mode (pins 1-2). The table below
outlines the default configuration of the Ethernet PHY. You can modify this configuration through software.
Table 2 Ethernet PHY default configuration
Configuration pin Board connection Bit 2 Bit 1 Bit 0
CONFIG0 Vcc 2.5 V PHYADR[2] = 1 PHYADR[1] = 1 PHYADR[0] = 1
CONFIG1 Ground ENA_PAUSE = 0 PHYADR[4] = 0 PHYADR[3] = 0
CONFIG2 Vcc 2.5 V ANEG[3] = 1 ANEG[2] = 1 ANEG[1] = 1
CONFIG3 Vcc 2.5 V ANEG[0] = 1 ENA_XC = 1 DIS_125 = 1
CONFIG4 Vcc 2.5 V or
LED_DUPLEX
HCWCFG_MODE[2] =
0 or 1
HCWCFG_MODE[1] =
1
HCWCFG_MODE[0] = 1
CONFIG5 Vcc 2.5 V DIS_FC = 1 DIS_SLEEP = 1 HCWCFG_MODE[3] = 1
CONFIG6 LED_RX SEL_BDT = 0 INT_POL = 1 75 Ω/50 Ω= 0
9. Ethernet port
10Base-T, 100Base-TX, and 1000Base-T (Gigabit) Ethernet port. Connected to the Ethernet PHY (8).
10.Flash memory
Intel StrataFlash embedded memory JS28F256P30B95. Provides the development board with 32-MB flash
memory. This memory provides non-volatile storage for data, software, or bitstreams. The device is 16 bits
wide. This flash memory can also be used to program the FPGA.
Note
The FMC module cannot be used when using the flash memory. Make sure that the FMC adjustable power
supply is configured for 3.3 V to use the flash memory. See FMC expansion connector for instructions about
how to properly configure the adjustable power supply.
The Flash memory shares the same data bus as the ZBT synchronous SRAM (16).
11.PS/2 connectors
The XtremeDSP Spartan-3A DSP Development Board is equipped with two PS/2 connectors for a keyboard
and mouse. Bidirectional level shifting transistors allow the FPGA’s 1.8-V and 3.3-V I/O to interface with the
5-V I/O of the PS/2 connectors, which are powered directly from the 5-V power source of the development
board. Connector J5 is used to connect a mouse, while connector J6 is used to connect a keyboard.
Note
Make sure that the power load of connected PS/2 devices does not overload the AC adapter of the
development board.
12.Power connector
Center positive, 2.1-mm × 5.5-mm barrel-type plug. Used to connect the supplied AC adaptor.
13.Power switch
Allows you to turn the XtremeDSP Spartan-3A DSP Development Board on and off by controlling the 12-V
supply of the board.
14.Soft Touch connector
The Soft Touch connector (J12) allows you to monitor signals between the FPGA and the FMC expansion
connector.

Hardware overview
15
Table 3 Soft Touch connector pin assignments
Soft Touch pin FPGA pin Description Soft Touch pin FPGA pin Description
A1 H2 FMC_LA18_P B1 M8 FMC_LA19_P
A2 NC GND B2 NC GND
A3 H1 FMC_LA18_N B3 M7 FMC_LA19_N
A4 J5 FMC_LA31_P B4 K3 FMC_LA32_P
A5 NC GND B5 NC GND
A6 J4 FMC_LA31_N B6 K2 FMC_LA32_N
A7 L4 FMC_LA29_P B7 K5 FMC_LA30_P
A8 NC GND B8 NC GND
A9 L3 FMC_LA29_N B9 K4 FMC_LA30_N
A10 P8 FMC_LA16_P B10 L10 FMC_LA17_P
A11 NC GND B11 NC GND
A12 P9 FMC_LA16_N B12 L9 FMC_LA17_N
A13 U1 FMC_LA14_P B13 R8 FMC_LA15_P
A14 NC GND B14 NC GND
A15 U2 FMC_LA14_N B15 R7 FMC_LA15_N
A16 M10 FMC_LA12_P B16 K6 FMC_LA13_P
A17 NC GND B17 NC GND
A18 M9 FMC_LA12_N B18 L7 FMC_LA13_N
A19 T5 FMC_LA33_P B19 V1 FMC_LA11_P
A20 NC GND B20 NC GND
A21 U4 FMC_LA33_N B21 V2 FMC_LA11_N
A22 P7 FMC_LA24_P B22 R5 FMC_LA25_P
A23 NC GND B23 NC GND
A24 P6 FMC_LA24_N B24 R6 FMC_LA25_N
A25 U5 FMC_LA26_P B25 T10 FMC_LA27_P
A26 NC GND B26 NC GND
A27 V5 FMC_LA26_N B27 T9 FMC_LA27_N
15.FMC expansion connector
Samtec ASP-127796-01. The FMC expansion connector (J13) follows the VITA 57.1 FMC standard and is
used in low pin count (LPC) format. See FMC expansion connector for details.
Note
The Flash Memory and ZBT synchronous SRAM cannot be used when using an FMC module. Make sure
that the FMC adjustable power supply is configured for the voltage specified by the FMC module to use the
FMC module properly. See FMC expansion connector for instructions about how to properly configure the
adjustable power supply.

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Table 4 FMC expansion connector pin assignments (1)
FMC pin FPGA pin Signal FMC pin FPGA pin Signal
C1 NC GND D1 M2 PGC2M
C2 NC DP0C2MP D2 NC GND
C3 NC DP0C2MN D3 NC GND
C4 NC GND D4 NC GBTCLK0M2CP
C5 NC GND D5 NC GBTCLK0M2CN
C6 NC DP0M2CP D6 NC GND
C7 NC DP0M2CN D7 NC GND
C8 NC GND D8 G6 LA28PCC
C9 NC GND D9 H7 LA28NCC
C10 L4 LA29P D10 NC GND
C11 L3 LA29N D11 D3 LA00P
C12 NC GND D12 E4 LA00N
C13 NC GND D13 NC GND
C14 K5 LA30P D14 E3 LA01P
C15 K4 LA30N D15 F4 LA01N
C16 NC GND D16 NC GND
C17 NC GND D17 K7 LA02P
C18 J5 LA31P D18 J6 LA02N
C19 J4 LA31N D19 NC GND
C20 NC GND D20 M5 LA03P
C21 NC GND D21 M6 LA03N
C22 K3 LA32P D22 NC GND
C23 K2 LA32N D23 N5 LA04P
C24 NC GND D24 N4 LA04N
C25 NC GND D25 NC GND
C26 T5 LA33P D26 N1 LA05P
C27 U4 LA33N D27 N2 LA05N
C28 NC GND D28 NC GND
C29 NC GND D29 A25 TCK
C30 AF23 SCL D30 E23 TDI
C31 AE25 SDA D31 NC TDO
C32 NC GND D32 NC 3P3VAUX
C33 NC GND D33 D4 TMS
C34 NC GA0 (ground) D34 NC TRSTL
C35 NC 12P0V D35 NC GA1 (gnd)
C36 NC GND D36 NC 3P3V

Hardware overview
17
FMC pin FPGA pin Signal FMC pin FPGA pin Signal
C37 NC 12P0V D37 NC GND
C38 NC GND D38 NC 3P3V
C39 NC 3P3V D39 NC GND
C40 NC GND D40 NC 3P3V
Table 5 FMC expansion connector pin assignments (2)
FMC pin FPGA pin Signal FMC pin FPGA pin Signal
G1 NC GND H1 NC VREFAM2C
G2 T3 CLK0C2MP H2 G1 PRSNTM2CL
G3 T4 CLK0C2MN H3 NC GND
G4 NC GND H4 U3 CLK0M2CP
G5 NC GND H5 V4 CLK0M2CN
G6 L10 LA17P H6 NC GND
G7 L9 LA17N H7 F5 LA06P
G8 NC GND H8 G4 LA06N
G9 H2 LA18P H9 NC GND
G10 H1 LA18N H10 B2 LA07P
G11 NC GND H11 B1 LA07N
G12 M8 LA19P H12 NC GND
G13 M7 LA19N H13 E1 LA08P
G14 NC GND H14 F2 LA08N
G15 J7 LA20P H15 NC GND
G16 H6 LA20N H16 J8 LA09P
G17 NC GND H17 J9 LA09N
G18 K9 LA21P H18 NC GND
G19 K8 LA21N H19 G3 LA10P
G20 NC GND H20 F3 LA10N
G21 M4 LA22P H21 NC GND
G22 M3 LA22N H22 V1 LA11P
G23 NC GND H23 V2 LA11N
G24 N6 LA23P H24 NC GND
G25 N7 LA23N H25 M10 LA12P
G26 NC GND H26 M9 LA12N
G27 P7 LA24P H27 NC GND
G28 P6 LA24N H28 K6 LA13P
G29 NC GND H29 L7 LA13N
G30 R5 LA25P H30 NC GND
G31 R6 LA25N H31 U1 LA14P

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FMC pin FPGA pin Signal FMC pin FPGA pin Signal
G32 NC GND H32 U2 LA14N
G33 U5 LA26P H33 NC GND
G34 V5 LA26N H34 R8 LA15P
G35 NC GND H35 R7 LA15N
G36 T10 LA27P H36 NC GND
G37 T9 LA27N H37 P8 LA16P
G38 NC GND H38 P9 LA16N
G39 NC VADJ H39 NC GND
G40 NC GND H40 NC VADJ
16.ZBT synchronous SRAM
ISSI IS61NLP25636A-200TQL. The ZBT synchronous SRAM is high-speed, low-latency external memory
for the FPGA. The memory is organized as 256 K × 36 bits, providing a 32-bit data bus supporting four
parity bits.
Note
The FMC module cannot be used when using the ZBT synchronous SRAM. Make sure that the FMC
adjustable power supply is configured for 3.3 V to use the memory. See FMC expansion connector for
instructions about how to properly configure the adjustable power supply.
The ZBT synchronous SRAM shares the same data bus as the flash memory (10).
17.Mictor
The mictor (J14) allows you to monitor up to 32 single-ended signals from the FPGA.
Table 6 Mictor pin assignments
Mictor pin FPGA pin Description Mictor pin FPGA pin Description
1 NC NC 2 NC NC
3 NC GND 4 NC NC
5 A12 SE_CLK_IN 6 D13 SE_CLK_OUT
7 C10 SE_IO_9 8 B7 SE_IO_17
9 D10 SE_IO_11 10 B6 SE_IO_19
11 A9 SE_IO_7 12 NC 3.3V
13 B9 SE_IO_5 14 A4 SE_IO_21
15 B8 SE_IO_13 16 G9 SE_IO_23
17 A8 SE_IO_15 18 B4 SE_IO_25
19 C8 SE_IO_3 20 G10 SE_IO_27
21 C7 SE_IO_1 22 B3 SE_IO_28
23 K12 SE_IO_0 24 F7 SE_IO_29
25 G12 SE_IO_2 26 C6 SE_IO_16
27 K11 SE_IO_4 28 E7 SE_IO_18
29 H9 SE_IO_6 30 C5 SE_IO_20
31 J12 SE_IO_8 32 E10 SE_IO_22
33 H10 SE_IO_10 34 D9 SE_IO_24
35 J11 SE_IO_12 36 D6 SE_IO_26

Hardware overview
19
Mictor pin FPGA pin Description Mictor pin FPGA pin Description
37 H12 SE_IO_14 38 D8 SE_IO_30
39 NC GND 40 NC GND
41 NC GND 42 NC GND
43 NC GND
18.Power supply devices
The power supply circuitry of the XtremeDSP Spartan-3A DSP Development Board generates 0.9 V, 1.2 V,
1.8 V, 2.5 V, 3.3 V, and 5 V, as well as one adjustable voltage to power the components of the board. The
1.2 V (PS3), 1.8 V (PS5), 2.5 V (PS2), 3.3 V (PS4), and adjustable (PS1) supplies are driven by Linear
Technology LTM4601 switching power regulators. The regulators are driven by a 753-kHz clock, making
them run synchronously and reducing noise caused by beat frequencies. The clocks sent to each regulator are
out of phase to reduce reflected noise at the input.
The adjustable device is user-configurable through the FPGA and is used for the VCCIO of the FPGA bank
connected to the FMC expansion connector. When no FMC expansion module is present, the output voltage
of PS1 should be set to 3.3 V with the I2C bus interface to configure the digital potentiometer (U28). See I2C
bus addressing for details.
The diagram in Figure 3 illustrates the power supply architecture and maximum current handling by each
supply. The typical operating currents are significantly below the maximum capacity. The XtremeDSP
Spartan-3A DSP Development Board is normally shipped with a 60-W power supply, which should be
suitable for most applications.
Figure 3 XtremeDSP Spartan-3A DSP Development Board power supply diagram
19.Expansion connector
This expansion connector is not used by the XtremeDSP Spartan-3A DSP Development Board.
20.FPGA
XC3SD3400A-4FGG676C Xilinx Spartan-3A DSP FPGA. The board supports configuration in several
modes: JTAG, master serial, slave serial, master SelectMAP, slave SelectMAP, byte-wide peripheral
interface (BPI) up, BPI down, and SPI modes. See Configuration options for details.
The FPGA is also equipped with four I/O banks. The I/O voltage applied to each bank is summarized below.

XtremeDSP Spartan-3A DSP Development Board - Technical reference guide - v1.1
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Table 7 FPGA I/O bank voltage rail
FPGA bank I/O voltage rail
0 Adjustable (2.5 V or 3.3 V)
1 1.8 V
2 3.3 V
3 Adjustable (1.5 V, 1.8 V, 2.5 V, or 3.3 V)
21.Clock generator
IDT IDT5V9885PFGI. The clock generator is used to generate different clocks on the XtremeDSP Spartan-
3A DSP Development Board. The following table summarizes the default settings of output clocks. The clock
generator can be programmed through the I2C interface. See I2C bus addressing for details.
Table 8 Clock generator default settings
Clock output Default frequency Clock usage
1 25 MHz Ethernet PHY clock.
2 14.31818 MHz Audio codec clock.
3 12 MHz USB clock.
4_P 33 MHz System ACE clock.
4_N 33 MHz FPGA clock (FPGA pin AE13).
5_P 200 MHz FPGA differential clock P (FPGA pin AA13).
5_N 200 MHz FPGA differential clock N (FPGA pin Y13).
6 27 MHz FPGA clock (FPGA pin AF13).
22.Program and reset buttons
Button S10 is used to force the FPGA to be reprogrammed and button S9 is used to force the System ACE to
reset.
23.64-Kb I2C EEPROM
The I2C EEPROM 24LC64 can be used to store non-volatile data such as an Ethernet MAC address. The
EEPROM is accessible through the I2C bus. See I2C bus addressing for details. The EEPROM write-protect
is disabled on the board. I2C bus pull-up resistors are provided on the board.
The I2C bus is extended to the FMC expansion connector so that the board can access additional I2C devices
and share the I2C controller in the FPGA.
Table 9 I2C FPGA pin assignments
I2C signal FPGA pin Description
IIC_SCLK AF23 I2C clock
IIC_SDAT AE25 I2C data