Xilinx SP701 User manual

SP701 Evaluaon Board
User Guide
UG1319 (v1.0) July 12, 2019

Revision History
The following table shows the revision history for this document.
Section Revision Summary
07/12/2019 Version 1.0
Initial release. N/A
Revision History
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Table of Contents
Revision History...............................................................................................................2
Chapter 1: Introduction.............................................................................................. 4
Overview.......................................................................................................................................4
Additional Resources.................................................................................................................. 5
Block Diagram..............................................................................................................................5
Board Features............................................................................................................................ 6
Board Specifications....................................................................................................................7
Chapter 2: Board Setup and Configuration......................................................9
Electrostatic Discharge Caution.................................................................................................9
Board Components..................................................................................................................... 9
Default Switch and Jumper Settings....................................................................................... 12
Spartan-7 Device Configuration.............................................................................................. 13
Chapter 3: Board Component Descriptions................................................... 15
Overview.....................................................................................................................................15
Component Descriptions......................................................................................................... 15
Appendix A: VITA 57.1 FMC Connector Pinouts............................................ 44
Appendix B: Xilinx Design Constraints............................................................. 45
Overview.....................................................................................................................................45
Appendix C: Regulatory and Compliance Information........................... 46
CE Information...........................................................................................................................46
Compliance Markings............................................................................................................... 47
Appendix D: Additional Resources and Legal Notices.............................48
Xilinx Resources.........................................................................................................................48
Documentation Navigator and Design Hubs.........................................................................48
References..................................................................................................................................49
Please Read: Important Legal Notices................................................................................... 50
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Chapter 1
Introduction
Overview
The SP701 evaluaon board is based on the XC7S100FGGA676 device, a member of the Xilinx®
7 series FPGA family. It is opmized for low cost, low power, and high I/O performance. It comes
with advanced high-performance FPGA logic based on real6-input look up table (LUT), 36 Kb
dual-port block RAM, support for DDR3L interface up to 1866 Mb/s, XADC with 12-bit
1 MSPA ADC with on-chip thermal and supply sensors, and powerful clock management les
(CMTs). The board is designed for high-performance and lower power with a 28 nm, 1V core
voltage process. For lower power, it has a 0.9V core voltage opon.
Table 1: XC7S100 Resources
Spartan®-7 FPGA
Resources Component Features
Logic Resources Part Number XCS7100
Logic Cells 102,400
Slices 16,000
CLB Flip-flops 128,000
Memory Resources Max. Distributed RAM (Kb) 1,100
Block RAM/FIFO w/EEC (36 Kb each) 120
Total Block RAM (Kb) 4,320
Clock Resources Clock Mgmt. Tiles (1 MMCM + 1 PLL) 8
I/O Resources Max. Single-Ended I/O Pins 400
Max. Differential I/O Pins 192
Embedded Hard IP
Resources
DSP Slices 160
Analog Mixed Signal (AMS)/XADC 1
Configuration AES/HMAC Blocks 1
Speed Grades Commercial Temp (C) -1, -2
Industrial Temp (I) -1, -2, -1L
Expanded Temp (Q) -1
Package Body Area (mm) Ball Pitch (mm) Available User I/O:
3.3V SelectIO™
technology HR I/O
FGGA676 27 x 27 1.0 400
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The following table lists the models for this board. See the SP701 evaluaon board product page
for details.
Table 2: Models of SP701 Boards
Kit Description
EK-S7-SP701-G Xilinx Spartan-7 FPGA SP701 Evaluation Kit
EK-S7-SP701-G-J Xilinx Spartan-7 FPGA SP701 Evaluation Kit, Japan Specific
Additional Resources
See Appendix D: Addional Resources and Legal Noces for references to documents, les, and
resources relevant to the SP701 evaluaon board.
Block Diagram
The following gure shows the various components of the SP701 Evaluaon Board.
Figure 1: SP701 Evaluation Board Block Diagram
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Board Features
The SP701 evaluaon board features are listed here. Detailed informaon for each feature is
provided in Chapter 3: Board Component Descripons.
• XC7S100-2FGGA676 package
• Form factor: 6.00 in (152.4 mm) square, 0.08844 in (88.44 mils) thick
•Conguraon:
○Quad SPI (QSPI) 1 Gb
○Direct QSPI ash program header
○USB-to-JTAG bridge
• DDR3L SDRAM memory:
○256Mx16 4 Gb DDR3-1866
• 32 Kb I2C EEPROM for hardware ID storage accessible by FPGA and System Controller
• Clocks:
○I2C programmable SYSCLK oscillator 33.33 MHz
• VITA 57.1 FMC-LPC connector:
○34 dierenal pairs or 68 single-ended LA[00-33] bus
• 2x 10/100/1000 Tri-Speed Ethernet PHY
• Mobile industry processor interface (MIPI) features:
○MIPI-CSI Camera Serial Interface (for PCAM 5C from Digilent)
○MIPI-DSI Display Serial Interface
• HDMI output (1.4 specicaon support)
• USB-UART interface:
○FT4232H JTAG/3xUART
• System Controller (MSP430)
• I2C Bus
• 6x Pmod rt-angle receptacle (Digilent Pmod IF 1.2.0 specicaon support)
• General purpose I/O (GPIO):
○8x LED (GPIO_LED[0:7]) (acve-High)
○5x pushbuon switch, geographical, GPIO_SW_[N,E,S,W,C] (acve-High)
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○1x pushbuon switch, CPU_RESET (acve-High)
○2x 8-pole DIP switch, GPIO_DIP_SW_B[0:15] (acve-High)
•Operaonal Switches:
○Power On-O slide switch
○PROG_B pushbuon switch (acve-Low)
○4-pole conguraon mode DIP switch M[0:2]_0_SW, INIT_B_0 (acve-Low)
•Operaonal Status LEDs:
○Done
○Power On
○PG (Power Good)
• Power System:
○Vccint 0.90V or 1.00V (I2C selectable)
○I2C telemetry on 12V input and Vccint
Board Specifications
Dimensions
• Height: 6.00 in (152.4 mm)
• Width: 6.00 in (152.4 mm)
• Thickness: 0.08844 in (88.44 mils)
Note: A 3D model of this board is not available.
See the SP701 board website documentaon tab (Board Files check box) for the XDC lisng and
board schemacs (0381874).
Environmental
• Temperature
○Operang: 0°C to +45°C
○Storage: –25°C to +60°C
• Humidity
○10% to 90% non-condensing
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Operating Voltage
• +12VDC
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Chapter 2
Board Setup and Configuration
Electrostatic Discharge Caution
CAUTION! ESD can damage electronic components when they are improperly handled, and can result in total or
intermient failures. Always follow ESD-prevenon procedures when removing and replacing components.
To prevent ESD damage:
• Use an ESD wrist or ankle strap and ensure that it makes skin contact. Connect the equipment
end of the strap to an unpainted metal surface on the chassis.
• Avoid touching the adapter against your clothing. The wrist strap protects components from
ESD on the body only.
• Handle the adapter by its bracket or edges only. Avoid touching the printed circuit board or
the connectors.
• Put the adapter down only on an anstac surface such as the bag supplied in your kit.
• If you are returning the adapter to Xilinx® Product Support, place it back in its anstac bag
immediately.
Board Components
The following gure shows the SP701 board component locaons. Each numbered component is
keyed to the table in Board Component Locaon.
IMPORTANT! The following gure is for visual reference only and might not reect the current revision of the
board. There could be mulple revisions of this board. The specic details concerning the dierences between
revisions are not captured in this document. This document is not intended to be a reference design guide and the
informaon herein should not be used as such. Always refer to the schemac, layout, and XDC les of the specic
SP701 version of interest for such details.
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Figure 2: SP701 Evaluation Board Components
5
00
00 Round callout references a component
on the front side of the board
Square callout references a component
on the back side of the board
16
7
14
17
27
18
21
34
26
31
15
4
30 8 9
6
25
10 11
29
24
23
35
32
33
13
19
220
3
12
1
22
28
X22622-070119
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Board Component Location
The following table idenes the components, references the respecve schemac (0381874)
page numbers, and links to a detailed funconal descripon of the components and board
features in Chapter 3: Board Component Descripons.
Table 3: Board Component Locations
Callout Feature [#] = Bottom Notes
Schematic
Page
Number
1Spartan-7 XC7S100 FPGA (U1) XC7S100-2FGGA676C
2 1Gb QSPI Flash 4-bit [U3] Micron MT25QL01GBBB8ESF-0SIT 4
3 Direct QSPI Flash Program Header (J37) 2X5 1.27 mm
pitch male header
Samtec FTSH-105-01-F-DV 3
4DDR3L Component Memory (U12) Micron MT41K256M16TW 7
5 IIC EEPROM [U27] ST Microelectronics M24C32-WDW6 8
6 I2C Programmable Clock, LVDS [U45] Silicon Labs SI570BAB000875DG
(default 33.3333 MHz)
8
7FMC LPC Connector J21 Samtec ASP-134603-01 15-16
810/100/1000 Mb/s Tri-speed Ethernet PHY (RGMII)
with RJ45, SGMII mode only (U14), (J9)
TI DP83867IRPAP with Wurth
7499111221A RJ45 (with magnetics)
9
910/100/1000 Mb/s Tri-speed Ethernet PHY (RGMII)
with RJ45, SGMII mode only (U16), (J11)
TI DP83867IRPAP with Wurth
7499111221A RJ45 (with magnetics)
10
10 MIPI-CSI Camera Serial Interface (J8) TE Connectivity 1-1734248-5 8
11 MIPI-DSI Display Serial Interface (J20) Hirose FH34SJ-34S-0.5SH 11
12 HDMI Video Output (U18), (J13) Analog Devices ADV7511KSTZ, Molex
47151-1001
12,13
13 USB UART Interface, USB bridge (U6) with micro-AB
USB connector (J5), and 2x7 2 mm keyed program
cable connector (J3)
FTDI FT4232HQ_QFN64, Hirose ZX62D-
AB-5P8(30), Molex 87832-1420
3, 5
14 System Controller MSP430 (U25) TI MSP430F5342IRGZ 19
15 System Controller MSP430 4-pole GPIO DIP switch
(SW2)
Wurth 416131160804 19
16 System Controller MSP430 reset pushbutton (SW3,
active-Low)
Panasonic EVQ-11L07K 19
17 I2C Bus Switch (U23)
I2C_MSP430 Bus Port Expander (U24)
TI TCA9548A
TI TCA6416A
19
18 PMOD Interface 6x 2x6 Rt-Angle receptacles (J14-J19) Sullins PPPC062LJBN-RC 17
19 User 8x LEDs, Green, active-High (D6-D13) Lumex SML-LX0603GW-TR 21
20 User 6x pushbutton, active-High (SW4-SW9) E-Switch TL3301EF100QG 21
21 User 2x 8-pole DIP switch, 1.27 mm pitch, active-High
(SW10, SW12)
Wurth 416131160808 21
22 FPGA Program pushbutton, (SW1), active-Low Omron B3U-1000P 3
23 Power Input Connector, 2x6 (J30) Molex-39-30-1060 23
24 Power On/Off Slide Switch (SW11) C&K 1101M2S3AQE2 23
25 SP701 Board Power System, MPS (top and bottom) Monolithic Power Systems (MPS) 24-26
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Table 3: Board Component Locations (cont'd)
Callout Feature [#] = Bottom Notes
Schematic
Page
Number
26 Configuration options, FPGA U1 configuration mode
4-pole DIP switch, (SW13)
Wurth 416131160804 3
27 XADC/SYSMON 2x10 shrouded/keyed
Header (J24)
Samtec TST-110-01-G-D 22
28 Encryption Key Battery Backup Circuit
Battery retainer [B1]
Keystone 2998 3
29 System Controller MSP430 2x7 0.1"
JTAG Header (J22)
Tyco 5103308-2 19
30 Ethernet 1x4 0.1" JTAG header (J10) Sullins PBC36DAAN 9
Default Switch and Jumper Settings
Jumpers
Default jumper sengs are listed in the following table. The table also references the respecve
schemac (0381874) page numbers.
Table 4: Default Jumper Settings
Callout Jumper Type Function Default
Schematic
Page
Number
31 J38 2-pin male header USB JTAG enable Jumper ON 5
32 J2 2-pin male header FPGA U1 CFGBVS_0 Jumper OFF 3
33 J6 2-pin male header FT4232 U6 SUSPEND Jumper OFF 5
34 J23 3-pin male header FPGA U1 XADC_VCC Select 2-3 22
34 J25 3-pin male header REF3012 U29 Vin Select 1-2 22
34 J26 3-pin male header FPGA U1 XADC_VREFP Select 1-2 22
34 J27 2-pin male header GND-to-J28/L12 Jumper ON 22
34 J28 2-pin male header J28/L12-to-XADC_GND Jumper OFF 22
35 J35 2-pin male header Power System Inhibit Jumper OFF 23
Switches
Default switch sengs are listed in the following table. The table also references the respecve
schemac (0381874) page numbers.
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Table 5: Default Switch Settings
Callout Switch Type Function Default
Schematic
Page
Number
15 SW2 5-pole DIP MSP430 U25 GPIO OFF, OFF, OFF, OFF,
OFF
19
21 SW10 8-pole FPGA U1 GPIO All OFF 21
21 SW12 8-pole FPGA U1 GPIO All OFF 21
26 SW13 4-pole DIP
FPGA U1 Configuration:
OFF, ON, OFF=101
OFF 3
Switch OFF = 1 = High; ON = 0 = Low
Mode = SW13[4:2] = Mode[2:0]
JTAG: SW13[4:2] = OFF, ON, OFF =
Mode[101]
MASTER SPI: SW13[4:2] = ON, ON, OFF =
Mode[001]
SW13[1] = INIT_B, OFF = OPEN, ON = 0 =
Low
Spartan-7 Device Configuration
The SP701 board supports two of the 7 series FPGA conguraon modes:
• Master SPI ash memory using the onboard QSPI ash memory
• JTAG
○J5 micro-AB USB-JTAG interface connector
- USB A-to-micro-B PC to SP701 cable connecon
○J3 2x7 2 mm keyed JTAG pod at cable header
-Plaorm cable USB II/Parallel cable IV type connecon
Each conguraon interface corresponds to one or more conguraon modes and bus widths as
listed in the following table.
The mode switches M2, M1, and M0 are on SW13 posions 4, 3, and 2, respecvely.
Table 6: SP701 Board FPGA Configuration Modes
Configuration Mode SW13 Switch Settings M[2:0]
Master SPI 001
JTAG (default) 101
See Table 5, callout 26 SW13 for more informaon on the switch posion.
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JTAG
Vivado® design tools, Xilinx® SDK, or third-party tools can establish a JTAG connecon to the
Spartan-7 device through the FTDI FT4232 USB-to-JTAG/USB UART device (U6) connected to
the micro-USB connector (J5).
To use the JTAG pod cable with the FTDI used for the UART only on J5, remove the jumper from
J38 when using the PC4/USB cable for JTAG.
To use the FPGA programming tools to detect the JTAG chain and program the FPGA, connect
the PC4/USB JTAG pod at cable to the 2x7 2 mm keyed shrouded connector J3.
Quad SPI
To boot from the QSPI nonvolale conguraon memory, use the following procedure:
1. Store a valid Spartan-7 boot image in the SPI ash device. See the 7 Series FPGAs
Conguraon User Guide (UG470) for informaon on programming the SPI.
2. Set the boot mode pins SW13 [4:2] MODE[2:0] as indicated in the table in Spartan-7 Device
Conguraon for Master SPI.
3. Power-cycle the SP701 board. SW13 is callout 30 in Board Components.
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Chapter 3
Board Component Descriptions
Overview
This chapter provides a detailed funconal descripon of the components and features of the
SP701 board. Board Component Locaon idenes the components, references the respecve
schemac page numbers, and links to the corresponding detailed funconal descripon in this
chapter. Component locaons are shown in Board Components.
Component Descriptions
Spartan-7 XC7S100 FPGA
[Figure 2, callout 1]
A Spartan-7 XC7S100-2FGGA676C FPGA is installed on the SP701 evaluaon board. The
Spartan-7 family is opmized for low cost, lowest power, and high I/O performance.
For further informaon on Spartan-7 FPGAs, see 7 Series FPGAs Data Sheet: Overview (DS180).
Encryption Key Battery Backup Circuit
The XC7S100 FPGA U1 implements bitstream encrypon key technology. The SP701 board
provides the encrypon key backup baery circuit shown in the following gure.
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Figure 3: Encryption Key Backup Circuit
The Keystone 2998 baery retainer B1 is soldered to the board with the posive output
connected to the FPGA U1 VCC_PSBATT pin D13. The B1 retainer accepts a 6.8 mm 1.5V
single-cell, coin type baery similar to Seiko part number SR621SW, silver oxide, 1.55V non-
rechargeable baery.
Bank Voltage Rails
The XC7S100 FPGA U1 bank voltages are listed in the following table.
Table 7: FPGA U1 Bank Voltage Rails
XC7S100 U1 Bank Power Net Name Voltage Connected To
0 VCCO_3V3 3.3V FPGA Configuration I/F
13 VCCO_1V8 1.8V MIPI_DSI, GPIO Switches, FT4232_C_UART, I2C3_DSI Bus
14 VCCO_3V3 3.3V FLASH_SPI, FT4232_B_UART
15 VCCO_3V3 3.3V HDMI Out, I2C4_HDMI Bus, GPIO LEDs, XADC I/F
16 VCCO_3V3 3.3V PMOD[1:6] I/F
33 VCCO_2V5 2.5V Ethernet PHY 1/2 I/F, MIPI_CSI, I2C2_CAM
34 VCCO_1V35 1.35V DDR3L I/F
35 VADJ 1.8V (nom),
3.3V, 2.5V
LPC FMC I/F, MPS430_GPIO
36 VADJ 1.8V (nom),
3.3V, 2.5V
LPC FMC I/F, MPS430_GPIO
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DDR3L Component Memory
[Figure 2, callout 4]
The 4 Gb, 16-bit wide DDR3L memory system is comprised of one 4 Gb x 16 SDRAM U12.
• Manufacturer: Micron
• Part Number: MT41K256M16TW-107:P
•Descripon:
○4 Gb (256 Mb x 16)
○1.35V 96-ball TFBGA
The Spartan-7 DDR interface performance is documented in the Spartan-7 FPGAs Data Sheet: DC
and AC Switching Characteriscs (DS189).
This memory system is connected to FPGA U1 bank 34. The DDR3L 0.675V VTT terminaon
voltage is supplied from MP20073DH regulator U13.
The following gure shows the DDR3L memory interface.
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Figure 4: DDR3L Memory Interface
DDR3L SDRAM
MT41K256M16TW-
107cc
Spartan-7
FPGA
A[14:0]
DQ[7:0]
DQ[15:8]
UDM
UDQS/UDQS#
LDM
LDQS/LDQS#
CK/CK#
CKE
BA[2:0]
CS#
ODT
RAS#, CAS#, WE#
RESET#
240E ZQ
VDD
VDDQ
VREFCA
VREFDQ
1.35V
1.35V
0.675V
0.675V
VDDO_34
VDDO_34
VDDO_34
1.35V
100E
U12U1
X22787-042619
For more details, see the Micron MT41K256M16TW-107 data sheet at the Micron Technology
website.
The detailed FPGA connecons for the feature described in this secon are documented in the
SP701 board XDC le, referenced in Appendix B: Xilinx Design Constraints. For more
informaon, see the Zynq-7000 SoC and 7 Series Devices Memory Interface Soluons (UG586).
Quad SPI Flash Memory
[Figure 2, callout 2]
A single Micron MT25QL01GBBBESF-0SIT 1 Gb serial NOR Flash memory (U3) holds the boot
images for the XC7S100 device. The Spartan-7 conguraon clock is 66 MHz resulng in a
typical conguraon me of 112 ms. This memory can also be used for user data.
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The following gure shows the conguraon ash memory interface.
Figure 5: Configuration Flash Memory Interface
SPI NOR FLASH
MT25QL01G
Spartan-7
FPGA
DQ0
DQ1
DQ2/W#
DQ3/HOLD#/RESET#
C
S#
FLASH_DQ[0]
FLASH_DQ[1]
FLASH_DQ[2]
FLASH_DQ[3]
FLASH_CLK
CS#
U1
X22788-042619
The detailed FPGA connecons for the feature described in this secon are documented in the
SP701 board XDC le, referenced in Appendix B: Xilinx Design Constraints.
SP701 JTAG Chain
[Figure 2, callout 13]
The SP701 JTAG chain has the following components:
• J5 USB micro-AB connector connected to U6 FT4232HQ USB-JTAG bridge
• U1 XCS700 FPGA
• J21 FMC LPC connector
• J3 2x7 2 mm shrouded, keyed JTAG pod at cable connector
The SP701 board JTAG chain is shown in the following gure.
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Figure 6: SP701 JTAG Chain
USB Conn
FT4232H
16
17
19
TCK>
TDI<
TMS>
PC4 14pin(2X7)
6
10
8
4
TCK>
TDI>
TDO<
TMS>
14
2
VREF
SRST
FPGA 7S100
>TCK
>TDI
<TDO
>TMS
18
TDO> FPGA_TDI_0
FPGA_TDO_0
PC4_JTAG_TDO
FPGA_TMS_0
FPGA_TCK_0
FMC_TDO
FMC_TDI_FPGA_TDO
JTAG Devices
FMC_TMS_BUF
FMC_TCK_BUF
SN74AVC1T45
J5
TXB0304
U6
J3
U1
U5
U44
>TCK
>TDI
<TDO
>TMS
D29
D30
D31
D33
<PRSNT_L
H2
J21
SW
U42 FMC LPC
X22789-042619
FMC LPC Connector JTAG Bypass
When an FPGA mezzanine card (FMC) is aached to J21, it is automacally added to the JTAG
chain through an electronically controlled single-pole single-throw (SPST) switch, U42. The SPST
switch is normally closed and transions to an open state when an FMC is aached. Switch U42
adds an aached FMC to the JTAG chain as determined by the FMC_PRSNT_M2C_L signal. The
aached FMC card must implement a TDI-to-TDO connecon using a device or bypass jumper
to ensure that the JTAG chain connects to the U1 XC7S100 FPGA.
The U5 TXBN0304 translator between the U6 FTDI JTAG/UART interface and the J3 JTAG pod
at cable connector J3 is normally not enabled (2-pin U5 enable header J38 jumper o) as the
USB JTAG funcon using USB connector J5 is typically in use. To use the J3 JTAG pod at cable
connector, remove the J5 USB cable and install a jumper on 2-pin header J38.
Chapter 3: Board Component Descriptions
UG1319 (v1.0) July 12, 2019 www.xilinx.com
SP701 Board User Guide 20
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