Xilinx Spartan-6 FPGA Series User manual

SP605 Getting Started
Guide [optional]
UG525 (v1.3) March 29, 2011 [optional]
Getting Started with the
Xilinx Spartan-6 FPGA
SP605 Evaluation Kit
UG525 (v1.3) March 29, 2011
XPM 0402789-01

Spartan-6/SP605 Getting Started Guide www.xilinx.com UG525 (v1.3) March 29, 2011
© Copyright 2009 – 2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included
herein are trademarks of Xilinx in the United States and other countries. [If applicable, insert relevant third-party sentence.] All other
trademarks are the property of their respective owners.
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Revision History
The following table shows the revision history for this document.
Date Version Revision
11/13/09 1.0 Initial Xilinx release.
12/02/09 1.0.1 Initial release to Web. Minor typographical edits.
06/07/10 1.1 Removed references to ISE software, version 11.1 and 11.3. Removed Figure 1-21 through
Figure 1-29, Figure 1-39 through Figure 1-49 and text associated with the figures.
10/15/10 1.2 Updated Figure 1-1, page 8. Revised “Installing the ISE Software,” page 23 describing
the use of the software voucher as part of the software registration process.
03/29/11 1.3 Updated Legal DISCLAIMER. Revised Figure 1-1, page 8. Updated website and
document links on page 31.

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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SP605 Evaluation Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Spartan-6 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Communications and Networking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Expansion Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Getting Started with the Base Reference Design Demonstration. . . . . . . . . . . . . . . 8
Setting Up the SP605 Board for the BRD Demonstration . . . . . . . . . . . . . . . . . . . . . . . . 9
Installing the Application GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Default Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Connecting the Cables and CompactFlash Memory Card . . . . . . . . . . . . . . . . . . . . . . . 11
Setting the CF Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Starting the Base Reference Design GUI Application . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Setting Ethernet Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Selecting an Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Changing the Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Getting Started with the Diagnostic Flash Demonstration. . . . . . . . . . . . . . . . . . . . 18
Setting the Default Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Installing CompactFlash Card, USB UART Cable, and 12V Power . . . . . . . . . . . . . . . 18
Setting the Mode Select and System ACE CF Select Switches . . . . . . . . . . . . . . . . . . . 19
Installing the USB UART Cable and Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Setting Up a Terminal Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Configure with BIST Diagnostic Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Running the Diagnostic Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Installing the ISE Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Redeeming the Software and IP License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Getting Additional Help and Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Warranty. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Appendix A: References
Support Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Spartan-6 FPGA Documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table of Contents

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Getting Started with the
Spartan-6 FPGA
SP605 Evaluation Kit
Introduction
The SP605 Spartan®-6 FPGA Evaluation Kit provides all the basic components for
developing broadcast, wireless communications, automotive, and other cost- and power-
sensitive applications that require transceiver capabilities in one package. Along with the
evaluation board, cables, and documentation, the SP605 evaluation kit provides an
integration of hardware, software, intellectual property (IP), and pre-verified reference
designs so development can begin right out of the box.
The SP605 evaluation kit provides a flexible environment for system design, including
applications that implement features such as high-speed serial transceivers, a
PCI Express® interface, DVI, and DDR3 component memory. The SP605 evaluation board
includes an industry-standard VITA-57 FPGA Mezzanine Connector (FMC) connector for
scaling and customizing to specific applications and markets. Xilinx development tools
helps streamline the creation of systems that adhere to complex requirements.
This guide describes how to set up the SP605 evaluation kit and run a diagnostic
demonstration that exercises basic board features. It introduces a more complex Base
Reference Design (BRD) that exercises key features of the Spartan-6 FPGA. This guide also
describes how to install the Xilinx® ISE® Design Suite: Logic Edition software, obtain
updates, and generate a license.
SP605 Evaluation Kit Contents
• SP605 Spartan-6 FPGA Evaluation Board
• ISE Design Suite: Logic Edition (device-locked) for the Spartan-6 XC6SLX45T FPGA
• Includes ChipScope™ Pro software and the ChipScope Pro serial I/O toolkit
• Includes PlanAhead™ design analysis tool
• Timing driven place and route, SmartGuide™, and SmartXplorer technology
• Documentation
•XTP089, Hardware Setup Guide
•UG525, SP605 Evaluation Kit Getting Started Guide (this document)
•UG526, SP605 Hardware User Guide
•UG527, SP605 Reference Design User Guide

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Key Features
• Schematics and PCB files
• Universal 12V power supply
• Cables
•TwoUSBcables
•Ethernet
• DVI-to-VGA adapter
• Reference Designs and Demonstrations
• SP605 Built-In Self Test Applications Design File
• SP605 BRD Design Files
• SP605 MultiBoot Design Files
• SP605 MIG Design File
• SP605 GTP IBERT Design Files
• SP605 PCIe® x1 Gen1 Design Files
• Reference designs, demonstrations, documentation, and applications delivered on
USB flash drive to get started quickly
Key Features
Spartan-6 FPGA
• XC6SLX45T-3C in FGG484 package
Configuration
• Onboard JTAG configuration circuitry
• 8 MB Quad SPI flash memory
• 32 MB Parallel (BPI) flash memory
• 2 GB CompactFlash (CF) memory card
Memory
• 128 MB DDR3 component memory
• 32 MB parallel (BPI) flash memory (also available for configuration)
•8KbIICEEPROM
• 8 MB Quad SPI flash memory (also available for configuration)
Communications and Networking
• 10 Mb/s, 100 Mb/s, 1,000 Mb/s Ethernet
• SFP optical transceiver connector
• GTP transceiver port (TX, RX) with four SMA connectors
•USBToUARTbridge
• PCI Express® x1 edge connector

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Key Features
Expansion Connectors
• FMC LPC connector (1 GTP transceiver, 68 single-ended or 34 differential user-
defined signals)
• User GPIO with two SMA connectors
• 4 user I/O (1 x 6 header)
Clocking
• 200 MHz oscillator (differential)
• 27 MHz socketed oscillator (single-ended)
• SMA connectors for external clock (differential)
• GTP transceiver reference clock port with two SMA connectors
Display
• Video - DVI/VGA interface
• 16 x 2 LCD character display
•4LEDs
Control
•4Pushbuttons
•4DIPswitches
Power
• 12V wall adapter or ATX power supply
• Voltage and current measurement capability of 2.5V, 1.5V, and 1.2V supplies

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Getting Started with the Base Reference Design Demonstration
Getting Started with the Base Reference Design Demonstration
Before installing the ISE software, some of the included demonstration designs can be run.
These designs are preinstalled on the CompactFlash memory card contained in the
SP605 evaluation kit and set up to be run immediately, offering an overview of the board’s
features. (Additional reference designs and application notes can be downloaded from the
Xilinx website.) The default Base Reference Design (BRD) demonstration exercises and/or
tests the Ethernet, DVI port, DDR3 memory, DSP, and the overall high-speed logic
capabilities of the Spartan-6 FPGA. Figure 1-2 shows a block diagram of the Base Reference
Design.
The SP605 BRD demonstration uses the SP605 board to filter images that are transferred
via Ethernet between the SP605 board and a PC. This filtered image is then retrieved by the
BRD interface GUI and displayed on a PC. A simple loopback test is used to demonstrate
the GTP transceivers. A simple memory test demonstrates the DDR3 connectivity using
MIG generator in the CORE Generator™ software. Images are sent from a PC via a series
of Ethernet packets. This image data is filtered and eventually sent back to the PC for
display.
The Ethernet Management section includes an embedded MAC, a GTP transceiver, a
PicoBlaze™ host controller, and a Packet Processing Engine. This section provides a way to
control various aspects of the demo, transfer images between the SP605 board and a PC,
and receive status from the demo. The MAC and packet processing logic can run at
1,000 Mb/s, 100 Mb/s, or 10 Mb/s, depending on the connection speed to the PC.
The Image Processing structure consists of a 5 x 5-pixel 2D FIR filter that is built using the
dedicated Spartan-6 FPGA DSP resources. A multiboot feature also allows this design to be
implemented using only logic—that is, without the dedicated DSP blocks.
X-Ref Target - Fi gure 1-1
Figure 1-1: SP605 Evaluation Board Features
Pushbuttons (4x)
LEDs (4x) 12VFan
Connector
GTP Transceiver
Differential Pairs
User CLK
Socket
PCIe Gen 1
SPI Prog/Sel
Header
32MB Parallel (BPI)
Linear Flash Memory
IIC EEPROM
(Reverse Side)
Suspend Header
Video Connector (DVI/VGA)
10/100/1000 Ethernet PHY
Ethernet Connector (RJ45)
DIP Switches (4x)
Ethernet Status LEDs
JTAG Download Port (USB)
Serial USB
I/O (4x)
High-Speed Differential
GPIO (SMA Connectors)
Power On/Off
Switch
Mode Switches
12VPower Connector
PROG and Reset
Pushbuttons
System ACE Controller
Mode Select Switches
FMC LPC
Connector DDR3 Memory
SFP Optical
Transceiver
GTP RefCLK Differential Pair
(SMA Connectors)
User CLK Differential Pair
(SMA Connectors)
System ACE™ Compact Flash
Memory Card
Status LEDs
UG525_01_030811
Spartan-6 FPGA
XC6SLX45T-3C FFG484
Power Monitor
Connector

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Getting Started with the Base Reference Design Demonstration
Setting Up the SP605 Board for the BRD Demonstration
Installing the Application GUI
The Base Reference Design includes an application GUI that must be installed before
running the demonstration. On the USB flash drive included with the kit, locate the install
image:
SP605_BRD_Reference Design →SP605_BRD_Application →
BaseRefDISetup2_0_5.msi
This application is used to display the graphical information for the Base Reference
Design. Double-click the MSI file to install the software.
Note: The Windows .NET Framework might need to be installed or updated. Go to
http://www.microsoft.com/NET/ and click Get the .NET Framework.
When running BaseRefDISetup2_0_5.msi, an Unknown Publisher Warning appears.
Click Run, then click Next in the Base Reference Design Interface Setup Wizard.
X-Ref Target - Figure 1-2
Figure 1-2: SP605 Base Reference Design Block Diagram
UG525_02_101710
DDR3
DVI
Output
Inverse
Gamma
FIR
Filters
Management
PicoBlaze
Gamma
Packet
Processing
Engine
1000 Mb/s
100 Mb/s
Ethernet
MAC
PHY
MIG Memory Interface
Image Processing
Link
Status
Ethernet Management
Loopback
Test
GTP
Transceiver
GMII
PC Ethernet
MDIO

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Getting Started with the Base Reference Design Demonstration
This also installs WinPcap, as shown in Figure 1-3 and Figure 1-4. WinPcap is used by the
BRD GUI application.
X-Ref Target - Figure 1-3
Figure 1-3: Base Reference Design Install Window
X-Ref Target - Figure 1-4
Figure 1-4: WinPcap Setup Window
UG525_03_101910
UG525_04_101910

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Getting Started with the Base Reference Design Demonstration
Default Jumper Settings
As shown in Figure 1-5, 2-pin headers J44 and J46 should have jumpers installed across
both pins; 3-pin headers J19 and J22 should have jumpers installed across pins 1–2.
Headers J9, J10, J13, J45, J47, J48, J49, J58, and J60 should have no jumpers installed.
Connecting the Cables and CompactFlash Memory Card
The Base Reference Design is one of the demonstrations on the CompactFlash memory
card.
Note: Turn off any wireless cards while running this demonstration.
Insert the CF card. Connect the Ethernet cable between the Ethernet RJ45 connectors on the
PC and the SP605 board. Connect the DVI port to a DVI-capable monitor, or to a VGA-
capable monitor through the DVI-to-VGA adaptor. Plug in the power adaptor to the local
AC power. Plug the 12V power jack into the board connector J18. Turn on the power by
moving slide switch SW2 to the ON position. See Figure 1-6.
X-Ref Target - Figure 1-5
Figure 1-5: Default Jumper Settings
UG525_05_101810
J22
J44
J19
J46

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Getting Started with the Base Reference Design Demonstration
Setting the CF Configuration Mode
The Base Reference Design is located in the CompactFlash memory card. To select the CF
configuration, set DIP switch (SW1) so that both M0 and M1 are in the OFF position, as
shown in Figure 1-7.
Now set the System ACE™ CF Image Select DIP switch (S1) to 1101 where switches 1, 2,
and 4 are set to the ON position and switch 3 is set to the OFF position, as shown in
Figure 1-7. Setting switch 4 to the ON position enables the System ACE CF controller.
Setting switches 1 and 2 to the ON position selects configuration slot 3, where the Base
Reference Design demonstration is located.
X-Ref Target - Figure 1-6
Figure 1-6: Connecting Cables and CF Card
UG525_06_101910
DVI to VGA
Adapter
CompactFlash Card and
System ACE CF Controller
12V
Power
J18
Power On
Switch
Ethernet
Cable
X-Ref Target - Figure 1-7
Figure 1-7: Setting the Mode Select and System ACE CF Select Switches
UG525_07_101910
S1 SW1

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Getting Started with the Base Reference Design Demonstration
Starting the Base Reference Design GUI Application
To start the application GUI, go to the Windows start menu and select
All Programs → XILINX → Base Reference Design → Base Reference Design Interface
The screen shown in Figure 1-8 is displayed.
.
X-Ref Target - Figure 1-8
Figure 1-8: Base Reference Design Interface
UG525_08_101910

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Getting Started with the Base Reference Design Demonstration
Load the Base Reference Design demonstration from the CompactFlash memory card. To
load from the CF card, reset the FPGA by pressing the System ACE CF reset button (SW9),
shown in Figure 1-9.
X-Ref Target - Figure 1-9
Figure 1-9: Reset System ACE CF and Load CF Card BRD Demonstration
UG525_09_101910
System ACE™ CF
Reset Button (SW9)

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Getting Started with the Base Reference Design Demonstration
Setting Ethernet Link
In the Base Reference Design GUI application, select a network from Setup →
Network Interface, as shown in Figure 1-10. The GUI will indicate Connected to FPGA and
the Ethernet Status LEDs will be active on the SP605 board.
X-Ref Target - Figure 1-10
Figure 1-10: Connecting the Ethernet Link
UG525_10_101910
Ethernet LEDs
Ethernet
Cable

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Getting Started with the Base Reference Design Demonstration
Selecting an Image
On the USB flash memory, navigate to the SP605_BRD_Reference_Design →
SP605_BRD_Images directory and select the fractal1.jpg image. Then click the
Show Display button.
The default filter effect is an Identity function (Figure 1-11). It takes the loaded image and
simply processes it without any filtering effect. The image is sent back over the Ethernet
link and displayed in the GUI. It is also sent over the DVI display port.
X-Ref Target - Figure 1-11
Figure 1-11: Selecting and Displaying an Image
UG525_11_101910

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Getting Started with the Base Reference Design Demonstration
Changing the Filter
The default filtering in Figure 1-11, page 16 shows the Identity effect. Now use the Effect
drop-down box to select Edge Detect. Figure 1-12 shows that the Image is filtered using the
transform effect. If a DVI or VGA monitor has been connected, this image will also be
displayed on the monitor. Other effects can be selected through interaction with the GUI.
Note that the 5 x 5 Filter coefficient table changes every time an effect is changed.
Another feature of this Base Reference Design is MultiBoot. See the DSP Mode radio
buttons in Figure 1-12. The two DSP Mode selections are Logic and DSP48A1. The default
is DSP48A1, which utilizes the digital signal processing (DSP) element in Spartan-6
FPGAs, the DSP48A1 slice. To demonstrate the performance these DSP48A1 slices provide,
notice the processing time for the DSP implementation is around 10.66 ms.
Selecting the Logic DSP mode reloads a new FPGA configuration that only uses FPGA
logic resources. When the FPGA is reconfigured, the Program and Done LEDs flash. The
Ethernet link also disconnects and then reconnects during reconfiguration. The Logic DSP
implementation processes the image at about 5x the DSP48A1 implementation, running at
about 53.3 ms.
X-Ref Target - Figure 1-12
Figure 1-12: Changing the Filter
UG525_12_102010

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Getting Started with the Diagnostic Flash Demonstration
Getting Started with the Diagnostic Flash Demonstration
In addition to the BRD demonstration, a board diagnostic built-in system test (BIST) can
also be run that provides an overview of the SP605 board features. The BIST exercises some
of the board features, including testing the UART, flashing the LEDs, reading the switches,
and testing the Flash memory, DDR3 component memory, IIC bus, Ethernet PHY, and DVI
interface.
Setting the Default Jumper Settings
Figure 1-13 highlights the default jumper settings, USB Mini-B JTAG connection,
CompactFlash memory card location, and 12V power connection.
As shown in Figure 1-13, 2-pin headers J44 and J46 should have jumpers installed across
both pins; 3-pin headers J19 and J22 should have jumpers installed across pins 1–2.
Headers J9, J10, J13, J45, J47, J48, J49, J58, and J60 should have no jumpers installed.
Installing CompactFlash Card, USB UART Cable, and 12V Power
1. Install the CompactFlash memory card.
2. Connect the Mini-B USB cable to the USB connector marked J23 (USB UART), and
connect the USB A end of the cable to the PC.
3. Plug in the power adapter to local AC power. Plug the 12V power cable into the board
connector on J18. Turn on the power by switching the SW1 to the ON position.
X-Ref Target - Figure 1-13
Figure 1-13: Default Jumper Settings, Cable Connections, and CompactFlash Memory Connection
UG525_13_030811
USB UART
Mini-B To J23
CompactFlash Card and
System ACE CF Controller
12V
Power
J18
Power On
Switch
J22
J44
J19
J46

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Getting Started with the Diagnostic Flash Demonstration
Setting the Mode Select and System ACE CF Select Switches
To run the diagnostic demonstration, set the FPGA Mode DIP switch (SW1) to the BPI
Configuration Mode, where both M0 and M1 are in the OFF position, as shown in
Figure 1-14.
Set the System ACE CompactFlash Image Select DIP switch (S1) to 0001, where 1, 2, and 3
are set to the OFF position and switch 4 is set to the ON position, as shown in Figure 1-14.
This setting addresses configuration 0 on the CompactFlash memory card.
Installing the USB UART Cable and Driver
Make sure the USB Mini-B cable is connected to J23 (USB UART). Install the USB UART
driver for the Silicon Labs CP2103GM USB-to-UART Bridge located on the USB drive
shipped with the SP605 evaluation kit.
Open the computer’s Device Manager dialog box by right-clicking the My Computer icon
and selecting Properties. Select the Hardware tab and click the Device Manager button.
Expand the Ports (COM and LPT) entry and see what port the CP210X USB to Bridge
Controller is connected to. The example in Figure 1-15 shows the CP210X USB to Bridge
Controller connected to COM5, but a customer computer might have assigned this to a
different COM Port. Right-click to view additional properties settings.
X-Ref Target - Figure 1-14
Figure 1-14: Setting the Mode Select and System ACE Select Switches
UG525_14_102610
S1 SW1

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Getting Started with the Diagnostic Flash Demonstration
Setting Up a Terminal Program
On the PC, open a serial terminal program. This example uses the HyperTerminal serial
communications tool included with Windows XP, but any other terminal emulation tool
can be used instead.
To open HyperTerminal, select Start → Programs → Accessories → Communications
→HyperTerminal. In the Connection Description window, type SP605 Board
Diagnostic in the Name box, then click OK. See Figure 1-16.
In the Connect To window, select the COM port that the USB cable is connected to — for
example, COM5 — and click OK. See Figure 1-17.
X-Ref Target - Figure 1-15
Figure 1-15: Setting System Properties to Access USB UART
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X-Ref Target - Figure 1-16
Figure 1-16: Opening a Terminal Program
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