Xilinx VCU118 User manual

VCU118 Evaluation Board
User Guide
UG1224 (v1.0) December 15, 2016

VCU118 Board User Guide 2
UG1224 (v1.0) December 15, 2016 www.xilinx.com
Revision History
The following table shows the revision history for this document.
Date Version Revision
12/15/2016 1.0 Initial Xilinx release.
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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: Introduction
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Board Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Operating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Chapter 2: Board Setup and Configuration
Board Component Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Default Switch and Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Installing the VCU118 Board in a PC Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 3: Board Component Descriptions
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Component Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Virtex UltraScale+ XCVU9P-L2FLGA2104 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
DDR4 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
RLD3 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Linear BPI Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Micro-SD Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Digilent USB JTAG Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
FMC Connector JTAG Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Programmable User Clock 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Programmable User Clock 2 (QSFP Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
250 MHz Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
User SMA Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Jitter Attenuated Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
GTY Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
PCI Express Endpoint Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
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28 Gb/s QSFP+ Module Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
FireFly Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
10/100/1000 Mb/s Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Ethernet PHY Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Dual USB-to-UART Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
I2C Bus, Topology, and Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Status and User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
User GPIO LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
User Pushbuttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
CPU Reset Pushbutton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
GPIO DIP Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
User Pmod GPIO Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
FPGA Mezzanine Card Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
VCU118 Board Power System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
FMC VADJ_1V8 Power Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Monitoring Voltage and Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Cooling Fan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Configuration Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Appendix A: VITA 57.1 and 57.4 FMC Connector Pinouts
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Appendix B: Master Constraints File Listing
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
VCU118 Board Constraints File Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Appendix C: Regulatory and Compliance Information
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Declaration of Conformity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Appendix D: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
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Chapter 1
Introduction
Overview
The VCU118 evaluation board for the Xilinx®Virtex®UltraScale+™FPGA provides a
hardware environment for developing and evaluating designs targeting the UltraScale+
XCVU9P-L2FLGA2104 device. The VCU118 evaluation board provides features common to
many evaluation systems, including:
• DDR4 and RLD3 component memory
• Dual small form-factor pluggable (QSFP+) connector
• Sixteen-lane PCI Express®interface
• Ethernet PHY
• General purpose I/O
•TwoUARTinterfaces
• FireFly™Optical x4 28 G connector
Other features can be supported using modules compatible with the VITA-57.1 FPGA
mezzanine card (FMC) and VITA-57.4 FPGA mezzanine card plus high serial pin
(FMC+ HSPC) connectors on the VCU118 board.
Additional Resources
See Appendix D, Additional Resources and Legal Notices for references to documents, files,
and resources relevant to the VCU118 evaluation board.
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Chapter 1: Introduction
Block Diagram
A block diagram of the VCU118 evaluation board is shown in Figure 1-1.
X-Ref Target - Figure 1-1
Figure 1-1: VCU118 Evaluation Board Block Diagram
X18010-100416
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Chapter 1: Introduction
Board Features
The VCU118 evaluation board features are listed here. Detailed information for each feature
is provided in Component Descriptions in Chapter 3.
• Virtex UltraScale+ XCVU9P-L2FLGA2104 device
•Zynq
®-7000 AP SoC XC7Z010 based system controller
• Two 2.5 GB DDR4 80-bit component memory interfaces (five [256 Mb x 16] devices
each)
• 288 MB 72-bit RLD3 memory interface comprised of two 1.125 Gb 36-bit devices
• 1 Gb (128 MB) linear x16 BPI flash memory
• USB JTAG interface using a Digilent module with separate micro-B USB connector
• Clock sources:
°Si5335A quad clock generator
°Three Si570 I2C programmable LVDS clock generators
°One SG5032 fixed 250 MHz LVDS clock generator
°Si5328B clock multiplier and jitter attenuator for QSFP
°Subminiature version A (SMA) connectors (differential)
• 52 GTY transceivers (13 Quads)
°FMC+ HSPC connector (twenty-four GTY transceivers)
°2x28 Gb/s QSFP+ connectors (eight GTY transceivers)
°Samtec Firefly connector (four GTY transceiver)
°PCIe 16-lane edge connector (sixteen GTY transceivers)
• PCI Express endpoint connectivity
°Gen1 16-lane (x16)
°Gen2 16-lane (x16)
°Gen3 8-lane (x8)
• Ethernet PHY SGMII interface with RJ-45 connector
• Dual USB-to-UART bridge with micro-B USB connector
•I
2C bus
•StatusLEDs
• User I/O (4-pole DIP switch, 6 each push-button switches, 8 x LED)
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Chapter 1: Introduction
• Two Pmod 2x6 connectors (one male pin header, one right-angle receptacle)
• VITA 57.4 FMC+ HSPC connector J22
•VITA57.1FMCHPC1connectorJ2
• Power management with PMBus voltage monitoring through Maxim power controllers
and GUI
• 10-bit 0.2 MSPS SYSMON analog-to-digital front end
• Configuration options:
°BPI linear flash memory
°Digilent USB configuration module
°Platform cable USB II interface 2x7 2 mm connector
Board Specifications
Dimensions
Height: 6.927 inch (17.59 cm)
Thickness (±5%): 0.061 inch (0.1549 cm)
Length: 9.5 inch (24.13 cm)
Note: A 3D model of this board is not available.
IMPORTANT: The VCU118 board height exceeds the standard 4.376 inch (11.15 cm) height of a PCI
Express®card.
Environmental
Temperature
Operating: 0°C to +45°C
Storage: -25°C to +60°C
Humidity
10% to 90% non-condensing
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Chapter 1: Introduction
Operating Voltage
+12 VDC
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Chapter 2
Board Setup and Configuration
Board Component Location
Figure 2-1 shows the VCU118 board component locations. Each numbered component
shown in the figure is keyed to Table 2-1. Table 2-1 identifies the components, references
the respective schematic page numbers, and links to a detailed functional description of the
components and board features in Chapter 3.
IMPORTANT: Figure 2-1 is for visual reference only and might not reflect the current revision of the
board.
CAUTION! The VCU118 board can be damaged by electrostatic discharge (ESD). Follow standard ESD
prevention measures when handling the board.
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Chapter 2: Board Setup and Configuration
X-Ref Target - Figure 2-1
Figure 2-1: VCU118 Evaluation Board Components
Round callout references a component
on the front side of the board
Square callout references a component
on the backside side of the board
9
7
20
19
36
28
38
8
21
14
18
26
17
4
C1
40
5
33 34
22 15 27
23
24
30
39
29
37
25
11
31
31
4
C2
16 13 12 35
6 10 11
2
1
3
00 00
41
X18022-102616
Table 2-1: VCU118 Board Component Descriptions
Callout Feature Notes Schematic
Page Number
1Virtex UltraScale+ XCVU9P-L2FLGA2104
Device, (with fan-sink on soldered FPGA)
XCVU9P-L2FLGA2104E
Cofan 30-5530-03
2GTY transceivers, Right Side Quads (six
quads) Embedded within FPGA U1 14-15
3GTY transceivers, Left Side Quads (seven
quads) Embedded within FPGA U1 16-17
4
DDR4 Component Memory, two 80-bit DDR4
component memory I/F, C1 (U60-U64)
(bottom) and C2 (U135-U139) (top)
C1: 5 x Micron MT40A256M16GE-075E,
C2: 5 x Micron MT40A256M16GE-075E
25-27,
28-30
5RLD3 Component Memory, RLD3 72-bit
component memory I/F C3 (U141-U142) Micron MT44K32M36RB-083F 31-32
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Chapter 2: Board Setup and Configuration
6Linear BPI Flash Memory, BPI 16-bit
configuration memory 1 Gb (U133) Micron MT28GU01GAAA1EGC-0SIT 54
7Micro-SD Card Interface, (bottom)
Micro-SD card interface connector (J83) Molex 5025700893 49
8Digilent USB JTAG Module, USB JTAG micro-B
connector (J106) Hirose ZX62D-AB-5P8 24
9Digilent USB JTAG Module (U115), with
micro-B connector Digilent JTAG-SMT2-NC 24
10
Clock Generation, multi-output clock
generator, SYSCLK and other clocks, 1.8V
LVDS (U122)
SI5335A-B02436-GM, 4 outputs:
300 MHz, 125 MHz, 90 MHz, 33.33 MHz 44
11
System Clock, programmable user clock
Si570_0, I2C programmable user clock, 3.3V
LVDS (U18) (bottom) with 1-to-2 LVDS
MUX/buffer (U157) (top)
Silicon Labs SI570BAB0000544DG
(default 156.250 MHz) with Si53340
MUX/buffer
44
12
Programmable User Clock 1, programmable
user clock Si570_1, I2C programmable user
clock, 3.3V LVDS (U32) with 1-to-2 LVDS
MUX/buffer (U104)
Silicon Labs SI570BAB0000544DG
(default 156.250 MHz) with Si53340
MUX/buffer
45
13
Programmable User Clock 2 (QSFP Clock),
programmable user clock Si570_2, I2C
programmable user clock, 3.3V LVDS (U38)
Silicon Labs SI570BAB0000544DG
(default 156.250 MHz) 45
14
250 MHz Clock, fixed SG5032 250 MHz user
clock, 3.3V LVDS (U14) (bottom) with 1-to-2
LVDS MUX/buffer (U21) (bottom)
EpsonSG5032VAN_250.000000M-KEGA3
with ICS85411AMLF 1-to-2 buffer 45
15 User SMA Clock pair J34(P)/J35(N) Rosenberger 32K10K-400L5 45
16 Jitter Attenuated Clock, jitter attenuated
QSFP clock (U57) Silicon Labs SI5328B 51
17 PCI Express Endpoint Connectivity, PCI
Express connector (P1) 8-lane card edge connector 43
18 Two 28 Gb/s QSFP+ Module Connectors,
QSFP1 (U145), QSFP2 (U123) Amphenol FS1-Z38-20Z6-10 50
19 10/100/1000 Mb/s Tri-Speed Ethernet PHY
with RJ45, SGMII mode only, (U7, J10)
TI DP83867ISRGZ with Wurth
7499111221A RJ45 (with magnetics) 52
20 Ethernet PHY Status LEDs, LEDs are
integrated into J10 bezel
Wurth 7499111221A RJ45 integrated
status LEDs 52
21 Dual USB-to-UART Bridge, bridge device
(U34) with mini-B connector (J4)
Silicon Labs CP2105-F01-GM bridge,
Hirose ZX62D-AB-5P8 connector 53
22 I2C Bus, Topology, and Switches, I2C bus,
I2C bus MUX (U28) (bottom) TI TCA9548APWR 58
23 I2C Bus, Topology, and Switches, I2C bus,
I2C bus MUX (U80) TI TCA9548APWR 58
Table 2-1: VCU118 Board Component Descriptions (Cont’d)
Callout Feature Notes Schematic
Page Number
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Chapter 2: Board Setup and Configuration
24 User GPIO LEDs (DS6-DS10, DS12, DS13,
DS18)
GPIO LEDs, green 0603 Lumex
SML-LX0603GW-TR 55
25
User Pushbuttons, (SW10, SW17, SW9, SW6,
SW7), CPU reset pushbutton (SW5) all
active-High
E-Switch TL3301EF100QG (north, south,
east, west, center pattern) 55
26 GPIO DIP Switch, GPIO DIP switch (SW12)
(bottom) 4-pole CTS 218-4LPSTRF 55
27
Program_B Pushbutton Switch, program_B
pushbutton switch, FPGA PROG pushbutton
(SW4)
E-Switch TL3301EF100QG 55
28 VCU118 XC7Z010 system controller, mode
switch DIP, switch (SW15) 4-pole CTS 218-4LPSTRF 49
29
User Pmod GPIO Headers, (J52 right-angle
receptacle, J53 male pin header) (top) with
level shifters (U41,U42) (bottom)
J52SullinsPPPC062LJBN-RC,
J53SullinsPBC36DAAN,
NXP NVT2008PW
57
30 Switches, power on/off slide switch SW1 C&K 1201M2S3AQE2 59
31 VCU118 Board Power System, power
management system (top and bottom)
Maxim MAX20751E and MAX15301
dig-ital P.O.L. controllers 60-75
32 Monitoring Voltage and Current, power
management voltage and current sensing
TI Current and Power Monitor
INA226AIDGS 60-67
33 GTY Transceivers, FMCP HSPC connector J22 Samtec ASP_184329_01 34-38
34 FMC HPC1 Connector J2 Samtec ASP_134486_01 39-42
35 Configuration Options, FPGA U1
configuration mode DIP switch, (SW16) 4-pole CTS 218-4LPSTRF 3
36 System Controller, VCU118 Zynq-7000 AP
SoC XC7Z010CLG225 (U111) XC7Z010CLG225 46-49
37
Monitoring Voltage and Current, VCU118
board power system 2x8 shrouded PMBus
connector (J39)
ASSMAN AWHW16G-0202 59
38 Digilent USB JTAG Module, USB JTAG
module, shrouded JTAG cable connector (J3) 2x7 2 mm Molex 87832-1420 24
39 Power On/Off Slide Switch SW1, power input
connector (J15) 2x6 Molex-39-30-1060 59
41 FireFly Connector, signal and power pair (J6) Samtec Signal: UEC5-019-2-H-D-RA-1,
Samtec Power: UCC8-10-1-H-S-1-A 50
40 PCI Express Endpoint Connectivity, lane
width select header, (J7)
2x4 0.1 inch male header Sullins
PBC36DAAN 43
Notes:
1. The VCU118 board schematics are available for download. See the VCU118 Evaluation Kit.
2. The VCU118 board jumper header locations are shown in Figure 2-2.
Table 2-1: VCU118 Board Component Descriptions (Cont’d)
Callout Feature Notes Schematic
Page Number
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Chapter 2: Board Setup and Configuration
Default Switch and Jumper Settings
Switches
Default switch settings are listed in Table 2-2. Switch locations are shown in Figure 2-1.
Table 2-2 also references the respective schematic page numbers.
Table 2-2: Default Switch Settings
Switch Function Default Comments Figure 2-1
Callout
Schematic
Page
SW1 SPST slide switch OFF Board shipped with power switch off 30 59
SW12 4-pole GPIO 0000 Positions 1-4, GPIO 26 55
SW15 4-pole configuration 0000 Positions 1-4, Zynq-7000 AP SoC System
Controller U111 28 49
SW16 4-pole configuration 0101 Position 1, System Controller Enable
Positions 2-4, FPGA U1 mode M[2:0] 35 3
Notes:
1. DIP switches are active-High (connected net is pulled High when DIP switch is closed).
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Chapter 2: Board Setup and Configuration
Jumpers
Figure 2-2 shows the VCU118 board jumper header locations. Each numbered component
shown in the figure is keyed to Table 2-3, which identifies the default jumper settings and
references the respective schematic page numbers.
X-Ref Target - Figure 2-2
Figure 2-2: VCU118 Board Header Jumper Locations
8
6
5
7
3
14
2
X18026-100416
Table 2-3: Default Jumper Settings
Jumper Function Default Comments Figure 2-2
Callout
Schematic
Page
J5 Power on reset (POR) override 2-3 U1 POR_OVERRIDE pin AG12 to GND 1 3
J7 PCIe lane size select 7-8 16-lane configuration 2 43
J8 SYSCLK source select Off SI5335A 300 MHz default 3 44
J9 USER/MGT_SI570 source select Off SI570 U32 156.250 MHz 4 45
J12 Maxim regulator inhibit Off Used when programming PWR. SYS. 5 59
J14 U30 VADJ_1V8 enable Off Input to U25 AND, VADJ_1V8
enabled 663
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Chapter 2: Board Setup and Configuration
Installing the VCU118 Board in a PC Chassis
Installation of the VCU118 board inside a computer chassis is required when developing or
testing PCI Express® functionality.
When the VCU118 board is used inside a computer chassis (that is, plugged in to the PCIe®
slot), power is provided from the ATX power supply 4-pin peripheral connector through the
ATX adapter cable (Figure 2-3) to J15 on the VCU118 board. The Xilinx part number for this
cable is 2600304. See [Ref 29] for ordering information.
To install the VCU118 board in a PC chassis:
1. On the VCU118 board, remove the six screws retaining the six rubber feet with their
standoffs, and the PCIe bracket. Reinstall the PCIe bracket using two of the previously
removed screws.
2. Power down the host computer and remove the power cord from the PC.
3. Open the PC chassis following the instructions provided with the PC.
4. Select a vacant PCIe expansion slot and remove the expansion cover (at the back of the
chassis) by removing the screws on the top and bottom of the cover.
J29 BPI Flash A25 source select 1-2 A25 connected to FPGA U1 pin BE17 7 54
J110 Zynq-7000 AP SoC System
Controller U111 QSPI_IO3 Off QSPI_IO3 P/U w/20K (On = P/D to GND) 847
Table 2-3: Default Jumper Settings (Cont’d)
Jumper Function Default Comments Figure 2-2
Callout
Schematic
Page
X-Ref Target - Figure 2-3
Figure 2-3: ATX Power Supply Adapter Cable
X17987-100416
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Chapter 2: Board Setup and Configuration
5. The VCU118 board requires three adjacent PCIe slots. The VCU118 board has a large
cooling fan that exceeds the PCIe top side component height restriction and has several
spring loaded screws on the back side of the board. Ensure the slots closest to the front
and back of the board are free of obstructions.
6. Plug the VCU118 board into the center of the three open slots.
7. Install the top mounting bracket screw into the PC expansion cover retainer bracket to
secure the VCU118 board in its slot.
8. Connect the ATX power supply to the VCU118 board using the ATX power supply
adapter cable as shown in Figure 2-3.
a. Plug the 6-pin 2 x 3 Molex connector on the adapter cable into J15 on the VCU118
board.
b. Plug the 4-pin 1 x 4 peripheral power connector from the ATX power supply into the
4-pin adapter cable connector.
CAUTION! Do NOT plug a PC ATX power supply 6-pin connector into J15 on the VCU118 evaluation
board. The ATX 6-pin connector has a different pin out than J15. Connecting an ATX 6-pin connector
into J15 damages the VCU118 evaluation board and voids the board warranty.
9. Slide the VCU118 board power switch SW1 to the ON position. The PC can now be
powered on.
FPGA Configuration
The VCU118 board supports two of the seven UltraScale FPGA configuration modes:
• Master BPI using the onboard linear BPI flash memory
•JTAGusing:
°USB JTAG configuration port (Digilent module U115)
°Platform cable USB 2.0, 2 mm, keyed flat cable header (J3)
Each configuration interface corresponds to one or more configuration modes and bus
widths, as listed in Table 2-4. The mode switches M2, M1, and M0 are on SW16 positions 2,
3, and 4, respectively. The FPGA default mode setting M[2:0] = 101 selects the JTAG
configuration mode.
Table 2-4: Configuration Modes
Configuration Mode SW16 DIP Switch
Settings M[2:0] Bus Width CCLK Direction
Master BPI 010 x8,x16 Output
JTAG 101 x1 Not Applicable
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Chapter 2: Board Setup and Configuration
For complete details on configuring the FPGA, see UltraScale Architecture Configuration
User Guide (UG570) [Ref 2].
Figure 2-4 shows the configuration mode DIP switch SW16 default switch positions.
X-Ref Target - Figure 2-4
Figure 2-4: SW16 Default Settings
;
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Chapter 3
Board Component Descriptions
Overview
This chapter provides a detailed functional description of the board’s components and
features. Table 2-1, page 11 identifies the components, references the respective schematic
page numbers, and links to the corresponding detailed functional description in this
chapter. Component locations are shown in Figure 2-1, page 11.
Component Descriptions
Virtex UltraScale+ XCVU9P-L2FLGA2104 Device
[Figure 2-1, callout 1]
The VCU118 board is populated with the Virtex UltraScale+ XCVU9P-L2FLGA2104 device.
For more information on Virtex UltraScale+ FPGAs, see Virtex UltraScale+ FPGAs Data
Sheet: DC and AC Switching Characteristics (DS923) [Ref 1].
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Chapter 3: Board Component Descriptions
Encryption Key Battery Backup Circuit
The XCVU9P device U1 implements bitstream encryption key technology. The VCU118
board provides the encryption key backup battery circuit shown in Figure 3-1. The Seiko
TS518FE rechargeable 1.5V lithium button-type battery B1 is soldered to the board with the
positive output connected to the XCVU9P device U1 VBATT pin AT11. The battery supply
current IBATT specification is 150 nA maximum when the board power is off. B1 is charged
from the SYS_1V8 1.8V rail through a series diode with a typical forward voltage drop of
0.38V and 4.7 KΩcurrent limit resistor. The nominal charging voltage is 1.42V.
X-Ref Target - Figure 3-1
Figure 3-1: Encryption Key Backup Circuit
To VBATT pin
U1.AT11
X18008-100416
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