XMOS xCORE-200 Multi-channel Audio board User manual

xCORE-200 Clock Frequency Control
IN THIS DOCUMENT
·PLL and Clock Divider Overview
·Constraints
·PLL Settings
·Configuring the xCORE-200 Device
·Frequency Control Registers
·Example PLL Configurations
·Example System Clock Divider Configurations
·Configuring the Clock System Through the XN File
·Document History
1 PLL and Clock Divider Overview
A low frequency external clock is used to drive the internal phase locked loop (PLL)
of xCORE-200 devices and obtain the system clock. A number of system clock
dividers are then used on the system clock to derive the clocks for the xCORE tiles,
the RGMII unit, the switch and the reference clock.
XCore0
Tile
Clk
XCore1
Tile
Clk
Divider
Stage 1
÷(R+1)
CLK Multiplier
Stage
*((F+1)÷2)
Divider
Stage 2
÷(OD+1)
Switch
Divider
System Clock Dividers
Reference
Divider
xCORE Tile
Divider
Switch
Clk
Ref
Clk
Comparator
Freq
VCO
Freq
System
Freq
xCORE Tile
Divider
RGMII
Divider
RGMII
TX Clk
USB
Clk
Figure 1:
PLL and Clock
Dividers
The PLL’s initial settings are determined by the state of any mode pins on the
xCORE-200 device. The standard configuration allows a 25MHz external clock to
be used to operate the xCORE tiles and the switch at 400MHz, and the reference
Publication Date: 2016/10/3 Document Number: XM010761A
XMOS © 2016, All Rights Reserved

xCORE-200 Clock Frequency Control 2/8
clock at 100MHz. In many applications this configuration will be selected, requiring
no reprogramming of the PLL or dividers. If the application requires a different
input frequency or system frequency then the PLL must be reprogrammed. The
xTIMEcomposer tools can be used to reprogram the PLL automatically by specifying
the application’s configuration in the XN file.
2 Constraints
There are a number of constraints on the frequencies of clocks at different points
on the xCORE-200 devices. These constraints must be met for the initial boot
sequence, and if the PLL is reprogrammed, for the reprogrammed values too.
Clock Constraint
CLK 4.22–100.0 MHz
VCO frequency 260–1300 MHz
System clock Maximum operating frequency—see device datasheet
Switch clock System clock maximum
Reference clock System clock maximum
xCORE Tile tiles clock System clock maximum
RGMII clock System clock maximum
USB clock 12 or 24 MHz
Figure 2:
Clock
Frequency
Constraints
3 PLL Settings
There are three dividers within the PLL. R divides the input clock down. The next
divider divides the output of the voltage controlled oscillator (VCO) stage down to
the same frequency as the output of the R divider. Therefore this divider sets the
multiplication factor (F) of the PLL. The OD divider divides the output clock of the
VCO.
There is a constraint on the frequency of the clock at the comparator—the output
of R. There is another constraint placed on the output of the VCO.
4 Configuring the xCORE-200 Device
Some packages have mode pins that are used to determine the initial PLL settings
used after reset. This configuration must be such that all of the constraints are
met for the input clock driven onto CLK.
CLK Range (MHz) Mode 1 Mode 0 XCore Clock (MHz) Multiplier OD F R
3.25-10 MHz 0 0 130-400 MHz 40 1 159 0
9-25 MHz 1 1 144-400 MHz 16 1 63 0
25-50 MHz 1 0 167-400 MHz 8 1 31 0
50-100 MHz 0 1 196-400 MHz 4 1 15 0
Figure 3:
Mode Pins
and Boot Con-
figuration
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If a different PLL configuration is required from that used to boot the application,
the new settings should be written to the PLL_CTRL register. The PLL_CTRL register
comprises five fields (R, F, OD, LOCKN, RESETN), detailed in §5. That register
contains a bit to instruct the PLL to hold the chip in reset, and a bit to pause the
chip whilst the PLL is not locked.
Small changes to either R or F that result in a frequency change of no more than
+/- 20% can be made by writing a new value to the register with a ‘1’ in the RESETN
bit and a ‘1’ in the LOCKN bit (0xCnnn nnnn). The PLL will gradually adjust to the
new values without either the need for a reset or a lock.
Larger changes to R or F, or changes that require both R and F to be modified,
or changes to OD can be made by writing a ‘0’ in the RESETN bit and a ‘0’ in the
LOCKN bit (0x0nnn nnnn).
If you choose to reset the device (by setting the RESETN bit low), the boot code
should read the value of the PLL_CTRL register and compare it to the reconfigured
value. If there is a difference, then this is the first time the boot code has executed
and the new PLL settings should be written to PLL_CTRL, causing a reset. The
second time the boot code executes, the value read back from the PLL_CTRL
register will be the reconfigured value and the boot process can continue.
The easiest way to reprogram the PLL is to specify the application’s frequency
requirements in the XN file and use the xTIMEcomposer tools to reprogram the
PLL—see §8.1.
5 Frequency Control Registers
To access the frequency control registers packets of data must be constructed
and communicated to the Switch through a channel end. Global PLL settings are
controlled through registers in the Node Configuration control registers. From C or
XC, use the write_node_config_reg() and read_node_config_reg() functions defined
in xs1.h. The bits that can be controlled are shown in Figure 4.
Settings on an individual tile basis are controlled through registers in the Tile
Configuration control registes. From C or XC, use the write_tile_config_reg() and
read_tile_config_reg() functions defined in xs1.h. The bits that can be controlled
are shown in Figure 5.
6 Example PLL Configurations
6.1 Standard Configuration: 25MHz Oscillator
Use MODE[1:0] = 11 , ie, leave any mode pins Not Connected. The PLL will configure
to the standard 400MHz, with the xCORE tile and SSwitch running at 400MHz, with
a 100MHz reference clock.
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Register Bitfield Reset Description
XS1_SSWITCH_PLL_CTL_NUM [6:0] Mode Pins R; PLL input divider stage =
R+1
XS1_SSWITCH_PLL_CTL_NUM [20:8] Mode Pins F; Multiplier stage of the PLL
= (F+1)/2
XS1_SSWITCH_PLL_CTL_NUM [25:23] Mode Pins OD; PLL output divider stage
= OD+1
XS1_SSWITCH_PLL_CTL_NUM 30 N/A LOCKN; ’0’ will force a wait
for PLL lock
XS1_SSWITCH_PLL_CTL_NUM 31 N/A RESETN; ’0’ will force reset
on PLL change
XS1_SSWITCH_CLK_DIVIDER_NUM [15:0] 0 System switch clock divider
= SSDIV+1. Reset value pro-
duces 400MHz for a 400MHz
system clock
XS1_SSWITCH_REF_CLK_DIVIDER_NUM [15:0] 3 Reference clock divider = REF-
DIV+1. Reset value produces
100MHz for a 400MHz sys-
tem clock.
Figure 4:
Node Config-
uration
Registers
Register Bitfield Reset Description
XS1_PSWITCH_PLL_CLK_DIVIDER_NUM [15:0] 0 xCORE Tile clock divider =
XCDIV+1. Reset value produces
400MHz for an 400MHz system
clock
Figure 5:
Tile Configu-
ration control
registers
6.2 24MHz Oscillator
Use MODE[1:0] = 11 , ie, leave any mode pins Not Connected. For the initial boot,
the system clock will be 100.0MHz, with the xCORE tile also running at 384 MHz.
The following are required: R = 0, F = 124, OD = 2. Write 0xC1007C00 to the PLL
Settings register in the Node Configuration to bring the PLL output up to 500MHz,
with code similar to the following:
# define P LL _5 00MH z 0 x01 00 7C00
...
un signe d p llCtrlReadData ;
read_node_config_reg ( til e [0] , XS1 _S SW IT CH _P LL _C TL _N UM , p ll Ct rl Re ad Da ta );
if ( pllCt rl ReadData != P LL_500M Hz ) {
writ e_ no de _c on fi g_ reg ( til e [0] , XS 1_ SS WI TC H_ PL L_ CT L_ NU M , PL L_ 50 0M Hz ) ;
}
...
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7 Example System Clock Divider Configurations
7.1 133MHz Reference Clock
To adjust the Reference Clock to 133MHz with a 400MHz System Clock, set REFDIV
to 2using the following code:
w ri te _n o de _c on fi g _r eg ( ti le [0 ] , X S1 _S SW I TC H_ RE F_ CL K_ D IV ID ER _N UM , 0 x0 2 );
This will adjust all timers and clock-blocks to run at 133.3MHz, and allow ports to
be configured at 66MHz, 33MHz and so on.
7.2 Slow Switch Clock
For applications where only a single xCORE-200 device is used, the SSwitch is only
used for configuration purposes. Once the system is configured, the SSwitch clock
can be substantially reduced to save on dynamic power. 1MHz is a good option for
a low power SSwitch clock because the SSwitch power is dominated by the static
power at this frequency.
To reduce the SSwitch clock to 1MHz with a system clock of 400MHz, set SSDIV to
399 using the following code:
wr it e_n od e_c on fig _r eg ( tile [0] , XS1 _S SW ITC H_ CL K_DI VI DE R_N UM , 399) ;
7.3 xCORE Tile Clock 200MHz
If your application does not need to run the xCORE tile at full speed to work,
dynamic power can be saved by running the tile at a slower rate. For this to work,
each tile has its own clock divider that is enabled by setting a bit in the Processor
Status Configuration
To run a tile at 200MHz from a system frequency of 400MHz, set XCDIV to 1 and
enable the clock divider for this processor by writing 0x10 to XCORE_CTRL0:
w ri t e_ t il e _c on f ig _ re g ( til e [ 0] , X S 1_ P SW IT C H_ P LL _C L K_ D IV ID E R_ NU M , 1) ;
se tp s ( XS 1_ PS _X CO RE _C TR L0 ,0 x10 ) ;
8 Configuring the Clock System Through the XN File
The PLL and the reference clock frequency can be programmed automatically for an
application by using the xTIMEcomposer tools. The application’s input oscillator
frequency, system frequency and reference frequency can be specified in the XN
file. When the application code is written to a flash device with XFLASH, the code to
reprogram the PLL to the desired system and reference frequencies will be added.
When run with XRUN or XGDB the PLL is reprogrammed via JTAG.
The frequency control attributes should be added to the Node node within the
XN file. Frequencies should be specified with their unit of MHz, kHz or Hz, (for
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Attribute Description Default Value
Oscillator Input frequency on the CLK pin. If this
attribute is specified, the system fre-
quency and the reference frequency are
programmed using their specified (or de-
fault) values. If this attribute is not speci-
fied, the boot configuration for the system
and reference frequencies are used for the
application.
Uses boot configu-
ration
SystemFrequency The desired system frequency. The Os-
cillator attribute must be specified if this
attribute is specified.
400MHz
ReferenceFrequency The desired reference frequency. The Os-
cillator attribute must be specified if this
attribute is specified.
100MHz
Figure 6:
XN File
Frequency
Control
Attributes
example 500MHz, 24576kHz or 6745800Hz). If the frequency control attributes
are not specified in the XN file, then the xTIMEcomposer tools will not modify the
frequency control registers.
If the target frequency specified in the XN file for either the system or reference
frequency cannot be met exactly for the application’s input frequency, a frequency
close to the target frequency will be selected by the tools and a warning will be
issued. XFLASH always issues the warning when it occurs, as does XGDB. XRUN
only issues the warning if it has been run with the --verbose switch. XGDB issues
the warning when the connect command is issued. Within xTIMEcomposer Studio,
the XFLASH warning is issued to the Console, but the XGDB or XRUN warning is not
available to the user.
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8.1 Example XN file using Frequency Control Attributes
<? xml v er si on = " 1.0 " e nc od in g = "UTF -8 "? >
< Ne tw or k x mln s = " htt p :/ / www . xm os . co m "
xm ln s : xsi = " ht tp : // w ww . w3 . org /2 00 1/ XM LSc he ma - in st an ce "
xs i : sc he ma L oc at io n = " htt p :/ / ww w . xmo s . com ht tp : // w ww . xm os . co m ">
<Type > Board </ Type >
<Declarations >
< Decl arat ion > ti lere f tile [1] </ D eclarat ion >
</Declarations >
<Packages >
< P ac ka ge id = " 0" T ype = " XS2 - UE nA - 512 - T Q12 8 " >
<Nodes >
< No de I d =" 0 " I nP ac k ag eI d = " 0" T yp e = "XS 2 - L 16A - 51 2 " O sc il l at or = " 20 M Hz "
S ys te mF re qu e nc y = " 500 M Hz " >
< T ile N um be r = " 0 " Re fe r en ce = " t il e [ 0] " / >
< T ile N um be r = " 1 " Re fe r en ce = " t il e [ 1] " / >
</ Node >
</ Nod es >
</ Pack age >
</Packages >
<JTAGChain >
< J TA GD ev ic e N od eId = " 0" / >
</JTAGChain >
</ Netw ork >
for more information on XN files see the xTIMEcomposer user guide.
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9 Document History
Date Release Comment
2016-09-30 1.0 First release
Copyright © 2016, All Rights Reserved.
Xmos Ltd. is the owner or licensee of this design, code, or Information (collectively, the “Information”) and
is providing it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in
relation to its use. Xmos Ltd. makes no representation that the Information, or any particular implementation
thereof, is or will be free from any claims of infringement and again, shall have no liability in relation to any
such claims.
XM010761A