abaco systems RTM311 User manual

UM082 RTM311 User Manual r1.3
UM082 www.abaco.com page 1 of 28
RTM311 User Manual
Abaco Systems
Support Portal
This document is the property of Abaco Systems, Inc. and may not be copied nor communicated
to a third party without the written permission of Abaco Systems, Inc.
© Abaco Systems, 2017

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Revision History
Document
Revision
Changes
Author
Peer
Review
Quality
Approval
Date
r1.0
Initial Release
Jpat
Ivk
Ivk
2017/09/25
r1.1
Changed SW4’s default position to
“OFF”
Jpat
Rza
JDS
2017/10/20
r1.2
Added USB3.0 and DisplayPort
verification and BSP details
Added remark about 1000BASE-T
only on RJ45’s
Ivk
Jpat
Ivk
2017/11/17
r1.3
Added/Changed information on
QTE, M.2, SATA and DisplayPort
switch position.
Removed ordering information and
referred to PN document.
Jpat
Ivk
JDS
2018/01/10

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1 Table of Contents
1Table of Contents...........................................................................................................3
2Acronyms........................................................................................................................4
3Terms used.....................................................................................................................4
4Related Documents........................................................................................................4
5General Description.......................................................................................................5
6Installation......................................................................................................................6
7Hardware Specifications ...............................................................................................6
7.1 Physical specifications...............................................................................................6
7.1.1 VPX connectors.......................................................................................................6
7.1.2 Backplane keying ....................................................................................................6
7.1.3 Front panel..............................................................................................................6
7.1.4 Connectors location.................................................................................................7
7.2 ESD Protection..........................................................................................................8
7.3 Switches....................................................................................................................8
7.3.1 “RESET” button/momentary switch.........................................................................8
7.3.2 On-board dip switches.............................................................................................8
7.3.3 I2C switch................................................................................................................9
7.4 LEDs........................................................................................................................10
7.4.1 On-board LEDs .....................................................................................................10
7.4.2 Front panel LEDs ..................................................................................................10
7.5 Connectors..............................................................................................................11
7.5.1 VPX connectors.....................................................................................................11
7.5.2 Front panel connectors..........................................................................................15
7.5.3 On-board connectors.............................................................................................18
7.6 CPLD.......................................................................................................................25
7.7 Battery.....................................................................................................................25
7.8 Safety ......................................................................................................................25
7.9 EMC.........................................................................................................................25
7.10 Warranty..................................................................................................................25
7.11 Ordering Information................................................................................................26
7.12 Appendix A: CPLD Register map...........................................................................27

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2 Acronyms
Table 1: Glossary
FBGA
Fineline Ball Grid Array
FMC
FPGA Mezzanine Card
FPGA
Field Programmable Gate Array
JTAG
Join Test Action Group
LED
Light Emitting Diode
LVDS
Low Voltage Differential Signaling
MGT
Multi-Gigabit Transceiver
MSB
Most Significant Bit(s)
PCB
Printed Circuit Board
PCI
Peripheral Component Interconnect
PCIe
PCI Express
3 Terms used
The terms used in this document are explained as the followings.
•On-board connectors: Any connectors (except the VPX connectors) on the RTM311
that cannot be accessed from the front panel.
•On-board switches: Any switches on the RTM311 that cannot be accessed from the
front panel.
4 Related Documents
•VITA 46.10-2009 (R2015)
•UM083 (VP881 User Manual)

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5 General Description
The RTM311 is a 3U VPX Rear Transition Module. It is intended to be used in combination with
certain 4DSP’s Xilinx FPGA VPX boards, typically VP881. The board implements features that
are required to bring several interfaces of a VPX board to the rear panel. Some of those interfaces
are: USB2.0, USB3.0, DisplayPort, Gigabit Ethernet and SD card. The board also carries a M.2
SSD card that communicates to the VPX through SATA or PCIe.
The global architecture of the RTM311 is shown in Figure 1.
I2C
I2C
I2C
JTAG
ctrl
ctrl
ctrl
VPX
ctrl
2x1000BASE-KX Eth Phy
2x Magnet ics 2x 2x RJ45
1000BASE-T
1xUSB2.0 USB3.0
Hub
1x
USB2.0
1x
USB3.0
1x USB2.0
1x USB3.0
JTAG
JTAG
CPLD
I2C MDIO
Display
Port
Driver
Display
Port
1x DisplayPort 1.2
1x DisplayPort 1.2
/USB3.0
LEDs
1x SATA3.0 SATA
SD
card
1xSDIO
GPIO
Micro
HDMI
2x LVDS
2xGPIO
I2C
Mux
Reset
SW
16x Differential
RP1.9 to RP1.16
MGT and legacy
LVDS
QTE 120 pins
8x MGT
RP0.9 to RP0.16
SATA
Redriver
VPX RP1.1
to RP1.8
RTM311
USB3.0
Figure 1 RTM311 block diagram

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6 Installation
Requirements and handling instructions
•The RTM311 is not hot-pluggable and must be installed in a system that is switched off
•The RTM311 must only be installed with an appropriate VPX board such as VP881
(Contact Abaco Systems for options)
•Prevent electrostatic discharge by observing Electro Static Damage (ESD) precautions
when handling the card
7 Hardware Specifications
This section describes all hardware specifications of the RTM311.
7.1 Physical specifications
7.1.1 VPX connectors
The RTM311 is a 3U VPX Rear Transition Module that has VPX connectors fitted as specified
below:
- VPX RP0: TE connectivity, 1410968-3 is fitted by default.
- VPX RP1: TE connectivity, 1410975-3 is fitted by default.
7.1.2 Backplane keying
Both alignment key1 and key2 are placed by default with the un-keyed version (1-1469492-9).
Contact Abaco Systems if specific keying is required.
7.1.3 Front panel
RTM311 provides various interfaces via the front panel. See section 7.5.2 for more details. The
front panel bezel options are offered as shown below.
•0.8-inch (IEEE 1101.10 and VITA 46 compliant)
•1-inch (IEEE 1101.10 –VITA 46)
•1-inch –VITA 48.1 (as per VITA 65)
It is recommended that the front panel bezel is to be chosen in compliant with the connected VPX
board’s bezel.
NOTE that the RJ45 connectors will only support 1000BASE-T. The ethernet phy’s are hard
configured to 1000BASE-T and will not negotiate with a 10/100BASE link. This is done because
the RJ45 connectors form a bridge to access the VP881 VITA46.6 UTP-1 and UTP-2 interfaces
which only support 1000BASE interface speeds according to the VITA standard.
Make sure to always connect the two RJ45 ports of RTM311 to a 1000BASE-T LAN
connection.

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7.1.4 Connectors location
7.1.4.1 VPX connectors location
The VPX connectors location on the RTM311 is shown in Figure 3 in section 7.1.4.3.
7.1.4.2 Front panel connectors location
The location of connectors is shown in the picture below. Pins assignment is provided in section
7.2.
Figure 2: RTM311 front panel connectors location
7.1.4.3 On-board connectors locations
The location of connectors is shown below. Pins assignment is provided in section 7.5.3.

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Figure 3: RTM311 On-board Connectors locations
7.2 ESD Protection
The front panel connectors have ESD protection compliant to IEC 61000-4-2, ±15kV (air), ±8kV
(contact).
7.3 Switches
On-board switches can be identified by the silkscreen.
7.3.1 “RESET” button/momentary switch
“RESET” button (SW1) is made assessible on the front panel, through a small key hole. The VPX
board can be reset by pressing this button.
7.3.2 On-board dip switches
Their functionalities are explained below. All switches are in “ON” position by default, apart from
SW4 which should be “OFF” by default.
Switch
“ON”
“OFF”
SW2
NVRMO = ‘0’
NVRMO = ‘1’
SW3
M.2 SATA selected
Standard SATA connector selected
SW4
JTAG to on-board CPLD
JTAG to VPX backplane (to the connected VPX
payload card)
SW5
USB3.0 selected
DisplayPort selected

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7.3.3 I2C switch
The I2C interface connects to I2C Master signals that come from the VPX connector pins:
- LOCAL-I2C_SCL: see section 7.5.1.
- LOCAL-I2C_SDA: see section 7.5.1.
It’s called a LOCAL I2C interface, to differ from the SMBus interface on VPX RP0.
The VPX I2C signals connect directly to a I2C level translator PN: TCA9517DGKR, and then to
Texas Instruments part: PCA9548ABS_118. The I2C interface diagram is shown below.
I2C
I2C
I2C
VPX
CPLD
XC2C256-
7VQG100I
I2C
DisplayPort
Driver
SN65DP141
GPIO
Micro
HDMI
PCA9548
MGT and legacy LVDS
QTE 120 pins SATA Redriver
DS100BR111
TCA9517
Side A Side B I2C
Port 1
P2 P4
Muxaddr[2:0], default I2C addr 0x70
Addr: 0x10
Addr: 0x04
Addr: 0x61
P3
I2C
M.2 Socket TCA9517
Side A Side B
Figure 4: Local I2C architecture
The slave addresses are shown in Figure 3 and the table below.
Slave
Slave address (HEX)
I2C switch
0x70
CPLD
0x10
DisplayPort driver
0x04
SATA Re-driver
0x61
Note that: To have access to the I2C interface on DisplayPort driver and SATA re-driver, CPLD’s
Command Register 2,bit2 and bit3 must be set, respectively. For more information refer to
Appendix A.

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The VPX backplane’s I2C interface can be connected to the other RTM311’s I2C interfaces by
writing to the I2C switch to connect its ports as below.
I2C switch (PCA9548) port
Description
Port1
Connect VPX backplane to CPLD, DisplayPort Driver, SATA Re-driver
Port2
Connect VPX backplane to MGT and legacy LVDS on QTE connector.
Port3
Connect VPX backplane to M.2 device
Port4
Connect VPX backplane to the debug connector (see section 7.5.2.2)
7.4 LEDs
7.4.1 On-board LEDs
RTM311 has 2 on-board status LEDs. The LEDs’ functionality is explained in the table below.
LED’s silkscreen
Colour
Description
LED5
GREEN
Displays solid green when 1.8V rail is present
LED6
GREEN
Displays solid green when 1.1V rail is present
7.4.2 Front panel LEDs
RTM311 has 3 front-panel status LEDs. The LEDs’ functionality is explained in the table below.
LED’s front panel label
Colour
Description
VPXRST
RED
Displays solid red when “RESET” button is pressed (VPX board is reset)
ACT
GREEN
Displays solid green when both Ethernet PHYs are configured.
PWR
GREEN
Displays solid green when power to the unit is present.
The integrated LEDs on the RJ45 connectors are also visible on the front panel. Each port on
RJ45 connectors has its own status LEDs which are connected to its own ETH PHY (Marvell,
88E1512). By default, the status LEDs are on dual LED mode 3 (see the datasheet).
Status
LED [1]
LED [0]
1000Mbps Link –No activity
Off
Solid On
1000Mbps Link –Activity
Off
Blink
No link
Off
Off

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7.5 Connectors
The connectors pin assignment tables are broken down as per the VITA 46 connector
nomenclature (RP0, RP1). The wafer positions are also provided.
7.5.1 VPX connectors
7.5.1.1 RP0 connector
Position
Wafer type
Row G
Row F
Row E
Row D
Row C
Row B
Row A
POS_RP0.1
No Wafer
No Wafer
POS_RP0.2
Power
Vs1
Vs1
Vs1
No Pad
Vs2
Vs2
Vs2
POS_RP0.3
Power
Vs3
Vs3
Vs3
No Pad
Vs3
Vs3
Vs3
POS_RP0.4
Single-
ended
SM2
SM3
GND
+12V_AUX
GND
SYSRESET*
NVMRO
POS_RP0.5
Single-
ended
GAP*
GA4*
GND
+3.3V_AUX
GND
SM0
SM1
POS_RP0.6
Single-
ended
GA3*
GA2*
GND
+12V_AUX
GND
GA1*
GA0*
POS_RP0.7
Differential
TCK
GND
TDO
TDI
GND
TMS
TRST*
POS_RP0.8
Differential
GND
REF_CLK-
REF_CLK+
GND
RES_BUS-
RES_BUS +
GND
POS_RP0.9
Differential
Gdiscrete1
GND
FPGA-
TX0-
FPGA-
TX0+
GND
FPGA-RX0-
FPGA-
RX0+
POS_RP0.10
Differential
GND
FPGA-
TX1-
FPGA-
TX1+
GND
FPGA-
RX1-
FPGA-RX1+
GND
POS_RP0.11
Differential
P1-VBAT
GND
FPGA-
TX2-
FPGA-
TX2+
GND
FPGA-RX2-
FPGA-
RX2+
POS_RP0.12
Differential
GND
FPGA-
TX3-
FPGA-
TX3+
GND
FPGA-
RX3-
FPGA-RX3+
GND
POS_RP0.13
Differential
SYS_CON*
GND
FPGA-
TX4-
FPGA-
TX4+
GND
FPGA-RX4-
FPGA-
RX4+
POS_RP0.14
Differential
GND
FPGA-
TX5-
FPGA-
TX5+
GND
FPGA-
RX5-
FPGA-RX5+
GND
POS_RP0.15
Differential
Reserved
GND
FPGA-
TX6-
FPGA-
TX6+
GND
FPGA-RX6-
FPGA-
RX6+
POS_RP0.16
Differential
GND
FPGA-
TX7-
FPGA-
TX7+
GND
FPGA-
RX7-
FPGA-RX7+
GND
Table 2: RP0 pin assignment

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Pin/Signal
Description
Connects to
Vs1
12 Volt non-isolated
Power Supply Tree
Vs2
3.3 Volt non-isolated
Power Supply Tree
Vs3
5 Volt non-isolated
Power Supply Tree
GA [4:0]*, GAP*
Geographical Address Inputs
0-4, Parity
Connects to CPLD.
SM [3:0]
System Management
connections
Connects to 6-pin header (incl GND) and optionally
pulled up to VP_AUX_3P3V if +3.3V_AUX connected.
SM0 and SM1 also connects to CPLD.
RES_BUS+/-
Reserved future use
Not connected on RTM
+3.3V_AUX
3.3V Auxiliary power, System
Management
If connected, this will pull SM [3:0] up to 3V3.
+/- 12V_AUX
Auxiliary Power Supplies
Not connected
SYSRESET*
System Reset
Can be driven from the CPLD
SYS_CON*
System Slot
Connects to CPLD and to 4.7k pull-up
REF_CLK+/-
Reference Clock 25 MHz or
100 MHz
Not connected
NVMRO
Non-Volatile Memory Read
Only
Connects to the CPLD
TCK, TMS,
TRST*, TDI, TDO
(wafer 7)
JTAG Signals
JTAG chain through front-panel and on-board JTAG
connector
FPGA-TX+/-[7:0]
FPGA MGT transmitter
interface
Connects to the QTE connector
FPGA-RX+/-[7:0]
FPGA MGT receiver interface
Connects to the QTE connector
No Pad
The construction of the
connector wafer is such that
there is no circuit pad in this
location
Not connected
Table 3: RP0 connector pin description and connection

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7.5.1.2 RP1 connector
RP1 has all positions loaded with differential wafers. A total of 32 differential pairs are available
on RP1:
Position
Wafer
type
Row G
Row F
Row E
Row D
Row C
Row B
Row A
POS_RP
1.1
Differe
ntial
USB2.0_
VBUS
GND
SATA_TX-
SATA_TX+
GND
SATA_RX-
SATA_RX+
POS_RP
1.2
Differe
ntial
GND
DISP_TX-
/USB3.0_T
X-
DISP_TX+/
USB3.0_TX
+
GND
DISP_RX-
/USB3.0_R
X-
DISP_RX+/
USB3.0_RX
+
GND
POS_RP
1.3
Differe
ntial
USB2.0_
DP
GND
DISP_HOT_
PLUG_DET
ECT
DISP_AUX_
DATA_OUT
GND
FPGA-
LVDS1-
FPGA-
LVDS1+
POS_RP
1.4
Differe
ntial
GND
DISP_AUX_
DATA_IN
DISP_AUX_
DATA_OE
GND
FPGA-
LVDS3-
FPGA-
LVDS3+
GND
POS_RP
1.5
Differe
ntial
USB2.0_
DM
GND
LOCAL-
I2C_SCL-
LOCAL-
I2C_SDA
GND
ZYNQ-
SDIO-CLK
ZYNQ-
SDIO-CMD
POS_RP
1.6
Differe
ntial
GND
ZYNQ-
SDIO-D0
ZYNQ-
SDIO-D1
GND
ZYNQ-
SDIO-D2
ZYNQ-
SDIO-D3
GND
POS_RP
1.7
Differe
ntial
Maskable
reset*
GND
UTP2_RX-
UTP2_RX+
GND
UTP2_TX-
UTP2_TX+
POS_RP
1.8
Differe
ntial
GND
UTP1_RX-
UTP1_RX+
GND
UTP1_TX-
UTP1_TX+
GND
POS_RP
1.9
Differe
ntial
GND
DP0-
DP0+
GND
DP1-
DP1+
POS_RP
1.10
Differe
ntial
GND
DP2-
DP2+
GND
DP3-
DP3+
GND
POS_RP
1.11
Differe
ntial
GND
DP4-
DP4+
GND
DP5-
DP5+
POS_RP
1.12
Differe
ntial
GND
DP6-
DP6+
GND
DP7-
DP7+
GND
POS_RP
1.13
Differe
ntial
GND
DP8-
DP8+
GND
DP9-
DP9+
POS_RP
1.14
Differe
ntial
GND
DP10-
DP10+
GND
DP11-
DP11+
GND
POS_RP
1.15
Differe
ntial
GND
DP12-
DP12+
GND
DP13-
DP13+
POS_RP
1.16
Differe
ntial
GND
DP14-
DP14+
GND
DP15-
DP15+
GND
Table 4 : RP1 connector pin assignment

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Pin/Signal
Description
Interface type
Connects to
USB2.0_VBUS
USB2.0 OTG VBUS
voltage
+5V power
USB power switch
USB2.0_DP/DM
USB2.0 OTG interface
USB diff pair
USB PHY
MaskableReset#
Optional local reset
input
3.3V, open drain
Place 4K7 pull-up to 3V3 and
connect to CPLD.
SATA-TXp/n
SATA Transmitter
signals from front
side module
SATA diff pair
SATA connector (via re-driver),
pin 2 and 3
SATA-RXp/n
SATA Receiver
signals from front
side module
SATA diff pair
SATA connector (via re-driver),
pin 5 and 6
DISP-TXp/n or
USB3.0_TXp/n
DisplayPort/USB3.0
Transmitter signals
from front side
module
DisplayPort/
USB3.0_TX diff pair
Mux/Demux 2:1
DISP-RXp/n or
USB3.0_RXp/n
DisplayPort/USB3.0
Receiver signals from
front side module
DisplayPort/
USB3.0_RX diff pair
Mux/Demux 2:1
UTP1_TXp/n
1000BASE-KX/BX
transmit data
1000BASE-X
Marvell Ethernet PHY 1
UTP1_RXp/n
1000BASE-KX/BX
receive data
1000BASE-X
Marvell Ethernet PHY 1
UTP2_TXp/n
1000BASE-KX/BX
transmit data
1000BASE-X
Marvell Ethernet PHY 2
UTP2_RXp/n
1000BASE-KX/BX
receive data
1000BASE-X
Marvell Ethernet PHY 2
LOCAL-I2C_SCL
I2C clock
1.8V, open drain
I2C switch
LOCAL-I2C_SDA
I2C data
1.8V, open drain
I2C switch
ZYNQ-SDIO*
P1 connector
differential pairs
3.3V
ZYNQ uSD card interface, 3.3V,
can be used as bootloader
FPGA-LVDS1/FPGA-LVDS3
P1 connector
differential pairs
Depending on VPX
payload module FPGA
and interface type
FPGA LVDS pairs, connect to
ESD protection and to HDMI
connector
DISP_HOT_PLUG_DETECT
DisplayPort Hot Plug
Detect
1.8V LVCMOS
Connect to DisplayPort
connector
DISP_AUX_DATA_OUT
DisplayPort Aux Data
Out
1.8V LVCMOS
Connect to DisplayPort AUX IF
driver
DISP_AUX_DATA_IN
DisplayPort Aux Data
In
1.8V LVCMOS
Connect to DisplayPort AUX IF
driver
DISP_AUX_DATA_OE
DisplayPort Aux Data
Out Enable
1.8V LVCMOS
Connect to DisplayPort AUX IF
driver
DPxP/N
Differential pair
Depending on VPX
payload module FPGA
and interface type
Connect to QTE connector
Table 5: RP1 connector pin description and connection

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7.5.2 Front panel connectors
7.5.2.1 RESET button
See section 7.3.1.
7.5.2.2 DEBUG connector
The system can be debugged using a debug cable which is provided with RTM311.
The debug cable is a customised break-out cable shown below.
Each cable end has its own ID label. The “RTM31x Debug” end is to connect to RTM311 via its
front panel’s µHDMI “Debug” connector.
The other ends provide means for debugging with pin assignments shown in the table below.
•“COM0”via a 9-Way Male D-type connector
Pin
VPX signal name
2
FPGA-LVDS1+
3
GND
5
FPGA-LVDS1-
•“COM1”via a 9-Way Male D-type connector
Pin
VPX signal name
2
FPGA-LVDS3+
3
GND
5
FPGA-LVDS3-

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•“JTAG” via a 2X7-Way (2mm pitch) connector
The JTAG connector has pinout compatible with Xilinx USB platform cables. See section 7.5.3.1.
Please note that care should be taken when using the JTAG cable, the cable should be
handled at the connector as there is no strain relief on the cable.
•“DEBUG” via a 5-Way (2.54mm pitch) connector
I2C interface can be used for debugging by writing to the I2C switch to connect port4.
Pin
VPX signal name
1
GPIO_DISC1, Reserved
2
GPIO_DISC0, Reserved
3
GPIO_I2C_SDA
4
GPIO_I2C_SCL
5
GND
7.5.2.3 USB2.0 connector
RTM311 has a USB3.0 hub which accommodates the use of both the USB2.0 and USB3.0
interfaces. The USB2.0 interface is connected to VPX backplane per table below.
USB2.0 connector
VPX backplane signals
Pin1, Vcc
Vs3
Pin2, DATA_N
USB2.0_DM
Pin3, DATA_P
USB2.0_DP
Pin4, GND
GND
7.5.2.4 USB3.0 connector
Ensure that the on-board switch, SW5, is in “ON” position. The USB3.0 interface is connected to
VPX backplane per table below.
USB3.0 connector
VPX backplane signals
Pin1-4
See USB2.0
Pin5, SSRX_N
DISP_TX-/USB3.0_TX-
Pin6, SSRX_P
DISP_TX+/USB3.0_TX+
Pin7, GND
GND
Pin8, SSTX_N
DISP_RX-/USB3.0_RX-
Pin9, SSTX_P
DISP_RX+/USB3.0_RX+

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USB3.0 on RTM311 has not been completely verified because of limited support of this feature in
the Xilinx PetaLinux BSP of the Zynq Ultrascale+ MPSoC device on the VP881. Contact Abaco
sales for more information on the roll-out schedule of an updated Zynq MPSoC BSP for VP881
that fully supports USB3.0.
7.5.2.5 DisplayPort connector
The RTM311 has a DisplayPort CML re-driver and an Aux driver/receiver circuit on-board. The
re-driver is set to GPIO mode by default. The re-driver can be accessed via I2C bus from VPX
backplane custom interface.
Ensure that the on-board switch, SW5, is in “OFF” position. See section 7.3.2.
The DisplayPort interface can be accessed by enabling the I2C/SMBus interface with the CPLD.
See Appendix A: CPLD Register map.
DisplayPort on RTM311 has not been completely verified because of limited support of this
feature in the Xilinx PetaLinux BSP of the Zynq Ultrascale+ MPSoC device on the VP881. Contact
Abaco sales for more information on the roll-out schedule of an updated Zynq MPSoC BSP for
VP881 that fully supports DisplayPort.
7.5.2.6 Ethernet connectors
RTM311 has 2 x 1Gbit ETH interfaces. The ETH PHY is Marvell 88E1512-A0-NNP2I000.
The ports of the PHYs connect to the VPX connector as shown below.
ETH PHY
VPX backplane signals
S1_IN_P/N
UTP1_RX_P/N
S1_OUT_P/N
UTP1_TX_P/N
S2_IN_P/N
UTP2_RX_P/N
S2_OUT_P/N
UTP2_TX_P/N
The Media Dependent Interfaces (MDI) of the PHYs connect to transformers (TG111-S12NYNLF
from HALO).
The MDIO control interfaces of the two PHYs connect to the CPLD which implements a small
protocol to send command across this interface based on I2C commands received from the VPX
backplane.
NOTE that the RJ45 connectors will only support 1000BASE-T. The ethernet phy’s are hard
configured to 1000BASE-T and will not negotiate with a 10/100BASE link. This is done
because the RJ45 connectors form a bridge to access the VP881 VITA46.6 UTP-1 and UTP-
2 interfaces which only support 1000BASE interface speeds according to the VITA standard.
Make sure to always connect the two RJ45 ports of RTM311 to a 1000BASE-T LAN
connection.

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The integrated LEDs of the RJ45 connectors connect to the respective phys. See section 7.4.2
for more information on the LEDs displays.
7.5.3 On-board connectors
In this section, other on-board connectors that cannot be accessed from the front panel will be
discussed.
7.5.3.1 JTAG Connector
The JTAG connector is compatible with standard Xilinx USB platform cables, the pinout is shown
in the table below:
Pin number
Signal
1, 12
Not connected
2
Vref, connected to 3.3V
4
TMS input
6
TCK input
8
TDO output
10
TDI input
13
PGND, has 4.7K pull-up to 3.3V and when pulled down the JTAG connector JTAG interface
becomes active and the VPX JTAG interface is disabled
14
HALT, not connected
3,5,7,9,11
Ground
Figure 5: JTAG connector pinout
7.5.3.2 QTE connector (QTE-060-03-FL-D-A-TR)
RTM311 provides access to VPX backplane’s differential signals via a QTE connectors. The
signals assignment on the QTE connector is per the table below.
Table 6: Signals assignment on the QTE connector
QTE connector pin
VPX RP0 signal
1/3
FPGA-RX0+/ FPGA-RX0-
2/4
FPGA-TX0+/ FPGA-TX0-
7/9
FPGA-RX1+/ FPGA-RX1-
8/10
FPGA-TX1+/ FPGA-TX1-
13/15
FPGA-RX2+/ FPGA-RX2-
14/16
FPGA-TX2+/ FPGA-TX2-
19/21
FPGA-RX3+/ FPGA-RX3-
20/22
FPGA-TX3+/ FPGA-TX3-

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QTE connector pin
VPX RP0 signal
25/27
FPGA-RX4+/ FPGA-RX4-
26/28
FPGA-TX4+/ FPGA-TX4-
31/33
FPGA-RX5+/ FPGA-RX5-
32/34
FPGA-TX5+/ FPGA-TX5-
37/39
FPGA-RX6+/ FPGA-RX6-
38/40
FPGA-TX6+/ FPGA-TX6-
41/43
FPGA-RX7+/ FPGA-RX7-
42/44
FPGA-TX7+/ FPGA-TX7-
47
LOCAL-I2C_SDA (See note below)
48
LOCAL-I2C_SCL (See note below)
50/52
QSE_DP0_P/N
49/51
QSE_DP1_P/N
54/56
QSE_DP2_P/N
53/55
QSE_DP3_P/N
58/60
QSE_DP4_P/N
57/59
QSE_DP5_P/N
62/64
QSE_DP6_P/N
61/63
QSE_DP7_P/N
66/68
QSE_DP8_P/N
65/67
QSE_DP9_P/N
70/72
QSE_DP10_P/N
69/71
QSE_DP11_P/N
74/76
QSE_DP12_P/N
73/75
QSE_DP13_P/N
78/80
QSE_DP14_P/N
77/79
QSE_DP15_P/N
81/83
12V
85/86
5V
82/84
3.3V

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QTE connector pin
VPX RP0 signal
5/6/11/12/17/18/23/24/29/30/
35/36/45/46/87/88/121/122/123/124/
125/126/127/128/129/130/131/132
GND
Other pins
Reserved for future development
The QTE connector has pins location shown in the figure below. Odd pins are located on the top
row, starts from Pin1 on the left and ends with Pin119 on the right. Even pins are located on the
bottom row, starts with Pin2 on the left and ends with Pin120 on the right.
Figure 6: Pin1 and Pin2 location (in yellow) and standoffs location (circled in pink)
Figure 7: SAMTEC mating connector with place for screws circled in pink
To connect to the QTE connector:
•Use a mating connector from SAMTEC with break out direction towards VPX connectors,
shown as a green arrow in Figure 6. Ensure to check the signals assignment in Table 6
and pins location in Figure 6 above.
•Place the mating connector on to the on-board QTE connector.
•Use 2 x 4-40 screws to secure the mating connector to the on-board QTE connector by
inserting the screws on each side of the mating connector (see Figure 6) and tighten them
into the on-board standoffs (approximately 9.45mm stacking height, circled in pink in
Figure 7).
1
2