
2-9 System Micro-Computer
The system micro-computer decodes and executes all
instructions, and controls all datatransfers. Itconsistsof a
microprocessor, an address decoder, RAM and ROM
memories, databuffers/latches, and a real timeclock as
shown in Figure 2-3.
2-10 Microprocessor and Clock Circuits. These circuits
contain a high performance 8-bitmicroprocessor(U201) and
associated clock circuits.The microprocessoroperates on a1
MHz cycle,whichit derives froma 4 MHz ceramicresonator
oscillator(Y201). The 1MHz Q signal is generated by the
microprocessor for use by other circuit.
A4 millisecond (approximately) clock signal, applied tothe
microprocessorinterrupt input, enablesthemicroprocessor
to keeptrackofrealtime.This allows themicroprocessorto
form necessary tasks on a regular basis. The real timeclock
signalis alsousedto keeptrack ofthetime that haselapsed
since the outputwas last changed. This enables
microprocessor todetermine if a CV/CCmode change
occurred before the selected time delay(see Reprogramming
Delay discussionin Section V of the Operating Manual). The
microprocessorinhibits theOCP functionuntilthedelay is
over.
The microprocessor also uses the 4 millisecond clock to
determinewhento refreshthefront paneldisplay andto
perform other regularly scheduled jobs.
The R/W (read/write) output from the microprocessor
indicatesthedirectionofflowonthedata bus,eitherto or
from the microprocessor. A low level R/W signal indicates
that themicroprocessoriswritingdata onto thedata bus.A
high level R/W signal indicates that the microprocessor is
readingdata that wasplacedonthebus by theaddressed
circuit. The microprocessoruses the addressdecodercircuit
andtheaddressbus to specifythedata transferlocations.
Addresses are valid on the rising edge of the Q signal.
2-11 Data Bus latches (U217) and Buffers(U216). The
timingsequence ofthemicroprocessor issuch thatthe
circuits providingdata for themicroprocessorarede-
selected (address disappears) before the microprocessor can
read the data. The databus latches (U217) latch the datato
be readbythe microprocessor.The datais updated on every
falling Q pulse. Dataputon the databus bythe
microprocessor goesaroundthelatchesthoughbuffers
(U216).
2-12 Free-Run and SignatureAnalysis Jumpers. The data
bus isconnected to the microprocessorthroughajumper
pack (W202). For somesignature analysis tests of the
microprocessor kernel (microprocessor, RAM, ROM), the
databusisbrokenbymovingW202fromtheNORMAL
positionto theNOP position(seeparagraph4-23).This
connects a NOP(no operation) code (free run) tothe
microprocessordata inputs.The NOP codedoes not contain
an address for the next instruction so the microprocessor
goes tothe next highest address. Therefore, the address bus
looks like a 16-bitcounter thatcontinuously rolls overand
startsat zero. The contentsofeach address appear
sequentiallyonthedatabus(othersideofthebreak)In
addition,forallsignatureanalysistests,jumperW201
mustbe movedfromtheNORM RUN positionto theSIG
ANALYSISposition (seeparagraph4-23).
2-13 Address Bus and Address Decoder. The
microprocessor has 16 address lines(A0-A15) allowing it to
address 65,536 locations. The address decoder (U208) allows
each addressablecircuittolookat a shorter address.The
chip select signals (CS0-CS8) are decoded from the higher
order address lines (A12-A15). When a databuffer’s CS is
decoded, it places itsdataon the databus lines. When adata
latch’s CS is decoded, the outputof eachlatch will beset to
the logic state thatis present onthe associated databus line.
If the chip select for the RAM (random accessmemory),
ROM (read only memory),or talker/listener chip is
decoded, the selected circuit will decode the lower order
address bits supplied toit onthe address bus.
2-14 Memory(ROMand RAM). The system microcomputer
contains both ROM(U206) and RAM(U207) devices. The
32KKnon-volatile ROM contains the operating program and
parameters. The 2 K static RAMstoresvariables voltageto
beprogrammed, outputcurrent readback, etc. A third
memorychip,shownin theoutput boardinterfaceblockof
Figure 2-3, is the EEPROM (electrically erasable
programmable memory).The EEPROM(U230) storesall of
thesystemconstants includingcalibrationconstants,the
supply’s GPIB address,and model number (see paragraph
2-19).
2-15 Real Time Clock. The real timeclock (U209) consists
ofa14-stageripplecounterthat dividesthe1MHzQclock
signalfrom the microprocessor to produce a pulse every 4
milliseconds. The real-time clock is used bythe
microprocessor toschedule regular jobs as described
previously.TheTIMER ENABLEsignalresets thecounterto
zero.
2-16 OutputBoardsInterface
2-17 Data Buffers. These3-statebuffers (U212) placethe
serialdata fromeach output board andtheEEPROMonthe
supply’s system microcomputer databus lines whenchip
selectCS3 is decoded. Serial datafrom outputboards 1-4
appears ondatabus lines D0-D3, respectively, and EEPROM
2-4
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This circuit provides the interface between the system
microcomputer and each of the output boards (up to 4) in
thepowersupply.Data istransferredseriallyonebit at a
time betweenlatches/buffersontheGPIBboardand
optoisolators on the output boards. As shown in Figure 2-3,
the latches/buffers use data bus lines D0-D3 to send/receive
data from the applicable output. Data line D0 is used for
output board 1, D1 for output board 2, D2 for output board
3 (if present), and D3 for output board 4 (if present). A
controlled and regulated 5 volt line is also generated on the
GPIBboardto operate artoftheopto-isolatorsonthe
output boards. In addition to interfacing with the output
boards, the latches/buffers interface with the 4 K bit serial
EEPROM in which system constants are stored.
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