Alinco DR-235 TMk III User manual

D R - 235T M k I I I
S e r v ic e M a n u a l
C O N T E N T S
SPECIFICATIONS
GENERAL .........................................................
TRANSMITTER................................................
RECEIVER........................................................
CIRC IT D IS C R E TIO N
1) Receiver System DR-235................................
2) Transmitter System DR-235 ............................
3) PLL Synthesizer Circuit DR-235......................
4) CP and Peripheral Circuit..............................
5) Power Supply Circuit .......................................
6) M38268MCA075GP (XA1130).........................
SEM ICO N D C TO R DATA
1) NJM7808FA (XA0102) .....................................
2) TC4S66F (XA0115) ..........................................
3) AN8010M (XA0119).........................................
4) TC4W53F (XA0348) ......................................
5) TA31136FN (XA0404) ......................................
6) LA4425A (XA0410) ..........................................
7) BR24L32FJ (XA0604Z) ...................................
8) L88MS05TLL (XA0675)....................................
9) S-816A50AMC (XA0925) .................................
10) LM2904PWR (XA1103) ...................................
11) LM2902PWR (XA1106) ...................................
12) MB15E07SR (XA1107).....................................
13) S-80845CLNB (XA1120) .................................
14) B 4052BCFV (XA1229) .................................
15) S-AV40 (XA1230).............................................
16) Transistor, Diode and LED Outline Drawing...
17) LCD Connection (TTR3626 PFDHN)............
EXPLODED VIEW
1) LCD Assembly..................................................
2) Top and Front View ..........................................
3) Bottom View......................................................
PARTS LIST
2 CP nit ................................................... 21,22
2 MAIN nit................................................ 22-25
2 Mechanical Parts ..................................... 25
Packing Parts........................................... 25
ACCESSORIES...................................... 25
3,4 ACCESSORIES (SCREW SET)............. 25
4 TNC (EJ41 )............................................ 26
5 TNC (EJ41 ) Packing Parts
................... 27
5 6 ^
6 DR-235 ADJ STMENT
7-9 1) Adjustment Spot ..................................... 28
2) VCO and RX Adjustment Specification.. 29
3) TX Adjustment Specification
.................. 30
10 4) RX Test Specification ............................. 31
10 5) TX Test Specification ............................. 32
10
10 PC BOARD VIEW
11 1) CP nit Side A DR-235 ( P0579) ...... 33
2) CP nit Side B DR-235 ( P0579) ...... 33
11 3) MAIN nit Side A DR-235 ( P0579) ..... 34
12 4) MAIN nit Side B DR-235 ( P0579).... 34
12 5) TNC nit Side A ( P0402) (option) ...... 35
12 6) TNC nit Side B ( P0402) (option) ..... 35
12
13 SCHEMATIC DIAGRAM
14 1) CP nit DR-235 ................................... 36
14 2) MAIN nit DR-235.................................. 37
15 3) TNC nit (option).................................... 38
16
17 BLOCK DIAGRAM
1) DR-235.................................................... 39
18
19
20
A U N C O , I N C

SPECIFICATIONS
■ General
Frequency coverage DR-235
TMklll 216.000 ~ 279.995MHz ( RX )
222.000 - 224.995MHz ( TX )
Operating mode FM 16K0F3E ( Wide mode ) 8K50F3E ( Narrow mode )
Frequency resolution 5 , 8.33 , 10 , 12.5 , 15 , 20 , 25 , 30 , 50 kHz
Number of memory
Channels 100
Antenna impedance 50ohm unbalanced
Power requirement 13.8V DC + / - 15% ( 11.7 ~ 15.8 V )
Ground method Negative ground
Current drain Receive
Transmit 0.6 A ( max.) 0.4 A ( Squelched ) Approx. 8.0 A max.
Operating temperature -10 °C - 60°C
Frequency stability + / - 2.5 ppm
Dimensions 142 ( w ) x 40 ( h ) x 174 ( d ) mm
( 142 x 40 x 188 mm for projection included )
Weight Approx. 1.0 Kg
■ Transmitter
Output power Hi
Mid
Low
25 W
10 W
Approx. 5 W
Modulation system Variable reactance frequency modulation
Maximum Frequency
deviation + / - 5kHz ( Wide mode ) + / - 2.5kHz ( Narrow mode )
Spurious emission -6 0 dB
Adjacent channel power -6 0 dB
Noise and hum ratio - 40 dB ( Wide mode ) - 34 dB ( Narrow mode )
Microphone impedance 2kohm
■ Receiver
Sensitivity -14 dBu for 12 dB SINAD
Receiver circuit Double conversion super-heterodyne
Intermediate frequency 1st 30.85 MHz 2nd 455kHz
Squelch sensitivity -18dBu
Adjacent channel selectivity - 65 dB ( Wide mode ) - 55 dB ( Narrow mode )
Inter-modulation rejection
ratio 60 dB
Spurious and image rejection
ratio 70 dB
Audio output power 2.0 W ( 8ohm , 10%THD )
! NOTE : All specifications are subject to change without notice or obligation.

CIRC IT DESCRIPTION
1) R e c e iv e r S y s te m D R - 2 3 5
The receiver system is a double superheterodyne system with a 30.85 MHz first IF and a 455 kHz
second IF.
1. Front End The received signal at any frequency in the 216.000MHz to 279.995MHz
range is passed through the low-pass filter (L116, L115, L114, L113, C204,
C203, C202, C216 and C215) and tuning circuit (L105, L104 and D105,
D104), and amplified by the RF amplifier (Q107). The signal from Q107 is
then passed through the tuning circuit (LI 03, L107, L102, and varicaps
D103, D107 and D102) and converted into 30.85 MHz by the mixer
(Q106). The tuning circuit, which consists of L105, L104, varicaps D105
and D104, L103, L107, L102, varicaps D103, D107 and D102, is
controlled by the tracking voltage form the VCO. The local signal from the
VCO is passed through the buffer (Q145), and supplied to the source of
the mixer (Q106). The radio uses the lower side of the superheterodyne
system.
2. IF Circuit The mixer mixes the received signal with the local signal to obtain the sum
of and difference between them. The crystal filter (XF101A, XF101B)
selects 30.85 MHz frequency from the results and eliminates the signals
of the unwanted frequencies. The first IF amplifier (Q105) then amplifies
the signal of the selected frequency.
3. Demodulation Circuit After the signal is amplified by the first IF amplifier (Q105), it is input to pin
16 of the demodulator IC (IC108). The second local signal of 30.395 MHz,
which is oscillated by the internal oscillation circuit in 1C108 and crystal
(X104), is input through pin 1 of 1C108. Then, these two signals are mixed
by the internal mixer in IC108 and the result is converted into the second
IF signal with a frequency of 455 kHz. The second IF signal is output from
pin 3 of IC108 to the ceramic filter (FL101 or FL102), where the unwanted
frequency band of that signal is eliminated, and the resulting signal is sent
back to the IC108 through pins 5.
The second IF signal input via pin 5 is demodulated by the internal limiter
amplifier and quadrature detection circuit in IC108, and output as an audio
signal through pin 9.
4. Audio Circuit The audio signal from pin 9 of IC108 is amplified by the audio amplifier
(IC120:A),and switched by the signal switch IC (IC111) and then input it to
the de-emphasis circuit.
and is compensated to the audio frequency characteristics in the
de-emphasis circuit (R203, R207, R213, R209, C191, C218, C217) and
amplified by the AF amplifier (IC120:B). The signal is then input to volume
(VR1) . The adjusted signal is sent to the audio power amplifier (IC117)
through pin 1 to drive the speaker.

5. Squelch Circuit The detected output which is outputted from the pin 9 of IC108 is inputted
to pin 8 of IC108 after it was been amplified by 10120:A and it is outputted
from pin 14 after the noise component was been eliminated from the
composed band pass filter in the built in amplifier of the IC. The adjusted
voltage level at VR101 is delivered to the comparator of the CP .
The voltage is led to pin 2 of CP and compared with the setting voltage.
The squelch will open if the input voltage is lower than the setting voltage.
During open squelch, pin 30 (SQC) of the CP becomes "L" level, AF
control signal is being controlled and sounds is outputted from the
speaker.)
6. AIR Band Reception If it is made air band receiving mode, IF signal is demodulated by AM
decoder of IC108, and is output from pin12 as the AF signal.
7. WIDE/NARROW
Switching circuit The 2nd IF 455 kHz signal which passes through filter FL101 (wide) and
FL102 (narrow) during narrow, changes its width using the width control
switching D115 and D116.
2) T ra n s m itte r S y s te m D R - 2 3 5
1. Modulator Circuit The audio signal is converted to an electrical signal by the microphone,
and input it to the microphone amplifier (Q6). Amplified signal which
passes through mic-mute control IC109 is adjusted to an appropriate
mic-volume by means of mic-gain adjust VR106.
IC114:C and D consists of four operational amplifiers; one amplifier (pins
12, 13, and 14) is composed of pre-emphasis and IDC circuits and the
other (pins 8, 9, and 10) is composed of a splatter filter. The maximum
frequency deviation is obtained by VR107. and input to the signal switch
(IC113) (9600 bps packet signal input switch) and input to the cathode of
the varicap of the VCO, to change the electric capacity in the oscillation
circuit. This produces the frequency modulation.
2. Power Amplifier Circuit The transmitted signal is oscillated by the VCO, amplified by the drive
amplifier (Q145) and younger amplifier (Q115), and input to the final
power module (IC110). The signal is then amplified by the final power
module (IC110) and led to the antenna switch (D110) and low-pass filter
(L113, L114, L115, L116, C215, C216, C202, C203 and C204), where
unwanted high harmonic waves are reduced as needed, and the resulting
signal is supplied to the antenna.
3. APC Circuit Part of the transmission power from the low-pass filter is detected by
D111, converted to DC. The detection voltage is passed through the APC
circuit (IC114:A,IC114:B), then it controls the APC voltage supplied to the
younger amplifier Q115 and the final power module IC110 to fix the
transmission power.

3) PLL Synthesizer Circuit DR- 235
1. PLL The dividing ratio is obtained by sending data from the CP (IC1) to pin 10
and sending clock pulses to pin 9 of the PLL IC (IC116). The oscillated
signal from the VCO is amplified by the buffer (Q134 and Q135) and input
to pin 8 of IC116. Each programmable divider in IC116 divides the
frequency of the input signal by N according to the frequency data, to
generate a comparison frequency of 5 or 6.25 kHz.
2. Reference Frequency
Circuit e re^erence frequency appropriate for the channel steps is obtained by
dividing the 12.8 MHz reference oscillation (X102) by 4250 or 3400,
according to the data from the CP (IC1). When the resulting frequency is
5 kHz, channel steps of 5, 10,15, 20, 25, 30, and 50 kHz are used. When
it is 6.25 kHz, the 12.5 kHz channel step is used.
3. Phase Comparator Circuit The PLL (IC116) uses the reference frequency, 5 or 6.25kHz. The phase
comparator in the IC116 compares the phase of the frequency from the
VCO with that of the comparison frequency, 5 or 6.25kHz, which is
obtained by the internal divider in IC116.
4. PLL Loop Filter Circuit If a phase difference is found in the phase comparison between the
reference frequency and VCO output frequency, the charge pump output
(pin 5) of IC116 generates a pulse signal, which is converted to DC
voltage by the PLL loop filter and input to the varicap of the VCO unit for
oscillation frequency control.
5. VCO Circuit A Colpitts oscillation circuit driven by Q131 directly oscillates the desired
frequency. The frequency control voltage determined in the CP (IC1) and
PLL circuit is input to the varicaps (D122 and D123). This change the
oscillation frequency, which is amplified by the VCO buffer (Q134) and
output from the VCO area.
4) C P a n d P e rip h e ra l C irc u its
1. LCD Display Circuit
2. Dimmer Circuit
3. Reset and Backup
The CP turns ON the LCD via segment and common terminals with 1/4
the duty and 1/3 the bias, at the frame frequency is 64Hz.
The dimmer circuit makes the output of pin 13 of CP (IC1) into "H" level
at set mode, so that Q9 and Q3 will turn ON to make the lamp control
resistor R84 short and make its illumination bright. But on the other hand,
if the dimmer circuit makes pin 13 into "L" level, Q9 and Q3 will turn OFF,
R84's illumination will become dimmer as its hang on voltage falls down in
the working LED (D11, D2, D5, D3 and D6).
When the power form the DC cable increases from Circuits 0 V to 2.5 or
more, "H" level reset signal is output form the reset IC (IC4) to pin 33 of
the CP (IC1), causing the CP to reset. The reset signal, however, waits
at 100, and does not enter the CP until the CP clock (X1) has
stabilized.

4. S (Signal) Meter Circuit The DC potential of pin 12 of iC108 is input to pin 1 of the CP (IC1),
converted from an analog to a digital signal, and displayed as the S-meter
signal on the LCD.
5. DTMF Encoder The CP (IC1) is equipped with an internal DTMF encoder. The DTMF
signal is output from pin 10, through R35, R34 and R261 (for level
adjustment), and then through the microphone amplifier (IC114:D), and is
sent to the varicap of the VCO for modulation. At the same time, the
monitoring tone passes through the AF circuit and is output form the
speaker.
6. Tone Encoder The CP (IC1) is equipped with an internal tone encoder. The tone signal
(67.0 to 250.3 Hz) is output from pin 9 of the CP to the varicap (D120) of
the VCO for modulation.
7. DCS Encoder The CP (IC1) is equipped with an internal DCS code encoder. The
code (023 to 754) is output from pin 9 of the CP to the PLL reference
oscillator. When DCS is ON, DCS M TE circuit (Q126-ON, Q133-ON,
Q132-OFF) works. The modulation activates in X102 side only.
8. CTCSS, DCS Decoder The voice band of the AF output signal from pin 3 of IC120:A is cut by
sharp active fitter IC104:A and D (VCVS) and amplified, then ied to pin 4
of CP . The input signal is compared with the programmed tone
frequency code in the CP . The squelch will open when they match.
During DCS, Q108 is ON, C419 is working and cut off frequency is
lowered.
5) P o w e r S u p p ly C irc u it
When power supply is ON, there is a "L" signal being inputted to pin 39 (PSW) of CP which enables the CP to
work. Then, "H" signal is outputted from the pin 41 (C5C) of CP and drives ON the power supply switch control
Q8 and Q7 which turns the 5VS ON.5VS turns ON the PLL IC116, main power supply switch Q127 and Q122, AF
POWER IC117 and the 8 V of AVR (IC115).During reception, pin 29 (R5) of CP outputs "H" level, Q124 is ON,
and the reception circuits supplied by 8 V.While during transmission, pin 28 (T5) of CP outputs "L" level which is
reverse by Q11 so that the output in Q128 will be "H" level, Q123 is ON, and the transmission circuit is supplied by
8 V.Or, in the case when the condition of PLL is NLOCK, "L" level is outputted from pin 14 of IC116, NLOCK
switch Q148 is OFF,Q129is ON, transmission switch Q128 is OFF which makes the transmission to stop.
1. ACC External Power Supply Terminal
When optional power supply cord DEC-37 etc. is connected to the
external power supply terminal JK101, with ACC power supply ON, switch
Q101 will turn ON, 5 V of AVR IC101 pin 2 (STB) becomes "L" which
makes C5V to turn ON. With this, it can turn the power supply of the radio
ON.

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P65/AN5-
P64/AN4-
P63/SCLK22/AN3-
P62/SCLK21/AN2-
P61/S0 T2/AN1 -
P60/SIN2/AN0-
P57/ADT/DA2-
P56/DA1 *
P55/CNTR1 -
P54/CNTR0-
P53/RTP1-
P52/RTP0-
P51/PWM1-
P50/PWM0-
P47/5EÜYT-
P46/SCLK1-
P45/TXD-
P44/RXD-
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SEG16
SEG17
P30/SEG18
P31/SEG19
P32/SEG20
P33/SEG21
P34/SEG22
P35/SEG23
P36/SEG24
P37/SEG25
P00/SEG26
P01/SEG27
P02/SEG28
•P03/SEG29
P04/SEG30
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No. Terminal Signal I/O Description
1 P67/AN7 SMT IS-meter input
2P66/AN6 SQL I Noise level input for squelch
3P65/AN5 BAT I Battery voltage input
4P64/AN4 TIN I CTCSS tone input / DCS code input
5 P63/SCLK22/AN3 BP1 I Band plan 1
6 P62/SCLK21/AN2 BP2 I Band plan 2
7 P61/SO T2/AN1 DCSW 0DCS signal mute
8P60/SIN2/AN0 RE2 I Rotary encoder input
9P57/ADT/DA2 TO T 0CTCSS tone output / DCS tone output
10 P56/DA1 DO T 0DTMF output
11 P55/CNTR1 SCL 0Serial clock for EEPROM
12 P54/CNTR0 TBST 0Tone burst output
13 P53/RTP1 BP4 I/O Band plan 4 / lamp dimmer HI / LOW switch
14 P52/RTP0 M TE I/O Microphone mute / Security alarm SW
15 P51/PWM1 CLK O Serial clock output for PLL, scramble
16 P50/PWM0 DATA I/O Serial data output for PLL scramble / PLL unlock signal input
17 P47/SRDY1 TSTB I/O Trunking board detection / Strobe signal to trunking board
18 P46/SCLK1 STB 0 Strobe for PLL IC
19 P45/TXD TX 0ART data transmission output
20 P44/RXD RTX I ART data reception output
21 P43/n/TO T BEEP I/O Beep tone / Band plan 3
22 P42/INT2 SEC I Security voltage input
23 P41/INT1 RE1 I Rotary encoder input
24 P40 DSQ I Digital squelch input
25 P77 PTT I PTT input
26 P76 SSTB 0 Strobe signal to scramble IC / Security mode
27 P75 W/N 0Wide Narrow SW
28 P74 T5 0TX power ON / OFF output
29 P73 R5 0RX power ON / OFF output
30 P72 SQC oSQL ON / OFF
31 P71 C/S oDigital scramble ON / OFF
32 P70/INT0 B I Backup signal detection input
33 RESET RESET I Reset input
34 XCIN Xcin - -
35 XCO T Xcout - -
36 XIN Xin -Main clock input
37 XO T Xout -Main clock output
38 VSS GND -CP GND
39 P27 PSW I Power switch input
40 P26 SDA oSerial data for EEPROM
41 P25 C5C 0 C5V power ON / OFF output
42 P24 AIR 0 Air band SW / Tx middle power
43 P23 LOW 0 Tx low power
44 P22 EXP 0 Trunking / Packet data SW
45 P21 SW6 I Key sw 6 (SQL)
46 P20 SW5 I Key sw 5 (CALL)
47 P17 SW4 I Key sw 4 (TSQ)
48 P16 SW3 I Key sw 3 (MHz)
49 P15/SEG39 SW2 I Key sw 2 (V/M)
50 P14/SEG38 SW1 Key sw 1 (F NC)

No. Terminal Signal I/O Description
51 P13/SEG37 DOWN I Mic down input
52 P12/SEG36 D D I Digital unit detect
53 P11/SEG35 SCR I Scramble IC ready signal / PTT input for 9600bps
54 P10/SEG34 P I Mic up input
55 P07/SEG33 S33 0
56 P06/SEG32 S32 0
57 P05/SEG31 S31 0
58 P04/SEG30 S30 0
59 P03/SEG29 S29 0
60 P02/SEG28 S28 0
61 P01/SEG27 S27 0
62 P00/S EG26 S26 0
63 P37/SEG25 S25 0
64 P36/SEG24 S24 0
65 P35/SEG23 S23 0
66 P34/SEG22 S22 0
67 P33/SEG21 S21 0
68 P32/SEG20 S20 0
69 P31/SEG19 S19 0
70 P30/SEG18 S18 0
71
72 SEG17
SEG16 S17 S16 0 0LCD segment signal
73 SEG15 S15 0
74 SEG14 S14 0
75 SEG13 S13 0
76 SEG12 S12 0
77 SEG11 S11 0
78 SEG10 S10 0
79 SEG9 S9 0
80 SEG8 S8 0
81 SEG7 S7 0
82 SEG6 S6 0
83 SEG5 S5 0
84 SEG4 S4 0
85 SEG3 S3 0
86 SEG2 S2 0
87 SEG1 S1 0
88 SEGO SO 0
89 VCC VDD -CP power terminal
90 VREF Vref -AD converter power supply
91 AVSS Avss -AD converter GND
92 COM3 COM3 0 LCD COM3 output
93 COM2 COM2 0 LCD COM2 output
94 COM1 COM1 0 LCD COM1 output
95 COMO COMO 0LCD COMO output
96 VL3 VL3 -LCD power supply
97 VL2 VL2 LCD power supply
98 C2 I - -
99 C1 C1 - -
100 VL1 VL1 I LCD power supply

SEMICOND CTOR DATA
1) N J M 7 8 0 8 F A (X A 0 1 0 2 )
8V (1A) Voltage Regulator
1. INP T
2. COMMON
3. O TP T
1 2 3
O
7808A
J RC
******
2 ) T C 4 S 6 6 F (X A 0 1 1 5 )
Bilateral Switch
5 4
b _____ a
C 9
□
1
1. IN/O T
2. O T/IN
3. VSS
4. CONT
5. VDD a
J^L
□ □ t j
1 2 3
CONT Function (IN-O T)
LDisconnect (Hi Z)
H Connect (290ohm typ.)
3 ) A N 8 0 1 0 M (X A 0 1 1 9 )
10V (50mA) Voltage Regulator Vin
•c 1. O TP T i-L 1
K
C_3 ** 2. COMMON 1 S
u u Ü3. INP T S
1 2 3
Shari circuit
pro to lor 3
Vaut
’ T
0 ------ •
GND
4 ) T C 4 W 5 3 F (X A 0 3 4 8 )
Multiplexer / De-multiplexer
8 7 6 5
n p
1. COMMON
2. INH
3. VEE
4. VSS
5. A
6. ch 1
7. ch 0
8. VDD
Control input ON channel
INH A
LLch 0
LHch 1
H*NONE
* Don’t’t care

5) TA31136FN (XA0404)
Narrow Band FM IF IC
It 15 14 13 12 11 10 9
3
o
n
1136
1 2 3 4 5 6 7 8
1. OSCIN
2. OSC O T
3. MIX O T
4. Vcc
5. IF IN
6. DEC
7. FILO T
8. FILIN
9. AF O T
10. Q AD
11. IF O T
12. RSSI
13. N-DET
14. N-REC
15. GND
16. MIX IN
6) L A 4 4 2 5 A (X A 0 4 1 0 )
5W Audio Power Amplifier
1. Input
2. Small signal GND
3. Large signal GND
4. Output
5. Vcc
¿X
LA4425
***
WILJII i
Test Circuit
1 2 3 4 5
7) B R 2 4 L 3 2 F J (X A 0 6 0 4 Z )
32K-Bit EEPROM
8 7 6 5
R R R R 1. AO
2. A1
3. A2
4. Vss
5. SDA
6. SCL
7. WP
8. Vcc
Name Function
A0...A2
Vss
SDA
SCL
WP
Vcc
ser Configurable Chip Select
Ground
Serial Address / Data / I/O
Serial Clock
Write Protect Input
+2.5 ~ 6.0V Power Supply

5V (500mA) Voltage Regulator with On/Off Function
I ------------ 1
8) L88MS05TLL (XA0675)
1 2 3 4 5
1. Vin
2. STB
3. GND
4. Cn
5. Vout
GND
9) S -8 1 6 A 5 0 A M C (X A 0 9 2 5 )
External Transistor Type 5V Voltage Regulator with On/Off Function
5
p4 f l
B A Z *
B d d
1 2 3
1. EXT
2. Vss
3. ON/OFF
4. Vin
5. Vout
1 0 ) L M 2 9 0 4 P W R (X A 1 1 0 3 )
Dual Operational Amplifiers
8 7 6 5
CD
cn
CVJ
o1
12 3 4
1. Output A
2. Inverting Input A
3. Non-inverting Input A
4. GND
5. Non-inverting Input B
6. Inverting Input B
7. Output B
8. Vcc
11) L M 2 9 0 2 P W R (X A 1 1 0 6 )
Quad Operational Amplifiers
2 3 4 5 6 7
1. Output A
2. Inverting Input A
3. Non-Inverting Input A
4. Vcc
5. Non-inverting Input B
6. Inverting Input B
7. Output B
8. Output C
9. Inverting Input C
10. Non-inverting Input C
11. GND
12. Non-Inverting Input D
13. Inverting Input D
14. Output D

PLL Synthesizer
16 15 14 13 12 11 10 9
12) MB15E07SR (XA1107)
1. OSC IN
2. N. C.
3. Vp
4. Vcc
5. Do
6. GND
7. Xfin
8. fin
9. Clock
10. Data
11. LE
12. PS
13.N.C.
14. LD/fout
15.N.C.
16.N.C.
OSC IN
PS
IE
Data
Clock
Reference
Oscillator
lot errait tent
mode control
(porer save)
l-bit
control latch
Xfin Prescaler
32/33
64/65
fin
Binary I4-bit
rcfcrcncc counter
14-bit latch
SW
Sff FC LDS CS
4-bit latch
19-bit shift register
7-bit latch 11-bit latch
Binaly 7-bit
swallow
counter Binary 11-bit
programmable
counter
ÍP
fr
Phase
comparator
Lock
dctcctor
LD/fr/fp
selector
Charge pump
■LD/fout
Vp
Do
VCC
GND
( Vcc = 2.7 to 5.0V, Ta = -40°C to +85oC )
Parameter Symbo
ICondition Min. Typ. Max. nit
Power supply voltage Vcc -2.7 3.75 5.0 V
Power supply current icc 2500MHz
Vcc=Vp=3.75V 8.0 mA
LPF supply voltage Vp -Vcc -5.5 V
Local oscillator input level Vf in 100MHz to 300MHz
300MHz to 2500MHz -6 -15 +2
+2 dBm
Local oscillator input
frequency fin -100 2500 MHz
Xin input level Vxin -0.5 Vcc Vp-p
Xin input frequency Fxin -340 MHz

4.5V Voltage Detector
13) S-80845CLNB (XA1120)
4 3 1. Vout
2. Vin
3. NC
4. GND
1 4 ) B 4 0 5 2 B F V (X A 1 2 2 9 )
Analog Multiplexer / De-multiplexer
YO (T if] VDD
I
Y2 [T - Y2 VO X2 - 15] X2
Y COMMON [T - Y
IN/OUT XI - J4] XI
Y3 [7 - vs X
U IN/OUT -35 X COMMON
Y1 \T - Y1 x -3U XO
INHIBIT (T - INH X3 W] X3
VEE [T - VEE B A-T ] A
VSS [T IT] B
INHIBIT A B COMMON ON SWITCH
L L L
X Y
XO YO
L H LX1 Y1
L L H X2 Y2
L H H X3 Y3
H**NONE
* Don’t care

222 ~ 225MHz 30W RF Power Module
15) S-AV40 (XA1230)
BLOCK DIAGRAM
G H b
® RF Input (Pin)
(D Gate Voltage (VGG), Power Control
® Drain Voltage (VDD), Battery
(D RF Output (Pout)
© RF Ground (Frange)
ABSOL TE MAXIM M RATING ( Tc = 25 °C, unless otherwise noted )
Symbol Parameter Conditions Ratings nit
VDD Drain Voltage VGG < 5V, Pi = 50mW, Po < 30W 17 V
VGG Gate Voltage VDD < 12.5V, Pin=50mW 6 V
IDD Drain Current 8 A
Pin Input Power 12.5V < VDD < 16.5V, VGG = 5V,
Pi = 50 mW 100 mW Pout Output Power 30 W
Tease (OP) Operation Case Temperature -30 to +100 °C
Tstg Storage Temprature -40 to +110 °C
ELECTRICAL CHARACTERISTICS ( Tc = 25°C, unless otherwise noted )
Symbol Parameter Conditions Ratings nit
Min Typ Max
fFrequency Range 220 246 MHz
Pout Output Power VDD = 12.5V
VGG = 5V
Pin = 50mW
30 W
V TTotal Efficiency 40 %
2fo 2na Harmonic -25 dBc
Pin Input VSWR 3.0 -
IGG Gate Current 1 mA
-Stability VDD=10.5-16,5V, VGG=0-5V, Pin=50mW,
Pout<30W (VGG control),
Load VSWR=3:1 ALL PHASE
All sprious output
than 60dB bellow
desired signal -
-Load VSWR
Tolerance VDD=15.0V, Pin=50mW,
Pout=30W (VGG control),
Load VSWR=10:1 ALL PHASE
No degradation

1 6 ) T ra n s is to r, D io d e a n d L E D O u tlin e D ra w in g
Top View
MI 407
XDÓÓÍ3 DA204U
XDÓÍ3Ó 1SV237 XD0Í4Í
RN731V
XDÔ25T 1SV268 XDÔ3ÔÎ
MA2S728
XD0315 " DAN235E XDÖ32Ö"
ÍH 3
S
K
n— u
JL
BB i—i
«ta
i n ru
i i
t u
A r
H----CT
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TT
m— er
MA2S111
XD0323 RLS 73
XD0363 1SV278 XDÍ3374 MA4S713
"XDO’3’75"1SV282
XD0376 CRG01
XD039Í UDZS5. 6B XD0395*
Q O
n n
MIN
n ~ n
n .□
n~ n
IgD4 D
VDZ5. 1B
XDÖ4Ö2 " S3V60
XDÖ414 RB521S XD04Í8 015AZ3- 0
’’XD045Í" 2SK880GR
XËÔÔ2Δ 3SK293
XÉd053 2SK2539
XËÔ066 ~
iŒ4 M
:XG
G2 Gl
B ___ Q
UF
b n
D S
AK*
FA1111C
XLÖÖ69 ” FA1111C XLÔÔ77 " 2SA1036K
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2SC4245Y
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2SB766A
m m 2SC4915
~xf Ö Í 78 ~ 2SB1386 xf0190 "
c
n
HQ HB BOR
u u u
B C E
QO BHQ
ü
B C E
2SC5551
~xf0194 2SD2620J "xf0208 ~ 2SC6026MFV
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XÛÔ2Ô9 RN1107FV
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B C E
RN2107FV
XÚ02ÍÍ"
c
__ □ __
YH
u u
B E
Rb=lOkohm
Rbe=47kohm
3B HG 9M O CD LU
r» n n
Rb=1Okohm
Rbe=none
XD
n— er
Rb=47kohm
Rbe=47kohm
D6
Rb=4. 7kohm
Rbe=none
XH
n— u
Rb=1Okohm
Rbe=47kohm

V

Íez
f e
ei
O
O
COM3
COM2
C0M1
COMO
17) LCD C on nectio n (T T R 3 6 2 6 P F D H N )

FF0017
EXPLODED VIEW
1) LCD Assembly
ST0064

2) Top and Front View
AA0050
DP0185
‘ NK0072 KZ01D5
NK0073