IP-48ADM16 HARDWARE REFERENCE MANUAL
ALPHI TECHNOLOGY CORP. Page iii REV 13
Part Number: 833-13-000-4000 Copyright ©2007, ALPHI Technology Corporation
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ____________________________________1
1.1 INTRODUCTION ____________________________________________________ 1
1.2 FUNCTIONAL DESCRIPTION__________________________________________ 2
2. THEORY OF OPERATION ____________________________________3
2.1 ANALOG INPUTS ___________________________________________________ 3
2.1.1 SINGLE-ENDED MODE__________________________________________________ 4
2.1.2 DIFFERENTIAL MODE___________________________________________________ 4
2.2 A/D CONVERTER ___________________________________________________ 5
2.2.1 ACQUISITION MODE ___________________________________________________ 5
2.2.2 CONTINUOUS MODE ________________________________________________ 6
3. INTERFACE TO THE IP CARRIER______________________________7
3.1 IDSPACE __________________________________________________________ 7
3.2 MEMSPACE________________________________________________________ 7
3.2.1 ADDRESS MAP _______________________________________________________ 7
3.2.2 DATARAM __________________________________________________________ 8
3.2.3 CHANNEL LIST _______________________________________________________ 8
3.2.4 THRESHOLD HIGH RAM _______________________________________________ 10
3.2.5 THRESHOLD LOW RAM________________________________________________ 10
3.3 IOSPACE _________________________________________________________ 11
3.3.1 ADDRESS MAP ______________________________________________________ 11
3.3.2 INTERNAL CLOCK DIVISOR (ICDH, ICDL) __________________________________ 12
3.3.3 END MEMORY ADDRESS POINTER ________________________________________ 12
3.3.4 STATE MACHINE CURRENT ADDRESS POINTER_______________________________ 12
3.3.5 DATARAM INTERRUPT POINTER REGISTER _________________________________ 12
3.3.6 INTERRUPT /DMA SOURCE _____________________________________________ 13
3.3.7 STOP ACQUISITION REGISTER ___________________________________________ 14
3.3.8 ACQUISITION CONTROL REGISTER________________________________________ 14
3.3.9 TRIGGER REGISTER __________________________________________________ 15
3.3.10 START ACQUISITION __________________________________________________ 16
3.3.11 INTERRUPT VECTOR REGISTER __________________________________________ 16
3.3.12 DIGITAL FILTER REGISTER______________________________________________ 17
3.3.13 CHANNEL INTERRUPT REGISTER #0 [15~0] _________________________________ 17
3.3.14 CHANNEL INTERRUPT REGISTER #1 [31~16] ________________________________ 17
3.3.15 CHANNEL INTERRUPT REGISTER #1 [47~32] ________________________________ 17
3.3.16 STATUS REGISTER ___________________________________________________ 17
3.3.17 RESET INTERRUPT REQUEST #0 _________________________________________ 18
3.3.18 DIRECT A/D READ ___________________________________________________ 18
3.4 RESET ___________________________________________________________ 18
4. CONNECTORS ____________________________________________19
5. JUMPER DESCRIPTIONS ___________________________________19
5.1 CONNECTOR DESCRIPTIONS________________________________________ 20
6. APPLICATION EXAMPLE____________________________________21
6.1 HOW TO SET A CHANNEL AS AD TRIGGER. ___________________________ 21
