Alphi IP-48ADM16TH User manual

IP-48ADM16TH
High Density 48-channel, 16-bit A/D Converter
REFERENCE MANUAL
833-14-000-4000
Version 1.6
August 2008
ALPHI TECHNOLOGY CORPORATION
1898 E. Southern Avenue
Tempe, AZ 85282 USA
Tel: [phone]
Fax: [phone]

IP-48ADM16TH HARDWARE REFERENCE MANUAL
ALPHI TECHNOLOGY CORP. Page ii REV 1.6
Part Number: 833-14-000-4000 Copyright ©2007, ALPHI Technology Corporation
NOTICE
The information in this document has been carefully checked and is believed to
be entirely reliable. While all reasonable efforts to ensure accuracy have been
taken in the preparation of this manual, ALPHI TECHNOLOGY assumes no
responsibility resulting from omissions or errors in this manual or from the use
of information contain herein.
ALPHI TECHNOLOGY reserves the right to make any changes, without notice,
to this or any of ALPHI TECHNOLOGY’s products to improve reliability,
performance, function or design.
ALPHI TECHNOLOGY does not assume any liability arising out of the
application or use of any product or circuit described herein; nor does ALPHI
TECHNOLOGY convey any license under its patent rights or the rights of
others.
ALPHI TECHNOLOGY CORPORATION
All Rights Reserved
This document shall not be duplicated, nor its contents used
for any purpose, unless express permission has been granted in advance.

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Part Number: 833-14-000-4000 Copyright ©2007, ALPHI Technology Corporation
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ____________________________________1
1.1 INTRODUCTION ____________________________________________________ 1
1.2 FUNCTIONAL DESCRIPTION__________________________________________ 2
2. THEORY OF OPERATION ____________________________________3
2.1 ANALOG INPUTS ___________________________________________________ 3
2.1.1 SINGLE-ENDED MODE__________________________________________________ 4
2.1.2 DIFFERENTIAL MODE___________________________________________________ 4
2.2 A/D CONVERTER ___________________________________________________ 5
2.2.1 ACQUISITION MODE ___________________________________________________ 5
2.2.2 CONTINUOUS MODE ________________________________________________ 6
3. INTERFACE TO THE IP CARRIER______________________________7
3.1 IDSPACE __________________________________________________________ 7
3.2 MEMSPACE________________________________________________________ 7
3.2.1 ADDRESS MAP _______________________________________________________ 7
3.2.2 DATARAM _________________________________________________________ 8
3.2.3 CHANNEL LIST _______________________________________________________ 8
3.2.4 THRESHOLD HIGH RAM _______________________________________________ 10
3.2.5 THRESHOLD LOW RAM________________________________________________ 10
3.3 IOSPACE _________________________________________________________ 11
3.3.1 ADDRESS MAP ______________________________________________________ 11
3.3.2 INTERNAL CLOCK DIVISOR (ICDH, ICDL) __________________________________ 12
3.3.3 SCAN_DELAY_COUNTER REGISTER _______________________________________ 12
3.3.4 STATE MACHINE CURRENT ADDRESS POINTER_______________________________ 12
3.3.5 SCAN_COUNTER REGISTER _____________________________________________ 13
3.3.6 SCAN_COUNTER STATUS_______________________________________________ 13
3.3.7 SCAN_COUNTER STATUS_______________________________________________ 13
3.3.8 STOP ACQUISITION REGISTER ___________________________________________ 14
3.3.9 ACQUISITION CONTROL REGISTER________________________________________ 14
3.3.10 TRIGGER REGISTER __________________________________________________ 15
3.3.11 HOST START ACQUISITION _____________________________________________ 17
3.3.12 DIGITAL FILTER REGISTER______________________________________________ 17
3.3.13 CHANNEL INTERRUPT REGISTER #0 [15~0] _________________________________ 17
3.3.14 CHANNEL INTERRUPT REGISTER #1 [31~16] ________________________________ 18
3.3.15 CHANNEL INTERRUPT REGISTER #1 [47~32] ________________________________ 18
3.3.16 STATUS REGISTER #1 _________________________________________________ 18
3.3.17 SOURCE INTERRUPT #0 AND #1__________________________________________ 19
3.3.18 DIRECT A/D READ ___________________________________________________ 19
3.3.19 RESET INTERRUPT REQUEST #1 _________________________________________ 20
3.3.20 INTERRUPT VECTOR REGISTER #0 _______________________________________ 20
3.3.21 INTERRUPT VECTOR REGISTER #1 _______________________________________ 20
3.4 RESET ___________________________________________________________ 20
4. JUMPER DESCRIPTIONS ___________________________________21
4.1 CONNECTOR DESCRIPTIONS________________________________________ 22
5. APPLICATION EXAMPLE____________________________________23

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5.1 HOW TO SET A CHANNEL AS AD TRIGGER. ___________________________ 23
5.2 SINGLE CHANNEL CONVERSION CONTROLLED BY HOST _______________ 23
5.3 SCAN LIST CONVERTED ONCE CONTROLLED BY HOST OR EXTERNAL
TRIGGER _________________________________________________________ 23
5.4 POST TRIGGER ACQUISITION WITH EVENT SIGNAL ____________________ 23
History :
Rev 1.3:
Correct input jumper Table.
Rev 1.4 :
Correct Acquisition Control register.
Rev 1.5 :
Correct Address map base address. 3.2.1,3.2.3
Table2.1.3.1, table 3.3 IO
Internal clock divisor
Rev 1.6:
Modified the clock divisor section and added in sampling period calculation
(3.3.2).

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Part Number: 833-14-000-4000 Copyright ©2007, ALPHI Technology Corporation
1. GENERAL DESCRIPTION
1.1 INTRODUCTION
The IP-48ADM16 is a 16 bit single width IP module designed for high speed burst
A/D data acquisition in 16 bits. The primary features of the IP-48ADM16 are:
•Mix of up to 48 single-ended or 24 differential channels
•On-board voltage reference ( +2.5v, -2.5v )
•Fault and Over-voltage Protected (-40 V, + 55 V) multiplexer
•1 MSPS 16-bit A/D converter
•Software programmable single-ended (SE) or differential (DIFF) input and gain
for each channel
•Input Ranges:- ±10V, ±5V,+/-2.5V,+/-1.25V using a software programmable gain
amplifier
•Additional jumper selectable gain from A/D converter(1-2-4-8)
•Acquisition time <= 1.3 μS without gain and channel change
•Internal sequencer with channel list for acquisition of selected channels
•64k x 16 DATARAM dual ported storage
•Channel list in RAM.
•Programmable Interrupt
•Flash EEPROM for gain/offset correction data
•On board input switches for offset or gain calibration
•Dual threshold level detection for each channel with interrupt possibilities
•Analog trigger with any channel and level selection
•32 MHz IP clock

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Part Number: 833-14-000-4000 Copyright ©2007, ALPHI Technology Corporation
Figure 1.1 : Data Flow Block Diagram
1.2 FUNCTIONAL DESCRIPTION
A data flow block diagram of the IP-48ADM16 is presented in Figure 1-1.
The IP-48ADM16 has 6 fault-protected CMOS analog multiplexers. Each multiplexer
has 8 inputs and one common output. These outputs are acquired by differential
multiplexers. The differential inputs can then be configured for single-ended,
differential, or calibration modes. These outputs go then to a PGA where the gain can
be set for 1, 2, 4, or 8
After the conversion, the data is stored in a 64k by 16 dual ported Data RAM.
Memory pointers can be selected to limit the number of scan gathered, as well as
used to control the generation of interrupts. Continuous acquisition and transfers can
be performed.
Two different threshold levels can be selected for each channel. When enabled the
result of the A/D acquisition is compared with one or both of the thresholds and will
generate a programmable interrupt to the host if the channel is out of the defined
band gap or into the defined band gap.
The board can also be set to monitor one channel and start the acquisition on all the
Channel List whenever the first channel in the channel list is inside or outside a pre-
programmed range.
A programmable digital filter selects the minimum number of consecutive values
before the interrupt is generated, or the acquisition starts.

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2. THEORY OF OPERATION
2.1 ANALOG INPUTS
There are two groups of 24-channel analog inputs that are multiplexed using two
eight-channel multiplexers.
A state machine scans a Channel List, acquires the data and stores them into the
DATARAM memory.
Each multiplexers output goes respectively to a second level of multiplexers that
determines whether the data is in single-ended, differential or in calibration mode,
using the data from the Channel List for that particular acquisition. The output of
these multiplexers is then fed into an instrument amplifier which gain is programmed
on the fly, also from the Channel List. This configuration allows the user to have a mix
of single ended or differential inputs selected on the fly from the Channel List.
While a 1 MSPS A/D converter convert the selected channel, it is possible to select
the next channel to reduce settling time. The channel list of up to 64 location is used
for this purpose.
Also, it is possible to inject a reference signal at the level of the switch upstream of
the PGA amplifier and A/D converter to get a data reference.
The software programmable PGA allows selecting an input range of +/-10v, +/-5v, +/-
2.5v, or +/-1.25v, based on a gain of 1, 2, 4, or 8, when the A/D is selected with a +/-
10V range by jumper.
Additional jumper selectable input range can be selected by modifying the A/D input
level section.
The A/D has a jumper selected programmable gain. The selection applies to all the
inputs of the A/D.
Input level W1 J3
+/-10v 1-3, 4-6, 8-10 1-2
+/-5v 1-2, 4-6, 8-10 1-2
+/-2.5v 1-2, 4-6, 9-10 1-2
0 -+10v 1-2, 3-5, 8-10 1-2
0 -+5v 1-2, 3-5, 9-10 1-2
0 -+2.5v 1-2, 5-7, 9-10 1-2
Note: J3 is factory use, do not change.

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Below is a simple block diagram to show how the data is processed from the input to
the A/D conversion in single-ended and differential modes.
IN 40, 41, 42, 43
44, 45, 46, 47
IN 32, 33, 34, 35
36, 37, 38, 39
IN 24, 25, 26, 27,
28, 29, 30, 31
OUT
MUX #3 A/D
CONVERTER
Gx_00
Gx_01
-IN
+IN
PGA
MUX #4
MUX #5
MUX #6
IN 8, 9,10, 11,
12, 13, 14, 15
OUT
MUX #1
MUX #2
IN 0, 1, 2, 3, 4,
5, 6, 7
IN 16, 17, 18, 19,
20, 21, 22, 23
MUX
MUX
2.1.1 Single-Ended Mode
2.1.2 Differential Mode
In differential mode channel #0 is associated with channel #24 and so on, until the
channel #23 being associated with channel #47.

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Part Number: 833-14-000-4000 Copyright ©2007, ALPHI Technology Corporation
2.2 A/D Converter
The converter used is an Analog Device AD7671. The A/D converter operates
continuously at the selected sampling rate. The A/D is a 1-MSPS 16-bit A/D
converter.
More information is available at www.analogdevices.com.
2.2.1 Acquisition Mode
Setting up the IP-48ADM16 for acquisition is done in several steps:
1) select the Scan clock source:
•Internal with the internal timer (the scan clock divisor needs to be programmed
as well.
•Host writing to the Start Acquisition register.
•Using the signal IPstrobe selected as input.
2) Initializing the Channel Ram list with the channels to acquire:
The A/D result of each channel is stored into the DATARAM in incrementing
order. One to N scan can be stored. Setting the DATARAM pointer to N scan list
will store N scan then the DATARAM re-start to address zero.
3) Next select the trigger source that will start the acquisition
•Host write to the Start Acquisition address (any write will start).
•Input corresponding to channel #47 uses as an external Event Trigger (need to
set-up jumper xx )
•Threshold A/D converter
4) Different possibilities of auto-triggering are available to get automatically more
acquisitions:
a) Nibble scan. One or N Scan are processed and the state machine stops until a
new trigger is generated
b) Continuous scan is performed filling the DATARAM up to the DATARAM
pointer and automatic restart from beginning, using the internal timer.
c) Host can stop the State machine by writing at address Stop acquisition. The
last address written is then available at the DATARAM SM ADDRESS location
register.
d) If using the Threshold A/D converter acquisition can be stopped every
timer the signal is back into the defined zone. Bit # need to be set to “1”
5) Program the interrupts as needed

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2.2.2 CONTINUOUS MODE
If continuous acquisition is desired, then the following procedure is used. Remember
that in a real world scenario, it is not possible to read the data at the maximum rate
that the IP is capable of. There is no way to predict the exact performance as it
depends on the carrier board and the application.
Setting the DATARAM pointer with a desired address lower than the End address or
a number of scan lower than the total scan and enabling an interrupt, the host can
“throttle” the read of A/D data.