Alphi IP-48ADM16TH User manual

IP-48ADM16TH
High Density 48-channel, 16-bit A/D Converter
REFERENCE MANUAL
833-14-000-4000
Version 1.6
August 2008
ALPHI TECHNOLOGY CORPORATION
1898 E. Southern Avenue
Tempe, AZ 85282 USA
Tel: [phone]
Fax: [phone]

IP-48ADM16TH HARDWARE REFERENCE MANUAL
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Part Number: 833-14-000-4000 Copyright ©2007, ALPHI Technology Corporation
NOTICE
The information in this document has been carefully checked and is believed to
be entirely reliable. While all reasonable efforts to ensure accuracy have been
taken in the preparation of this manual, ALPHI TECHNOLOGY assumes no
responsibility resulting from omissions or errors in this manual or from the use
of information contain herein.
ALPHI TECHNOLOGY reserves the right to make any changes, without notice,
to this or any of ALPHI TECHNOLOGY’s products to improve reliability,
performance, function or design.
ALPHI TECHNOLOGY does not assume any liability arising out of the
application or use of any product or circuit described herein; nor does ALPHI
TECHNOLOGY convey any license under its patent rights or the rights of
others.
ALPHI TECHNOLOGY CORPORATION
All Rights Reserved
This document shall not be duplicated, nor its contents used
for any purpose, unless express permission has been granted in advance.

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Part Number: 833-14-000-4000 Copyright ©2007, ALPHI Technology Corporation
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ____________________________________1
1.1 INTRODUCTION ____________________________________________________ 1
1.2 FUNCTIONAL DESCRIPTION__________________________________________ 2
2. THEORY OF OPERATION ____________________________________3
2.1 ANALOG INPUTS ___________________________________________________ 3
2.1.1 SINGLE-ENDED MODE__________________________________________________ 4
2.1.2 DIFFERENTIAL MODE___________________________________________________ 4
2.2 A/D CONVERTER ___________________________________________________ 5
2.2.1 ACQUISITION MODE ___________________________________________________ 5
2.2.2 CONTINUOUS MODE ________________________________________________ 6
3. INTERFACE TO THE IP CARRIER______________________________7
3.1 IDSPACE __________________________________________________________ 7
3.2 MEMSPACE________________________________________________________ 7
3.2.1 ADDRESS MAP _______________________________________________________ 7
3.2.2 DATARAM _________________________________________________________ 8
3.2.3 CHANNEL LIST _______________________________________________________ 8
3.2.4 THRESHOLD HIGH RAM _______________________________________________ 10
3.2.5 THRESHOLD LOW RAM________________________________________________ 10
3.3 IOSPACE _________________________________________________________ 11
3.3.1 ADDRESS MAP ______________________________________________________ 11
3.3.2 INTERNAL CLOCK DIVISOR (ICDH, ICDL) __________________________________ 12
3.3.3 SCAN_DELAY_COUNTER REGISTER _______________________________________ 12
3.3.4 STATE MACHINE CURRENT ADDRESS POINTER_______________________________ 12
3.3.5 SCAN_COUNTER REGISTER _____________________________________________ 13
3.3.6 SCAN_COUNTER STATUS_______________________________________________ 13
3.3.7 SCAN_COUNTER STATUS_______________________________________________ 13
3.3.8 STOP ACQUISITION REGISTER ___________________________________________ 14
3.3.9 ACQUISITION CONTROL REGISTER________________________________________ 14
3.3.10 TRIGGER REGISTER __________________________________________________ 15
3.3.11 HOST START ACQUISITION _____________________________________________ 17
3.3.12 DIGITAL FILTER REGISTER______________________________________________ 17
3.3.13 CHANNEL INTERRUPT REGISTER #0 [15~0] _________________________________ 17
3.3.14 CHANNEL INTERRUPT REGISTER #1 [31~16] ________________________________ 18
3.3.15 CHANNEL INTERRUPT REGISTER #1 [47~32] ________________________________ 18
3.3.16 STATUS REGISTER #1 _________________________________________________ 18
3.3.17 SOURCE INTERRUPT #0 AND #1__________________________________________ 19
3.3.18 DIRECT A/D READ ___________________________________________________ 19
3.3.19 RESET INTERRUPT REQUEST #1 _________________________________________ 20
3.3.20 INTERRUPT VECTOR REGISTER #0 _______________________________________ 20
3.3.21 INTERRUPT VECTOR REGISTER #1 _______________________________________ 20
3.4 RESET ___________________________________________________________ 20
4. JUMPER DESCRIPTIONS ___________________________________21
4.1 CONNECTOR DESCRIPTIONS________________________________________ 22
5. APPLICATION EXAMPLE____________________________________23

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5.1 HOW TO SET A CHANNEL AS AD TRIGGER. ___________________________ 23
5.2 SINGLE CHANNEL CONVERSION CONTROLLED BY HOST _______________ 23
5.3 SCAN LIST CONVERTED ONCE CONTROLLED BY HOST OR EXTERNAL
TRIGGER _________________________________________________________ 23
5.4 POST TRIGGER ACQUISITION WITH EVENT SIGNAL ____________________ 23
History :
Rev 1.3:
Correct input jumper Table.
Rev 1.4 :
Correct Acquisition Control register.
Rev 1.5 :
Correct Address map base address. 3.2.1,3.2.3
Table2.1.3.1, table 3.3 IO
Internal clock divisor
Rev 1.6:
Modified the clock divisor section and added in sampling period calculation
(3.3.2).

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Part Number: 833-14-000-4000 Copyright ©2007, ALPHI Technology Corporation
1. GENERAL DESCRIPTION
1.1 INTRODUCTION
The IP-48ADM16 is a 16 bit single width IP module designed for high speed burst
A/D data acquisition in 16 bits. The primary features of the IP-48ADM16 are:
•Mix of up to 48 single-ended or 24 differential channels
•On-board voltage reference ( +2.5v, -2.5v )
•Fault and Over-voltage Protected (-40 V, + 55 V) multiplexer
•1 MSPS 16-bit A/D converter
•Software programmable single-ended (SE) or differential (DIFF) input and gain
for each channel
•Input Ranges:- ±10V, ±5V,+/-2.5V,+/-1.25V using a software programmable gain
amplifier
•Additional jumper selectable gain from A/D converter(1-2-4-8)
•Acquisition time <= 1.3 μS without gain and channel change
•Internal sequencer with channel list for acquisition of selected channels
•64k x 16 DATARAM dual ported storage
•Channel list in RAM.
•Programmable Interrupt
•Flash EEPROM for gain/offset correction data
•On board input switches for offset or gain calibration
•Dual threshold level detection for each channel with interrupt possibilities
•Analog trigger with any channel and level selection
•32 MHz IP clock

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Figure 1.1 : Data Flow Block Diagram
1.2 FUNCTIONAL DESCRIPTION
A data flow block diagram of the IP-48ADM16 is presented in Figure 1-1.
The IP-48ADM16 has 6 fault-protected CMOS analog multiplexers. Each multiplexer
has 8 inputs and one common output. These outputs are acquired by differential
multiplexers. The differential inputs can then be configured for single-ended,
differential, or calibration modes. These outputs go then to a PGA where the gain can
be set for 1, 2, 4, or 8
After the conversion, the data is stored in a 64k by 16 dual ported Data RAM.
Memory pointers can be selected to limit the number of scan gathered, as well as
used to control the generation of interrupts. Continuous acquisition and transfers can
be performed.
Two different threshold levels can be selected for each channel. When enabled the
result of the A/D acquisition is compared with one or both of the thresholds and will
generate a programmable interrupt to the host if the channel is out of the defined
band gap or into the defined band gap.
The board can also be set to monitor one channel and start the acquisition on all the
Channel List whenever the first channel in the channel list is inside or outside a pre-
programmed range.
A programmable digital filter selects the minimum number of consecutive values
before the interrupt is generated, or the acquisition starts.

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2. THEORY OF OPERATION
2.1 ANALOG INPUTS
There are two groups of 24-channel analog inputs that are multiplexed using two
eight-channel multiplexers.
A state machine scans a Channel List, acquires the data and stores them into the
DATARAM memory.
Each multiplexers output goes respectively to a second level of multiplexers that
determines whether the data is in single-ended, differential or in calibration mode,
using the data from the Channel List for that particular acquisition. The output of
these multiplexers is then fed into an instrument amplifier which gain is programmed
on the fly, also from the Channel List. This configuration allows the user to have a mix
of single ended or differential inputs selected on the fly from the Channel List.
While a 1 MSPS A/D converter convert the selected channel, it is possible to select
the next channel to reduce settling time. The channel list of up to 64 location is used
for this purpose.
Also, it is possible to inject a reference signal at the level of the switch upstream of
the PGA amplifier and A/D converter to get a data reference.
The software programmable PGA allows selecting an input range of +/-10v, +/-5v, +/-
2.5v, or +/-1.25v, based on a gain of 1, 2, 4, or 8, when the A/D is selected with a +/-
10V range by jumper.
Additional jumper selectable input range can be selected by modifying the A/D input
level section.
The A/D has a jumper selected programmable gain. The selection applies to all the
inputs of the A/D.
Input level W1 J3
+/-10v 1-3, 4-6, 8-10 1-2
+/-5v 1-2, 4-6, 8-10 1-2
+/-2.5v 1-2, 4-6, 9-10 1-2
0 -+10v 1-2, 3-5, 8-10 1-2
0 -+5v 1-2, 3-5, 9-10 1-2
0 -+2.5v 1-2, 5-7, 9-10 1-2
Note: J3 is factory use, do not change.

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Below is a simple block diagram to show how the data is processed from the input to
the A/D conversion in single-ended and differential modes.
IN 40, 41, 42, 43
44, 45, 46, 47
IN 32, 33, 34, 35
36, 37, 38, 39
IN 24, 25, 26, 27,
28, 29, 30, 31
OUT
MUX #3 A/D
CONVERTER
Gx_00
Gx_01
-IN
+IN
PGA
MUX #4
MUX #5
MUX #6
IN 8, 9,10, 11,
12, 13, 14, 15
OUT
MUX #1
MUX #2
IN 0, 1, 2, 3, 4,
5, 6, 7
IN 16, 17, 18, 19,
20, 21, 22, 23
MUX
MUX
2.1.1 Single-Ended Mode
2.1.2 Differential Mode
In differential mode channel #0 is associated with channel #24 and so on, until the
channel #23 being associated with channel #47.

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2.2 A/D Converter
The converter used is an Analog Device AD7671. The A/D converter operates
continuously at the selected sampling rate. The A/D is a 1-MSPS 16-bit A/D
converter.
More information is available at www.analogdevices.com.
2.2.1 Acquisition Mode
Setting up the IP-48ADM16 for acquisition is done in several steps:
1) select the Scan clock source:
•Internal with the internal timer (the scan clock divisor needs to be programmed
as well.
•Host writing to the Start Acquisition register.
•Using the signal IPstrobe selected as input.
2) Initializing the Channel Ram list with the channels to acquire:
The A/D result of each channel is stored into the DATARAM in incrementing
order. One to N scan can be stored. Setting the DATARAM pointer to N scan list
will store N scan then the DATARAM re-start to address zero.
3) Next select the trigger source that will start the acquisition
•Host write to the Start Acquisition address (any write will start).
•Input corresponding to channel #47 uses as an external Event Trigger (need to
set-up jumper xx )
•Threshold A/D converter
4) Different possibilities of auto-triggering are available to get automatically more
acquisitions:
a) Nibble scan. One or N Scan are processed and the state machine stops until a
new trigger is generated
b) Continuous scan is performed filling the DATARAM up to the DATARAM
pointer and automatic restart from beginning, using the internal timer.
c) Host can stop the State machine by writing at address Stop acquisition. The
last address written is then available at the DATARAM SM ADDRESS location
register.
d) If using the Threshold A/D converter acquisition can be stopped every
timer the signal is back into the defined zone. Bit # need to be set to “1”
5) Program the interrupts as needed

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2.2.2 CONTINUOUS MODE
If continuous acquisition is desired, then the following procedure is used. Remember
that in a real world scenario, it is not possible to read the data at the maximum rate
that the IP is capable of. There is no way to predict the exact performance as it
depends on the carrier board and the application.
Setting the DATARAM pointer with a desired address lower than the End address or
a number of scan lower than the total scan and enabling an interrupt, the host can
“throttle” the read of A/D data.

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3. INTERFACE TO THE IP CARRIER
The IP carrier controls this IP via a set of registers in the IOSPACE and MEMORY
space.
3.1 IDSPACE
Each IP has a set of register allowing the local Host to identifies the IP module
Manufacturer, type , revision,etc.
Base Address is located in the IP Identification Base address.
These registers are read only.
ID space
address Description Value
$01 Ascii “I” $49
$03 Ascii “P” $50
$05 Ascii “A” $41
$07 Ascii “H” $48
$09 Manufacturer identification $11
$0B Module type $30
$0D Revision module $0A
$0F Reserved $00
$11 Driver ID,low byte $00
$13 Driver ID,high byte $00
$15 Number of bytes used $0A
$17 CRC $00
$19-$3F User space $00
Table 3.1: IDSPACE Registers contents
3.2 MEMSPACE
3.2.1 Address Map
MEMORY + R/W BITS Register
0x00000-1FFFF R/W 16 DATARAM 128k bytes
0x20000-27FFF R/W 8 FLASH memory 4k bytes
0x28000-2807F R/W 12 Channel List RAM
0x28080-280FF R/W 16 Threshold High RAM
0x28100-2817F R/W 16 Threshold Low RAM
Table 3.2: Memory Map

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3.2.2 DATARAM
Address: MEMspace + 0x000000
The DATARAM is a memory area of 65536 16-bit locations, mapped within the IP
memory space.
3.2.3 Channel List
Address: MEMspace + 0x028000
The Channel List is a memory area of 64 12-bit locations, mapped within the IP
memory space. It allows for the setup of calibration, gain and differential / single
ended mode selection on a per channel basis.
BIT 11 BIT10 BIT9 BIT 8 BIT 7-6 BIT 5-0
EXT/INT BAND GAP THRESHOLD
LOW
THRESHOLD
HIGH
SE/DIFF Gain Channel
Channel
Channel number from 0 to 47
Gain Selection
Input gains are selected on a per channel basis according to the following table.
Gx_7 Gx_6 Gain Selected
0 0 The gain selected is 1
0 1 The gain selected is 2
1 0 The gain selected is 4
1 1 The gain selected is 8
Table 2.2.1: Gain Selection
SE/DIFF Single-Ended/Differential mode selection
This bit selects whether the channels are in single ended or differential mode. If the
bit is set to 0, then the channels are in single-ended mode and when the bits are set
to 1 the channels are in differential mode.
Threshold high
Allow interrupts in relation with the “Threshold High” value. See Table 2.2.2 for bit
selection.
Threshold low
Allow interrupts in relation with the “Threshold High” value. See Table 2.2.2 for bit
selection.

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Ext/Int Thresh.
high Thresh. low Interrupt
x 0 0 No interrupt is selected
0 0 1 Selected when value is lower than Threshold Low
0 1 0 Selected when value is lower than Threshold High
0 1 1 Selected when value is outside the range
1 0 1 Selected when value is lower than Threshold High
1 1 0 Selected when value is lower than Threshold Low
1 1 1 Selected when value is inside the range
Table 3.2.2: Threshold Selection
SCAN
LIST
12X64
IN/
OUT
TH_L TH_H DIFF0PGA GAIN CH [47..0]
5..07..6891011Bit
63
DATARAM
64Kx16
AEB
SCAN
DATA
# 0
SCAN
DATA
# N
DATARAM POINTER
Number of scan
COMPARATOR
SCAN
COUNTER
DATARAM POINTER
Address location
SM
address
COMPARATOR
Scan_count_en = 0
Scan_count_en = 1
SRAM POINTER
(INT #1)
INT #1
AD DATA (ch # n)
COMPARATOR
THRESHOLD HIGH
ch # n
0
47
THRESHOLD LOW
Ch # n
0
47
COMPARATOR
Threshold_int ( #1)
Calibration source
Calibration can be done by switching the two inputs of the differential amplifier to:
GND OR +2.5V TO INPUT+ OR -2.5V TO Input, using pre-defined channels:

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Channel number (hex) Input + PGA Input - PGA
52 (0x34) GND GND
56 (0x38) VREF (+2.5 V) GND
60 (0x3C) GND VREF (-2.5 V)
Table 2.1.3.1: Calibration Sources
End of List
Selecting the channel number 63 (0x3F) in a location of the channel list signals to the
state machine that the channel list is finished. Depending on other control bits, the
state machine will either start over from the location 0 in the channel list, or stop.
Channel number (hex)
63 (0x3F) End channel list
3.2.4 Threshold High RAM
Address: MEMspace + 0x028080
The Threshold High RAM is a memory area of 64 12-bit locations, mapped within the
IP memory space. It is used for specifying a threshold high value used by the system
to take specific actions, in relation with the Channel List. The position 0 of this table
gives the value for the channel #0, and so on, until the position 47 corresponding to
channel #47. The locations 48 to 63 are not used.
3.2.5 Threshold Low RAM
Address: MEMspace + 0x028100
The Threshold Low RAM is a memory area of 64 12-bit locations, mapped within the
IP memory space. It is used for specifying a threshold high value used by the system
to take specific actions, in relation with the Channel List. The position 0 of this table
gives the value for the channel #0, and so on, until the position 47 corresponding to
channel #47. The locations 48 to 63 are not used.

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3.3 IOSPACE
3.3.1 Address Map
The registers are accessed in 16-bit mode. The addresses are as an offset to the
IOspace base address.
Iospace + R/W Register
0x00 R/W Internal Clock Divisor Low (bit 0-15)
0x02 R/W Internal Clock Divisor High (bit 16-23)
0x04 R/W Scan delay counter
0X06 R State Machine Current Address Pointer
0X06 W Reset Scan counter, Scan delay counter ,S.M.
address generator
0x08 R/W Scan counter register(end memory address pointer)
0x0A R Scan_counter present position
0X0C W Host Stop Acquisition
0x0E R/W Acquisition Control register
0x10 R/W Trigger register
0x12 W Host Start Acquisition pulse
0x16 R/W Digital Filter Register
0x18 R/W Channel Interrupt Register #0 (bit 0-15)
0x1A R/W Channel Interrupt Register #1 (bit 16-31)
0x1C R/W Channel Interrupt Register #2 (bit 32-47)
0x1E R Status register #1
0x22 W Source of interrupt #0 and # 1
0x24 R A/D Register
0x26 R/W Interrupt Vector Register # 0
0x28 R/W Interrupt Vector Register # 1
0x2A W Reset interrupt #0
0x2C W Reset interrupt # 1
Table 3.3 IO Registers

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3.3.2 Internal Clock Divisor (ICDH, ICDL)
Addresses: IOspace + 0x00 (ICDL)
IOspace + 0x02 (ICDH)
This 24-bit register serves as a divisor on the IP clock when Internal Sampling Clock
is selected in the Acquisition Control Register.
Program the Internal sample clock
)_(10 )1(*3.1*)_(
__min 6Secondsin NhertzinqIPClockFre Ratesamplingimum
+
=
)1(*)sec(3.1)sec_(
+
=
NondsmicroondsmicrointeSamplingRa
Each channel is acquired in 1.3 μS.
For 48 channels sampling rate is every (48 +1) * 1.35 = 66 μS.
Clock divider will be: 32000000 / (1/66*10-6) = 2112 ( $840 Hex).
•$00 - ICDL: Internal clock divisor low word, write 0x0840.
•$02 - ICDH: Internal clock divisor high word, write 0x00.
For 4 channels sampling rate is every (4 +1) * 1.35 = 6.75 μS.
Clock divider will be : 32000000 / 1/6.75 10 E -6 = 216 ( $D8 Hex).
•$00 - ICDL: Internal clock divisor low word, write 0x00D8.
•$02 - ICDH: Internal clock divisor high word, write 0x00.
)1)((*)(32/1)sec_(_
+
=
decimalxHzondsinperiodSampling
Where x is the number that will be will be written into the clock divisor.
For a sampling period of 100us you would write 3199d because
.0001 * 32000000 = x +1, x = 3200 – 1, x = 3199
3.3.3 Scan_delay_counter register
Address: IOspace + 0x04
This 16 bit register provides the number of scans the State machine will acquire after
receiving an external Event signal. When the count is reached a pulse is generated to
stop the Acquisition.
3.3.4 State Machine Current Address Pointer
Address: IOspace + 0x06 (read)
This register contains the position of the DATARAM address currently written to by
the State machine.
Address: IOspace + 0x06 (write)

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A host write will reset the Address Ram generator, the Scan_counter and the
Scan_delay_counter.
3.3.5 Scan_counter register
Address: IOspace + 0x08
This register contains the number of scans the state machine will go through before
stopping or re-starting to zero. The address counter will be reset when the count is
re-started. An interrupt can be issue. The Scan_counter position can be read at
address IOspace + 0x0A
3.3.6 Scan_counter status
Address: IOspace + 0x0A
The Scan_counter position can be read at address IOspace + 0x0A
3.3.7 Scan_counter status
Address: IOspace + 0x0A
The Scan_counter position can be read at address IOspace + 0x0A

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3.3.8 Stop Acquisition Register
Address: IOspace + 0x0C
A write to this register will stop acquisition at the end of the current Channel List. The
module will not do anymore acquisitions until a write to the Start Acquisition Register.
3.3.9 Acquisition Control Register
Address: IOspace + 0x0E
Bits 7-5 Bit 4 Bit 3 Bits 2-0
Sampling Clock Source Reserved
= “0”
Continue
scan
Trigger Enable Source
Bit
15 Bits 14..12 Bits 11 Bit 10 Bit 9 Bit 8
Not
used
Memory block size
allocation
WARP Binary /~2’s
complement
BYTE_
SWAP
IMPULSE
This register allows configuring the acquisition state machine.
Trigger Clock Source
These 3 bits determine the signal used as a trigger to start the acquisition.
Trigger Clock
Source Meaning
000 Host Start Acquisition pulse (write) IOspace + 0x12
001 External event pulse
010 Threshold int. A/D
011 IPStrobe
100 Internal clock Tclk0
Continue scan
When set to “1”, acquisition will be done continuously. The S.M. will go through the
Scan_counter than start again. The address memory generator will also start at “0”.
Sampling Clock Source
These 3 bits determine the signal used for the scan clock. This clock indicates when
the next entry in the Channel List should be executed.
Sampling
Clock Source Meaning
000 Host Start Acquisition pulse (write) IOspace + 0x12
001 External event pulse
010 Threshold int. A/D
011 IPStrobe
100 Internal clock Tclk0

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WARP, IMPULSE
These 2 bits are directly connected to the corresponding input of the A/D chip. They
should both be left to “0”.
Binary /~2’s complement
This bit is directly connected to the corresponding input of the A/D chip. A “1” directs
the A/D chip to output straight binary (0 is the smallest value, 0xffff is the largest). A
“0” directs the chip to use 2’s complement (0x8000 is the smallest value, 0x7fff is the
largest)
BYTE_SWAP
When “0”, the LSB is output on D [7:0] and the MSB is output on D [15:8]. When “1”,
the LSB is output on D [15:8] and the MSB is output on D [7:0].
Memory block size allocation
Programmation of these three bits defines the size of the memory block allocated to
each channel.
BIT 14 BIT 13 BIT 12 Block
size(words) Maximum channels
0 0 0 400 48 up to 64
0 0 1 800 32
0 1 0 1000 16
0 1 1 2000 8
1 0 0 4000 4
1 0 1 8000 2
3.3.10 Trigger Register
Address: IOspace + 0x$10
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Threshold
_ad_en
Event
Enable
output
Master Event_
stop_en
Scat_
scan_en
Not_used Post_
trigger_en
Multiple_
scan_en
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Not used Int_pulse IPstrobe
_en
Event_
polarity
Event_
threshold_
en
Reserved
=”0”
Intrequ1
_en
Intrequ0
_en
All the bits are set to “0” upon Reset.
Multiple scan enable

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When set to “0” (default) the State Machine goes through the scan list once then
stops.
When set to “1” the State Machine will go through the scan list “n” times then stop. “n”
is the number of scans loaded into the Scan counter register.
Post trigger enable
When set to “1” the State Machine will stop when the Scan_delay_counter has
reached the number of scans loaded into it after receiving a trigger.
Scat_scan (nibble)
When the THRESHOLD_AD_EN bit is set there are TWO (2) possible behaviors
depending on the state of the SCAT_SCAN bit:
- If “0”, the scan list is activated and acquisition stops only at the end of the
Scan_counter register.
- If “1”, the scan list is activated but stops when the condition that started the
scan disappears.
In/out=1
In/out =0
SCAT_SCAN = 1
SCAT_SCAN = 0
AEB
The example above is with a filter of 4 values
Event stop Enable
When set to “1”, the input corresponding to the channel #47 is used as an external
EVENT line.
Master
This bit, when set to 1, will make the IP module the source for the sample clock, the
signal will be output on IP-STROBE signal on the IP bus. The MASTER bit allows the
synchronization of multiple IP’s.
Event Enable output
When set to “1”, the input pin corresponding to the channel #47 is used as an
external OUTPUT EVENT line for multiple boards.