Altera Nios II User manual

101 Innovation Drive
San Jose, CA 95134
www.altera.com
TU-N2HWDV-4.0
Tutorial
Nios II Hardware Development
Subscribe
Nios II Hardware Development Tutorial

Nios II Hardware Development Tutorial May 2011 Altera Corporation
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.
& Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective
holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance
with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera
customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or
services.

May 2011 Altera Corporation Nios II Hardware Development Tutorial
Contents
Chapter 1. Nios II Hardware Development
Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Software and Hardware Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
OpenCore Plus Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Nios II System Development Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Analyzing System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Defining and Generating the System in Qsys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Integrating the Qsys System into the Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6
Developing Software with the Nios II Software Build Tools for Eclipse . . . . . . . . . . . . . . . . . . . . . . . 1–6
Running and Debugging Software on the Target Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
Varying the Development Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
Refining the Software and Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
Iteratively Creating a Nios II System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
Verifying the System with Hardware Simulation Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
Creating the Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
Install the Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
Analyze System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
Start the Quartus II Software and Open the Example Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
Create a New Qsys System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10
Define the System in Qsys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11
Specify Target FPGA and Clock Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11
Add the On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12
Add the Nios II Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–14
Add the JTAG UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17
Add the Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18
Add the System ID Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–19
Add the PIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–20
Specify Base Addresses and Interrupt Request Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–22
Generate the Qsys System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–23
Integrate the Qsys System into the Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–24
Instantiate the Qsys System Module in the Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–25
Add IP Variation File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–26
Assign FPGA Device and Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–26
Compile the Quartus II Project and Verify Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–29
Download Hardware Design to Target FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–31
Develop Software Using the Nios II SBT for Eclipse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–32
Create a New Nios II Application and BSP from Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–32
Compile the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–34
Run the Program on Target Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–35
Taking the Next Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–36
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2

iv Contents
Nios II Hardware Development Tutorial May 2011 Altera Corporation

May 2011 Altera Corporation Nios II Hardware Development Tutorial
1. Nios II Hardware Development
This tutorial introduces you to the system development flow for the Nios®II
processor. Using the Quartus®II software and the Nios II Embedded Design Suite
(EDS), you build a Nios II hardware system design and create a software program
that runs on the Nios II system and interfaces with components on Altera®
development boards. The tutorial is a good starting point if you are new to the Nios II
processor or the general concept of building embedded systems in FPGAs.
Building embedded systems in FPGAs involves system requirements analysis,
hardware design tasks, and software design tasks. This tutorial guides you through
the basics of each topic, with special focus on the hardware design steps. Where
appropriate, the tutorial refers you to further documentation for greater detail.
fIf you are interested only in software development for the Nios II processor, refer to
the tutorial in the Getting Started with the Graphical User Interface chapter of the Nios II
Software Developer’s Handbook.
When you complete this tutorial, you will understand the Nios II system
development flow, and you will be able to create your own custom Nios II system.
Design Example
The design example you build in this tutorial demonstrates a small Nios II system for
control applications, that displays character I/O output and blinks LEDs in a binary
counting pattern. This Nios II system can also communicate with a host computer,
allowing the host computer to control logic inside the FPGA.
The example Nios II system contains the following components:
■Nios II/s processor core
■On-chip memory
■Timer
■JTAG UART
■8-bit parallel I/O (PIO) pins to control the LEDs
■System identification component

1–2 Chapter 1: Nios II Hardware Development
Software and Hardware Requirements
Nios II Hardware Development Tutorial May 2011 Altera Corporation
Figure 1–1 is a block diagram showing the relationship among the host computer, the
target board, the FPGA, and the Nios II system.
As shown in Figure 1–1, other logic can exist within the FPGA alongside the Nios II
system. In fact, most FPGA designs with a Nios II system also include other logic. A
Nios II system can interact with other on-chip logic, depending on the needs of the
overall system. For the sake of simplicity, the design example in this tutorial does not
include other logic in the FPGA.
Software and Hardware Requirements
This tutorial requires you to have the following software:
■Altera Quartus II software version 11.0 or later—The software must be installed on
a Windows or Linux computer that meets the Quartus II minimum requirements.
fFor system requirements and installation instructions, refer to Altera
Software Installation and Licensing.
■Nios II EDS version 11.0 or later.
■Design files for the design example—A hyperlink to the design files appears next
to this document on the Literature: Nios II Processor page of the Altera website.
Figure 1–1. Tutorial Design Example
Nios II System
Character
I/O
Instr
Data
Debug
control 8
Other logic
Altera FPGA
Target Board
LED5
LED0
LED1
LED2
LED3
LED4
LED6
LED7
VCC
Clock
oscillator
System interconnect fabric
Timer
PIO
System
ID
On-chip
RAM
Nios II/s
core
JTAG
UART
JTAG controller
10-pin
JTAG
header

Chapter 1: Nios II Hardware Development 1–3
OpenCore Plus Evaluation
May 2011 Altera Corporation Nios II Hardware Development Tutorial
You can build the design example in this tutorial with any Altera development board
or your own custom board that meets the following requirements:
■The board must have an Altera Stratix®series, Cyclone®series, or Arria®series
FPGA.
■The FPGA must contain a minimum of 2500 logic elements (LE) or adaptive look-
up tables (ALUT).
■The FPGA must contain a minimum of 50 M4K or M9K memory blocks.
■An oscillator must drive a constant clock frequency to an FPGA pin. The
maximum frequency limit depends on the speed grade of the FPGA. Frequencies
of 50 MHz or less should work for most boards; higher frequencies might work.
■FPGA I/O pins can optionally connect to eight or fewer LEDs to provide a visual
indicator of processor activity.
■The board must have a JTAG connection to the FPGA that provides a
programming interface and communication link to the Nios II system. This
connection can be a dedicated 10-pin JTAG header for an Altera USB-Blaster™
download cable (revision B or higher) or a USB connection with USB-Blaster
circuitry embedded on the board.
1To complete this tutorial, you must refer to the documentation for your board that
describes clock frequencies and pinouts. For Altera development boards, you can find
this information in the associated reference manual.
fFor information about Altera development kits and development boards, refer to the
Literature: Development Kits page of the Altera website.
OpenCore Plus Evaluation
You can perform this tutorial on hardware without a license. With Altera's free
OpenCore Plus evaluation feature, you can perform the following actions:
■Simulate the behavior of a Nios II processor within your system
■Verify the functionality of your design
■Evaluate the size and speed of your design quickly and easily
■Generate time-limited device programming files for designs that include Nios II
processors
■Program a device and verify your design in hardware
You need to purchase a license for the Nios II processor only when you are completely
satisfied with its functionality and performance, and want to use your design in
production.
fFor more information about OpenCore Plus, refer to OpenCore Plus Evaluation of
Megafunctions.

1–4 Chapter 1: Nios II Hardware Development
Nios II System Development Flow
Nios II Hardware Development Tutorial May 2011 Altera Corporation
Nios II System Development Flow
This section discusses the complete design flow for creating a Nios II system and
prototyping it on a target board. Figure 1–2 shows the Nios II system development
flow.
The Nios II development flow consists of three types of development: hardware
design steps, software design steps, and system design steps, involving both
hardware and software. For simpler Nios II systems, one person might perform all
steps. For more complex systems, separate hardware and software designers might be
responsible for different steps. System design steps involve both the hardware and
software, and might require input from both sides. In the case of separate hardware
and software teams, it is important to know exactly what files and information must
be passed between teams at the points of intersection in the design flow.
The design steps in this tutorial focus on hardware development, and provide only a
simple introduction to software development.
fAfter completing this tutorial, refer to the Nios II Software Developer’s Handbook,
especially the tutorial in the Getting Started with the Graphical User Interface chapter, for
more information about the software development process. The handbook is a
complete reference for developing software for the Nios II processor.
Figure 1–2. Nios II System Development Flow
Altera
hardware
abstraction
layer
and
peripheral
drivers
Define and generate
system in Qsys
Analyze system
requirements
User C/C++
application
code and
custom
libraries
Custom
instruction
and
custom
peripheral
logic
Custom
hardware
modules
Nios II
cores
and
standard
peripherals
Integrate Qsys system
into Quartus II project Develop software with
the Nios II Software
Build Tools for Eclipse
Assign pin locations,
timing requirements
and other design constraints
Download FPGA design
to target board
Compile hardware design
for target board Run and debug software
on target board
Refine software
and hardware
Download software executable
to Nios II system on target board

Chapter 1: Nios II Hardware Development 1–5
Nios II System Development Flow
May 2011 Altera Corporation Nios II Hardware Development Tutorial
Analyzing System Requirements
The development flow begins with predesign activity which includes an analysis of
the application requirements, such as the following questions:
■What computational performance does the application require?
■How much bandwidth or throughput does the application require?
■What types of interfaces does the application require?
■Does the application require multithreaded software?
Based on the answers to these questions, you can determine the concrete system
requirements, such as:
■Which Nios II processor core to use: smaller or faster.
■What components the design requires and how many of each kind.
■Which real-time operating system (RTOS) to use, if any.
■Where hardware acceleration logic can dramatically improve system performance.
For example:
■Could adding a DMA component eliminate wasted processor cycles copying
data?
■Could a custom instruction replace the critical loop of a DSP algorithm?
Analyzing these topics involve both the hardware and software teams.
Defining and Generating the System in Qsys
After analyzing the system hardware requirements, you use Qsys to specify the
Nios II processor core(s), memory, and other components your system requires. Qsys
automatically generates the interconnect logic to integrate the components in the
hardware system.
You can select from a list of standard processor cores and components provided with
the Nios II EDS. You can also add your own custom hardware to accelerate system
performance. You can add custom instruction logic to the Nios II core which
accelerates CPU performance, or you can add a custom component which offloads
tasks from the CPU. This tutorial covers adding standard processor and component
cores, and does not cover adding custom logic to the system.
The primary outputs of Qsys are the following file types:
■Qsys Design File (.qsys)—Contains the hardware contents of the Qsys system.
■SOPC Information File (.sopcinfo)—Contains a description of the contents of the
.qsys file in Extensible Markup Language File (.xml) format. The Nios II EDS uses
the .sopcinfo file to create software for the target hardware.
■Hardware description language (HDL) files—Are the hardware design files that
describe the Qsys system. The Quartus II software uses the HDL files to compile
the overall FPGA design into an SRAM Object File (.sof).

1–6 Chapter 1: Nios II Hardware Development
Nios II System Development Flow
Nios II Hardware Development Tutorial May 2011 Altera Corporation
fFor more information about the following topics, refer to the related documentation:
■For Nios II processor cores, refer to the Nios II Processor Reference Handbook.
■For Qsys and developing custom components, refer to the System Design with Qsys
section of Volume 1: Design and Synthesis of the Quartus II Handbook.
■For custom instructions, refer to the Nios II Custom Instruction User Guide.
Integrating the Qsys System into the Quartus II Project
After generating the Nios II system using Qsys, you integrate it into the Quartus II
project. Using the Quartus II software, you perform all tasks required to create the
final FPGA hardware design.
As shown in Figure 1–1 on page 1–2, most FPGA designs include logic outside the
Nios II system. You can integrate your own custom hardware modules into the FPGA
design, or you can integrate other ready-made intellectual property (IP) design
modules available from Altera or third party IP providers. This tutorial does not cover
adding other logic outside the Nios II system.
Using the Quartus II software, you also assign pin locations for I/O signals, specify
timing requirements, and apply other design constraints. Finally, you compile the
Quartus II project to produce a .sof to configure the FPGA.
You download the .sof to the FPGA on the target board using an Altera download
cable, such as the USB-Blaster. After configuration, the FPGA behaves as specified by
the hardware design, which in this case is a Nios II processor system.
fFor further information about using the Quartus II software, refer to Introduction to the
Quartus II Software, the Quartus II Handbook, and the Quartus II Software Interactive
Tutorial in the Training Courses section of the Altera website.
Developing Software with the Nios II Software Build Tools for Eclipse
Using the Nios II Software Build Tools (SBT) for Eclipse™, you perform all software
development tasks for your Nios II processor system. After you generate the system
with Qsys, you can begin designing your C/C++ application code immediately with
the Nios II SBT for Eclipse. Altera provides component drivers and a hardware
abstraction layer (HAL) which allows you to write Nios II programs quickly and
independently of the low-level hardware details. In addition to your application code,
you can design and reuse custom libraries in your Nios II SBT for Eclipse projects.
To create a new Nios II C/C++ application project, the Nios II SBT for Eclipse uses
information from the .sopcinfo file. You also need the .sof file to configure the FPGA
before running and debugging the application project on target hardware.
The Nios II SBT for Eclipse can produce several outputs, listed below. Not all projects
require all of these outputs.
■system.h file—Defines symbols for referencing the hardware in the system. The
Nios II SBT for Eclipse automatically create this file when you create a new board
support package (BSP).
■Executable and Linking Format File (.elf)—Is the result of compiling a C/C++
application project, that you can download directly to the Nios II processor.

Chapter 1: Nios II Hardware Development 1–7
Nios II System Development Flow
May 2011 Altera Corporation Nios II Hardware Development Tutorial
■Hexadecimal (Intel-Format) File (.hex)—Contains initialization information for
on-chip memories. The Nios II SBT for Eclipse generate these initialization files for
on-chip memories that support initialization of contents.
■Flash memory programming data—Is boot code and other arbitrary data you
might write to flash memory. The Nios II SBT for Eclipse includes a flash
programmer, which allows you to write your program to flash memory. The flash
programmer adds appropriate boot code to allow your program to boot from flash
memory. You can also use the flash programmer to write arbitrary data to flash
memory.
This tutorial focuses on downloading only the .elf directly to the Nios II system.
fFor extensive information about developing software for the Nios II processor, refer to
the Nios II Software Developer's Handbook.
Running and Debugging Software on the Target Board
The Nios II SBT for Eclipse provides complete facilities for downloading software to a
target board, and running or debugging the program on hardware. The Nios II SBT
for Eclipse debugger allows you to start and stop the processor, step through code, set
breakpoints, and analyze variables as the program executes.
fFor information about running and debugging Nios II programs, refer to the tutorial
in the Getting Started with the Graphical User Interface chapter of the Nios II Software
Developer’s Handbook.
Varying the Development Flow
The development flow is not strictly linear. This section describes common variations.
Refining the Software and Hardware
After running software on the target board, you might discover that the Nios II
system requires higher performance. In this case, you can return to software design
steps to make improvements to the software algorithm. Alternatively, you can return
to hardware design steps to add acceleration logic. If the system performs multiple
mutually exclusive tasks, you might even decide to use two (or more) Nios II
processors that divide the workload and improve the performance of each individual
processor.
Iteratively Creating a Nios II System
A common technique for building a complex Nios II system is to start with a simpler
Qsys system, and iteratively add to it. At each iteration, you can verify that the system
performs as expected. You might choose to verify the fundamental components of a
system, such as the processor, memory, and communication channels, before adding
more complex components. When developing a custom component or a custom
instruction, first integrate the custom logic into a minimal system to verify that it
works as expected; later you can integrate the custom logic into a more complex
system.

1–8 Chapter 1: Nios II Hardware Development
Creating the Design Example
Nios II Hardware Development Tutorial May 2011 Altera Corporation
fAltera provides several working Nios II reference designs which you can use as a
starting point for your own designs. After installing the Nios II EDS, refer to the
<Nios II EDS install path>/examples/verilog or the <Nios II EDS install path>/
examples/vhdl directory. Demonstration applications are also available in newer
development kit installations.
Verifying the System with Hardware Simulation Tools
You can perform hardware simulation of software executing on the Nios II system,
using tools such as the ModelSim®RTL simulator. Hardware simulation is useful to
meet certain needs, including the following cases:
■To verify the cycle-accurate performance of a Nios II system before target
hardware is available.
■To verify the functionality of a custom component or a Nios II custom instruction
before trying it on hardware.
A hardware simulation step is not shown in Figure 1–2 on page 1–4. If you are
building a Nios II system based on the standard components provided with the
Nios II EDS, the easiest way to verify functionality is to download the hardware and
software directly to a development board.
fFor information about performing hardware simulation for Nios II system, refer to
Simulating Nios II Embedded Processor Designs.
Creating the Design Example
This section guides you through the Nios II development flow to create a working
design example. You perform the following steps:
1. “Install the Design Files” on page 1–8.
2. “Analyze System Requirements” on page 1–9.
3. “Start the Quartus II Software and Open the Example Project” on page 1–9.
4. “Create a New Qsys System” on page 1–10.
5. “Define the System in Qsys” on page 1–11.
6. “Integrate the Qsys System into the Quartus II Project” on page 1–24.
7. “Download Hardware Design to Target FPGA” on page 1–31.
8. “Develop Software Using the Nios II SBT for Eclipse” on page 1–32.
9. “Run the Program on Target Hardware” on page 1–35.
Install the Design Files
Before you proceed, you must install the Quartus II software and the Nios II EDS. You
must also download tutorial design files from the Altera web site. The design files
provide a ready-made Quartus II project to use as a starting point.
fThe design files appear next to this document on the Literature: Nios II Processor
page of the Altera website.

Chapter 1: Nios II Hardware Development 1–9
Creating the Design Example
May 2011 Altera Corporation Nios II Hardware Development Tutorial
Perform the following steps to set up the design environment:
1. Locate the zipped design files on the Altera web site.
2. Unzip the contents of the zip file to a directory on your computer. Do not use
spaces in the directory path name.
The remainder of this tutorial refers to this directory as the <design files directory>.
Analyze System Requirements
This section describes the system requirements for the tutorial design example. The
design example has the following goals:
■Demonstrate a simple Nios II processor system that you can use for control
applications.
■Build a practical, real-world system, while providing an educational experience.
■Demonstrate the most common and effective techniques to build practical, custom
Nios II systems.
■Build a Nios II system that works on any board with an Altera FPGA. The entire
system must use only on-chip resources, and not rely on the target board.
■The design should conserve on-chip logic and memory resources so it can fit in a
wide range of target FPGAs.
These goals lead to the following design decisions:
■The Nios II system uses only the following inputs and outputs:
■One clock input, which can be any constant frequency.
■Eight optional outputs to control LEDs on the target board.
■The design uses the following components:
■Nios II/s core with 2 KB of instruction cache
■20 KB of on-chip memory
■Timer
■JTAG UART
■Eight output-only parallel I/O (PIO) pins
■System ID component
fFor more information about these and other components, refer to the Embedded
Peripherals IP User Guide.
Start the Quartus II Software and Open the Example Project
To start, you open the Quartus II project for the tutorial design example. This
Quartus II project serves as an easy starting point for the Nios II development flow.
The Quartus II project contains all settings and design files required to create the .sof.

1–10 Chapter 1: Nios II Hardware Development
Creating the Design Example
Nios II Hardware Development Tutorial May 2011 Altera Corporation
To open the Quartus II project, perform the following steps:
1. Start the Quartus II software.
On Windows computers, click Start, point to Programs, Altera, Quartus II
<version>, and then click Quartus II <version>. On Linux computers, type
quartus
at a shell command prompt, assuming the Quartus II program directory is in the
search path.
2. Click Open Existing Project on the splash screen, or, on the File menu, click Open
Project. The Open Project dialog box appears.
3. Browse to the <design files directory>.
4. Select the file nios2_quartus2_project.qpf and click Open. The project opens.
5. To display the Block Diagram File (.bdf) nios2_quartus2_project.bdf (Figure 1–3),
perform the following steps:
a. On the File menu, click Open. The Open dialog box appears.
b. Browse to the <design files directory>.
c. Select nios2_quartus2_project.bdf and click Open.
Figure 1–3 shows the nios2_quartus2_project.bdf file.
The .bdf contains an input pin for the clock input and eight output pins to drive LEDs
on the board. Next, you create a new Qsys system, which you ultimately connect to
these pins.
Create a New Qsys System
You use Qsys to generate the Nios II processor system, adding the desired
components, and configuring how they connect together. To create a new Qsys
system, click Qsys on the Tools menu in the Quartus II software. Qsys starts and
displays the System Contents tab.
Figure 1–3. Design Example Block Diagram File

Chapter 1: Nios II Hardware Development 1–11
Creating the Design Example
May 2011 Altera Corporation Nios II Hardware Development Tutorial
Figure 1–4 shows the Qsys GUI in its initial state.
Define the System in Qsys
You use Qsys to define the hardware characteristics of the Nios II system, such as
which Nios II core to use, and what components to include in the system. Qsys does
not define software behavior, such as where in memory to store instructions or where
to send the
stderr character stream.
In this section, you perform the following steps:
1. Specify target FPGA and clock settings.
2. Add the Nios II core, on-chip memory, and other components.
3. Specify base addresses and interrupt request (IRQ) priorities.
4. Generate the Qsys system.
The Qsys design process does not need to be linear. The design steps in this tutorial
are presented in the most straightforward order for a new user to understand.
However, you can perform Qsys design steps in a different order.
Specify Target FPGA and Clock Settings
The Clock Settings and the Project Settings tabs specify the Qsys system's
relationship to other devices in the system.
Figure 1–4. Qsys GUI

1–12 Chapter 1: Nios II Hardware Development
Creating the Design Example
Nios II Hardware Development Tutorial May 2011 Altera Corporation
Perform the following steps:
1. On the Project Settings tab, select the Device Family that matches the Altera
FPGA you are targeting.
1If a warning appears stating the selected device family does not match the
Quartus project settings, ignore the warning. You specify the device in the
Quartus project settings later in this tutorial.
2. In the documentation for your board, look up the clock frequency of the oscillator
that drives the FPGA.
fFor Altera development board reference manuals, refer to the Literature:
Development Kits page of the Altera website.
3. On the Clock Settings tab, double-click the clock frequency in the MHz column
for
clk_0 . clk_0 is the default clock input name for the Qsys system. The
frequency you specify for
clk_0 must match the oscillator that drives the FPGA.
4. Type the clock frequency and press Enter.
Next, you begin to add hardware components to the Qsys system. As you add each
component, you configure it appropriately to match the design specifications.
Add the On-Chip Memory
Processor systems require at least one memory for data and instructions. This design
example uses one 20 KB on-chip memory for both data and instructions. To add the
memory, perform the following steps:
1. On the Component Library tab (to the left of the System Contents tab), expand
Memories and Memory Controllers, expand On-Chip, and then click On-Chip
Memory (RAM or ROM).
2. Click Add. The On-Chip Memory (RAM or ROM) parameter editor appears.
Figure 1–5 shows the GUI.
3. In the Block type list, select Auto.
4. In the To t al m emory size box, type
20480 to specify a memory size of 20 KB.
1Do not change any of the other default settings.

Chapter 1: Nios II Hardware Development 1–13
Creating the Design Example
May 2011 Altera Corporation Nios II Hardware Development Tutorial
Figure 1–5 shows the On-Chip Memory (RAM or ROM) parameter editor.
5. Click Finish. You return to Qsys.
6. Click the System Contents tab. An instance of the on-chip memory appears in the
system contents table.
1For more information about on-chip memory, you can click Documentation in the
On-Chip Memory (RAM or ROM) parameter editor. This documentation feature is
available in the parameter editor for each component.
7. In the Name column of the system contents table, right-click the on-chip memory
and click Rename.
8. Type
onchip_mem and press Enter.
Figure 1–5. On-Chip Memory Parameter Editor

1–14 Chapter 1: Nios II Hardware Development
Creating the Design Example
Nios II Hardware Development Tutorial May 2011 Altera Corporation
1You must type these tutorial component names exactly as specified. Otherwise, the
tutorial programs written for this Nios II system fail in later steps. In general, it is a
good habit to give descriptive names to hardware components. Nios II programs use
these symbolic names to access the component hardware. Therefore, your choice of
component names can make Nios II programs easier to read and understand.
Add the Nios II Processor Core
In this section you add the Nios II/s core and configure it to use 2 KB of on-chip
instruction cache memory. For educational purposes, the tutorial design example uses
the Nios II/s (standard) core, which provides a balanced trade-off between
performance and resource utilization. In reality, the Nios II/s core is more powerful
than necessary for most simple control applications.
Perform the following steps to add a Nios II/s core to the system:
1. On the Component Library tab, expand Processors, and then click Nios II
Processor.
2. Click Add. The Nios II Processor parameter editor appears, displaying the Core
Nios II tab. Figure 1–6 shows the GUI.
3. Under Select a Nios II core, select Nios II/s.
4. In the Hardware multiplication type list, select None.
5. Turn off Hardware divide.
6. Click Finish. You return to the Qsys System Contents tab, and an instance of the
Nios II core appears in the system contents table. Ignore the exception and reset
vector error messages. You resolve these errors in steps 13 and 14.
7. In the Name column, right-click the Nios II processor and click Rename.
8. Type
cpu and press Enter.
9. In the Connections column, connect the
clk port of the clk_0 clock source to both
the
clk1 port of the on-chip memory and the clk port of the Nios II processor by
clicking the hollow dots on the connection line. The dots become solid indicating
the ports are connected.
10. Connect the
clk_reset port of the clk_0 clock source to both the reset1 port of the
on-chip memory and the
reset_n port of the Nios II processor.
11. Connect the
s1 port of the on-chip memory to both the data_master port and
instruction_master port of the Nios II processor.
12. Double-click the Nios II processor row of the system contents table to reopen the
Nios II Processor parameter editor.
13. Under Reset Vector, select onchip_mem.s1 in the Reset vector memory list and
type
0x0 in the Reset vector offset box.
14. Under Exception Vector, select onchip_mem.s1 in the Exception vector memory
list and type
0x20 in the Exception vector offset box.

Chapter 1: Nios II Hardware Development 1–15
Creating the Design Example
May 2011 Altera Corporation Nios II Hardware Development Tutorial
Figure 1–6 shows the Core Nios II tab of the Nios II Processor parameter editor.
15. Click the Caches and Memory Interfaces tab. Figure 1–7 shows the GUI.
16. In the Instruction cache list, select 2Kbytes.
17. In the Burst transfers list, select Disable.
18. In the Number of tightly coupled instruction master port(s) list, select None.
Figure 1–6. Nios II Parameter Editor – Core Nios II Tab

1–16 Chapter 1: Nios II Hardware Development
Creating the Design Example
Nios II Hardware Development Tutorial May 2011 Altera Corporation
Figure 1–7 shows the Caches and Memory Interfaces tab of the Nios II Processor
parameter editor.
1Do not change any settings on the Advanced Features, MMU and MPU Settings,
JTAG Debug Module, or Custom Instruction tabs.
19. Click Finish. You return to the Qsys System Contents tab.
fFor more information about configuring the Nios II core, refer to the Instantiating the
Nios II Processor in Qsys chapter of the Nios II Processor Reference Handbook.
fFor more information about connecting memory to Nios II systems, refer to the System
Design with Qsys section of Volume 1: Design and Synthesis of the Quartus II Handbook.
Figure 1–7. Nios II Parameter Editor – Caches and Memory Interfaces Tab