Freescale Semiconductor 56F827 User manual

56F800
16-bit Digital Signal Controllers
freescale.com
56F827
Evaluation Module User Manual
DSP56F827EVMUM
Rev. 2
07/2005

TABLE OF CONTENTS
Table of Contents, Rev. 2
Freescale Semiconductor i
Preface vii
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
Notation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
Definitions, Acronyms, and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x
Chapter 1
Introduction
1.1 56F827EVM Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 56F827EVM Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.3 56F827EVM Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Chapter 2
Technical Summary
2.1 56F827. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Program and Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3 SPI EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.4 RS-232 Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.5 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.6 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.7 Debug LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.8 Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.8.1 JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.8.2 Parallel JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.9 External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.10 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.11 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.12 Stereo Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.12.1 Analog Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.12.2 Digital Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.13 Daughter Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.13.1 Memory Daughter Card Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.13.2 Peripheral Daughter Card Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

56F827EVM User Manual, Rev. 2
ii Freescale Semiconductor
2.14 SCI Port #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.15 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Appendix A
56F827EVM Schematics
Appendix B
56F827EVM Bill of Material

LIST OF FIGURES
List of Figures, Rev. 2
Freescale Semiconductor iii
1-1 Block Diagram of the 56F827EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1-2 56F827EVM Jumper Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1-3 Connecting the 56F827EVM Cables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
2-1 Schematic Diagram of the External Memory Interface. . . . . . . . . . . . . . . . . . . . . . . 2-3
2-2 SPI EEPROM Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2-3 Schematic Diagram of the RS-232 Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2-4 Schematic Diagram of the Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-5 Schematic Diagram of the Debug LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-6 Block Diagram of the Parallel JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2-7 Schematic Diagram of the User Interrupt Interface. . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2-8 Schematic Diagram of the RESET Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2-9 Schematic Diagram of the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2-10 Codec Analog Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2-11 CS4218 Stereo Audio Codec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

56F827EVM User Manual, Rev. 2
iv Freescale Semiconductor

LIST OF TABLES
List of Tables, Rev. 2
Freescale Semiconductor v
1-1 56F827EVM Default Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
2-1 SPI Port Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2-2 RS-232 Serial Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2-3 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-4 JTAG Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2-5 Parallel JTAG Interface Disable Jumper Selection . . . . . . . . . . . . . . . . . . . . . . . 2-9
2-6 Parallel JTAG Interface Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2-7 Codec Sample Rate Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2-8 Memory Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2-9 Peripheral Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . 2-19
2-10 SCI Port #2 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

56F827EVM User Manual, Rev. 2
vi Freescale Semiconductor

Preface, Rev. 2
Freescale Semiconductor vii
Preface
This reference manual describes in detail the hardware on the 56F827 Evaluation Module.
Audience
This document is intended for application developers who are creating software for
devices using the 56F827 part.
Organization
This manual is organized into two chapters and two appendixes.
•Chapter 1, Introduction - provides an overview of the EVM and its features.
•Chapter 2, Technical Summary - describes in detail the 56F827 hardware.
•Appendix A, "56F827EVM Schematics" contains the schematics of the
DSP56F827EVM.
•Appendix B, 56F827EVM Bill of Material - provides a list of the materials used on the
DSP56F827EVM board.
Suggested Reading
More documentation on the 56F827 and the DSP56F827EVM kit may be found at URL:
www.freescale.com

DSP56F827EVM User Manual, Rev. 2
viii Freescale Semiconductor
Notation Conventions
This manual uses the following notational conventions:
Term or Value Symbol Examples Exceptions
Active High Signals
(Logic One)
No special symbol
attached to the 
signal name
A0
CLKO
Active Low Signals
(Logic Zero)
Noted with an
overbar in text and
in most figures
WE
OE
In schematic drawings,
Active Low Signals may be
noted by a backslash:
/WE
Hexadecimal 
Values
Begin with a “$” 
symbol
$0FF0
$80
Decimal Values No special symbol
attached to the
number
10
34
Binary Values Begin with the letter
“b” attached to the
number
b1010
b0011
Numbers Considered positive
unless specifically
noted as a negative
value
5
-10
Voltage is often shown as
positive: +3.3V
Blue Text Linkable on-line ...refer to
Figure 1-1
Bold Reference sources,
paths, emphasis
...see:
http://www.freescale.com/...

Preface, Rev. 2
Freescale Semiconductor ix
Definitions, Acronyms, and Abbreviations
Definitions, acronyms and abbreviations for terms used in this document are defined below for
reference.
Codec COder/DECoder; a part used to convert analog signals to digital (Coder)
and digital signals to analog (Decoder)
EEPROM Electrically Erasable Programmable Read Only Memory
EVM Evaluation Module; a hardware platform which allows a customer to
evaluate the silicon and develop their application
GPIO General Purpose Input and Output Port; does not share pin functionality
with any other peripheral on the chip and can only be set as an input,
output or level-sensitive interrupt input
IC Integrated Circuit
JTAG Joint Test Action Group; a bus protocol/interface used for test and debug
LQFP Low-profile Quad Flat Pack
MPIO Multi-Purpose Input/Output Port; shares package pins with other
peripherals on the chip and can function as a GPIO
OnCETM On-Chip Emulation, a debug bus and port created by Freescale to enable
designers to create a low-cost hardware interface for a professional
quality debug environment
PCB Printed Circuit Board
PLL Phase Locked Loop
RAM Random Access Memory
ROM Read-Only Memory
SCI Serial Communications Interface Port
SPI Serial Peripheral Interface Port
SRAM Static Random Access Memory
SSI Synchronous Serial Interface Port
WS Wait State

DSP56F827EVM User Manual, Rev. 2
xFreescale Semiconductor
References
The following sources were referenced to produce this manual:
[1] DSP56800 Family Manual, DSP56800FM, Freescale Semiconductor
[2] DSP56F826/827 Digital Signal Processor User’s Manual, DSP56F826_827UM,
Freescale Semiconductor
[3] DSP56F827 Technical Data, DSP56F827, Freescale Semiconductor

Introduction, Rev. 2
Freescale Semiconductor 1-1
Chapter 1
Introduction
The 56F827EVM is used to demonstrate the abilities of the 56F827 and to provide a
hardware tool allowing the development of applications that use the 56F827.
The 56F827EVM is an evaluation module board that includes a 56F827 part, 16-bit stereo
codec, external memory and a daughter card expansion interface. The daughter card
expansion connectors are for signal monitoring and user feature expandability.
The 56F827EVM is designed for the following purposes:
• Allowing new users to become familiar with the features of the 56800 architecture.
The tools and examples provided with the 56F827EVM facilitate evaluation of the
feature set and the benefits of the family.
• Serving as a platform for real-time software development. The tool suite enables
the user to develop and simulate routines, download the software to on-chip or
on-board RAM, run it, and debug it using a debugger via the JTAG/OnCETM port.
The breakpoint features of the OnCE port enable the user to easily specify complex
break conditions and to execute user-developed software at full-speed, until the
break conditions are satisfied. The ability to examine and modify all user
accessible registers, memory and peripherals through the OnCE port greatly
facilitates the task of the developer.
• Serving as a platform for hardware development. The hardware platform enables
the user to connect external hardware peripherals. The on-board peripherals can be
disabled, providing the user with the ability to reassign any and all of the
controller's peripherals. The OnCE port's unobtrusive design means that all of the
memory on the board and on the controller chip are available to the user.
1.1 56F827EVM Architecture
The 56F827EVM facilitates the evaluation of various features present in the 56F827 part.
The 56F827EVM can be used to develop real-time software and hardware products based

56F827EVM User Manual, Rev. 2
1-2 Freescale Semiconductor 
on the 56F827. The 56F827EVM provides the features necessary for a user to write and debug
software, demonstrate the functionality of that software and interface with the customer's
application-specific device(s). The 56F827EVM is flexible enough to allow a user to fully
exploit the 56F827's features to optimize the performance of his product, as shown in Figure 1-1.
56F827
RESET
MODE
Address,
Data &
Control
JTAG/OnCE
XTAL/EXTAL
SPI
SCI
SSI
GPIO
& GND
Peripheral
Daughter
Card
Connector
RESET
LOGIC
MODE
LOGIC
Program Memory
64Kx16-bit
SRAM
Memory
Daughter Card
Connector
JTAG
Connector
Parallel
JTAG
Interface
4.00MHz
Crystal
DSub
25-Pin
Data Memory
64Kx16-bit
SRAM
Debug LEDs
Stereo 16-bit
Codec
RS-232
Interface
SPI EEPROM
1M-bit
Power Supply
+2.5V, +3.3V & +5.0V
IRQ Interface
IRQ
Amp
Stereo Line Out
Headphone Jack
Stereo Line In
+2.5V, +3.3V
A/D
DSub
9-Pin
Figure 1-1. Block Diagram of the 56F827EVM
1.2 56F827EVM Configuration Jumpers
Seven jumper groups, (JG1-JG7), shown in Figure 1-2, are used to configure various features on
the 56F827EVM board. Table 1-1 describes the default jumper group settings.

JG6
DSP56F827EVM
J3
JTAG
U7
S/N
P1
Y1
U1
U2
S2
S3
S1
S4
P2
LEDS
JG5
JG2
U5
RESET
IRQB
IRQA
1
2
7
8
JG3
J2
P6
1
JG5
3
JG2
JG3
JG1
JG6
TB1
P3
P4 P5
JG4
J1
JG7
HEADPHONE
LINE
LINE
IN OUT
JG1
JG4
3
1
JG7
J3
JTAG
56F827EVM Connections
Introduction, Rev. 2
Freescale Semiconductor 1-3
Figure 1-2. 56F827EVM Jumper Reference
Table 1-1. 56F827EVM Default Jumper Options
Jumper
Group Comment Jumpers Connections
JG1 Enable on-board Parallel JTAG Host/Target Interface NC
JG2 Enable RS-232 output NC
JG3 Enable on-board SRAM 1–2
JG4 Use on-board EXTAL crystal input for controller oscillator 2–3
JG5 Use on-board XTAL crystal input for controller oscillator 1–2
JG6 Selects controller’s Mode 0 operation upon exit from reset 1-2
JG7 Enable SPI EEPROM 1–2, 3–4, 5–6 & 7–8
1.3 56F827EVM Connections
An interconnection diagram is shown in Figure 1-3 for connecting the PC and the external
+12.0V DC power supply or external +5.0V DC lab power supply to the 56F827EVM board.

PC-compatible
Cable
Computer
Parallel Extension
56F827EVM
External
+12.0V
Power
P2
P1
Connect cable
to Parallel/Printer port
with 2.1mm,
receptacle
connector
+5.0V
Lab
Supply
TB1
or
56F827EVM User Manual, Rev. 2
1-4 Freescale Semiconductor 
Figure 1-3. Connecting the 56F827EVM Cables
Perform the following steps to connect the 56F827EVM cables:
1. Connect the parallel extension cable to the parallel port of the host computer.
2. Connect the other end of the parallel extension cable to P2, shown in Figure 1-3, on the
56F827EVM board. This provides the connection which allows the host computer to
control the board.
3. Make sure that the external +12.0V DC 1.2A switching power supply or the external
+5.0V DC 1.0A lab power supply is not plugged into a 120V AC power source.
4. Connect the 2.1mm output power plug from the external switching power supply into P1,
shown in Figure 1-3, on the 56F827EVM board. Optionally, attach an external +5.0V DC
lab power supply via the 2-pin terminal block, TB1.
5. Apply power to the external power supply. The green Power-On LED, LED7, will
illuminate when power is correctly applied.

Technical Summary, Rev. 2
Freescale Semiconductor 2-1
Chapter 2
Technical Summary
The 56F827EVM is designed as a versatile controller development card for developing
real-time software and hardware products to support a new generation of applications in
digital and wireless messaging, digital answering machines, feature phones, modems, and
digital cameras. The power of the 16-bit 56F827 controller, combined with the on-board
64K u16-bit external program static RAM (SRAM), 64K u16-bit external data SRAM,
RS-232 interface, stereo 16-bit codec interface, Daughter Card Expansion interface and
parallel JTAG interface, makes the 56F827EVM ideal for developing and implementing
many audio and voice algorithms, as well as for learning the architecture and instruction
set of the 56F827 processor.
The main features of the 56F827EVM, with board and schematic reference designators
include:
• 56F827 16-bit +2.5V/+3.3V controller operating at 80MHz [U1]
• External fast static RAM (FSRAM) memory [U2], configured as:
— 64Ku16 bits of program memory with 0 wait states at 70MHz
— 64Ku16 bits of data memory with 0 wait states at 70MHz
• 1M-bit Serial EEPROM [U4]
• 4.00MHz crystal oscillator for controller frequency generation [Y1]
• Optional external oscillator frequency input connector [JG4 and JG5]
• Joint Test Action Group (JTAG) port interface connector for an external debug
Host Target Interface [J3]
• On-board Parallel JTAG Host Target Interface, with a connector for a PC printer
port cable [P2]
• RS-232 interface for easy connection to a host processor [U3 and P3]
• 16-bit stereo codec interface [U5, P4 and P5]
• Stereo headphone interface [U6 and P6]

56F827EVM User Manual, Rev. 2
2-2 Freescale Semiconductor 
• Codec sample rate selector [S4]
• Peripheral Daughter Card Expansion Connector, to allow the user to connect his own SCI,
SSI, SPI or GPIO-compatible peripheral to the controller[J2]
• Memory Daughter Card Expansion Connector, to allow the user to connect his own
memory or memory device to the controller[J1]
• On-board power regulation from an external +12V DC-supplied power input [P1]
• On-board power regulation from an optional +5V DC-supplied power input [TB1]
• Light Emitting Diode (LED) power indicator [LED7]
• Six on-board real-time user debugging LEDs [LED1-6]
• Manual RESET push-button [S1]
• Manual interrupt push-button for IRQA [S2]
• Manual interrupt push-button for IRQB [S3]
2.1 56F827
The 56F827EVM uses a Freescale DSP56F827FG80 part, designated as U1 on the board and in
the schematics. This part will operate at a maximum speed of 80MHz. A full description of the
56F827, including functionality and user information, is provided in these documents:
•DSP56F827 Technical Data, (DSP56F827):Provides features list and specifications
including signal descriptions, DC power requirements, AC timing requirements and
available packaging.
•DSP56F826/827 16-Bit Digital Signal Processor User’s Manual, (DSP56F826_827UM):
Provides an overview description of the controller and detailed information about the
on-chip components including the memory and I/O maps, peripheral functionality, and
control/status register descriptions for each subsystem.
• DSP56800 Family Manual, (DSP56800FM): Provides a detailed description of the core
processor, including internal status and control registers and a detailed description of the
family instruction set.
Refer to these documents for detailed information about chip functionality and operation. They
can be found on this URL:
www.freescale.com

Program and Data Memory
Technical Summary, Rev. 2
Freescale Semiconductor 2-3
2.2 Program and Data Memory
The 56F827EVM uses one bank of 128Ku16-bit Fast Static RAM (GSI GS72116, labelled U2)
for external memory expansion; see the FSRAM schematic diagram in Figure 2-1. This physical
memory bank is split into two logical memory banks of 64Kx16-bits: one for program memory
and the other for data memory. By using the controller’s program strobe, PS, signal line along
with the memory chip’s A0 signal line, half of the memory chip is selected when program
memory accesses are requested and the other half of the memory chip is selected when data
memory access are requested. This memory bank will operate with zero wait-state accesses while
the 56F827 is running at 70MHz. However, when running at 80MHz, the memory bank operates
with four wait-state accesses. This memory bank can be disabled by removing the jumper at JG3.
56F827 GS72116
A0-A15
PS
D0-D15
RD
WR
A1-A16
A0
DQ0-DQ15
OE
WE
CE
1 2
JG3
+3.3V
Jumper Pin 1-2:
Enable SRAM
Jumper Removed:
Disable SRAM
Figure 2-1. Schematic Diagram of the External Memory Interface

56F827EVM User Manual, Rev. 2
2-4 Freescale Semiconductor 
2.3 SPI EEPROM Memory
A 1M-bit +3.3V SPI serial EEPROM Memory, Atmel AT45DB011-SC, is provided on the
56F827EVM, reference Figure 2-2. This memory connects directly to the SPI Port through a
header on the 56F827. It can be used to load program code and data into the 56F827’s internal or
external memory spaces. A jumper block is provided, JG7, to allow the user to disconnect the
on-board SPI EEPROM from the SPI port and allow him to connect his own SPI port peripheral.
The header details are shown in Table 2-1.
56F827
MOSI
MISO
SCLK
GPIOF7
Serial EEPROM
SDI
SDO
SCK
CS
EEPROM Enable
(SPI Port Connector)
Figure 2-2. SPI EEPROM Memory Block Diagram
Table 2-1. SPI Port Connector Description
JG7
Pin # Signal Pin # Signal
1SS/
GPIO7 2 CS
3 MISO 4 SDO
5 MOSI 6 SDI
7 SCLK 8 SCK