Altera Cyclone V Application guide

Cyclone V Device Handbook
Volume 1: Device Interfaces and Integration
101 Innovation Drive
San Jose, CA 95134
www.altera.com
CV-5V2
2014.01.10
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Contents
Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices...........1-1
LAB ...............................................................................................................................................................1-1
MLAB ................................................................................................................................................1-2
Local and Direct Link Interconnects ............................................................................................1-3
LAB Control Signals........................................................................................................................1-4
ALM Resources ...............................................................................................................................1-5
ALM Output ....................................................................................................................................1-6
ALM Operating Modes ..............................................................................................................................1-7
Normal Mode ..................................................................................................................................1-8
Extended LUT Mode ......................................................................................................................1-8
Arithmetic Mode .............................................................................................................................1-8
Shared Arithmetic Mode ................................................................................................................1-9
Document Revision History.....................................................................................................................1-11
Embedded Memory Blocks in Cyclone V Devices..............................................2-1
Types of Embedded Memory.....................................................................................................................2-1
Embedded Memory Capacity in Cyclone V Devices..................................................................2-1
Embedded Memory Design Guidelines for Cyclone V Devices............................................................2-2
Guideline: Consider the Memory Block Selection......................................................................2-2
Guideline: Implement External Conflict Resolution..................................................................2-3
Guideline: Customize Read-During-Write Behavior.................................................................2-3
Guideline: Consider Power-Up State and Memory Initialization............................................2-6
Guideline: Control Clocking to Reduce Power Consumption..................................................2-7
Embedded Memory Features.....................................................................................................................2-7
Embedded Memory Configurations.............................................................................................2-8
Mixed-Width Port Configurations................................................................................................2-9
Embedded Memory Modes......................................................................................................................2-10
Embedded Memory Clocking Modes.....................................................................................................2-11
Clocking Modes for Each Memory Mode..................................................................................2-11
Asynchronous Clears in Clocking Modes..................................................................................2-12
Output Read Data in Simultaneous Read/Write.......................................................................2-12
Independent Clock Enables in Clocking Modes.......................................................................2-13
Parity Bit in Memory Blocks....................................................................................................................2-13
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Cyclone V Device Handbook Volume 1: Device Interfaces and Integration
TOC-2

Byte Enable in Embedded Memory Blocks............................................................................................2-13
Byte Enable Controls in Memory Blocks....................................................................................2-13
Data Byte Output...........................................................................................................................2-14
RAM Blocks Operations...............................................................................................................2-15
Memory Blocks Packed Mode Support..................................................................................................2-15
Memory Blocks Address Clock Enable Support....................................................................................2-15
Document Revision History.....................................................................................................................2-17
Variable Precision DSP Blocks in Cyclone V Devices........................................3-1
Features.........................................................................................................................................................3-1
Supported Operational Modes in Cyclone V Devices............................................................................3-2
Resources.......................................................................................................................................................3-3
Design Considerations................................................................................................................................3-4
Operational Modes..........................................................................................................................3-4
Internal Coefficient and Pre-Adder...............................................................................................3-4
Accumulator.....................................................................................................................................3-4
Chainout Adder................................................................................................................................3-4
Block Architecture.......................................................................................................................................3-5
Input Register Bank.........................................................................................................................3-6
Pre-Adder..........................................................................................................................................3-8
Internal Coefficient..........................................................................................................................3-8
Multipliers.........................................................................................................................................3-8
Adder.................................................................................................................................................3-9
Accumulator and Chainout Adder................................................................................................3-9
Systolic Registers............................................................................................................................3-10
Double Accumulation Register....................................................................................................3-10
Output Register Bank....................................................................................................................3-10
Operational Mode Descriptions..............................................................................................................3-10
Independent Multiplier Mode.....................................................................................................3-11
Independent Complex Multiplier Mode....................................................................................3-13
Multiplier Adder Sum Mode........................................................................................................3-15
18 x 18 Multiplication Summed with 36-Bit Input Mode........................................................3-15
Systolic FIR Mode..........................................................................................................................3-15
Document Revision History.....................................................................................................................3-18
Clock Networks and PLLs in Cyclone V Devices................................................4-1
Clock Networks............................................................................................................................................4-1
Clock Resources in Cyclone V Devices.........................................................................................4-2
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TOC-3
Cyclone V Device Handbook Volume 1: Device Interfaces and Integration

Types of Clock Networks................................................................................................................4-3
Clock Sources Per Quadrant..........................................................................................................4-7
Types of Clock Regions...................................................................................................................4-8
Clock Network Sources...................................................................................................................4-9
Clock Output Connections...........................................................................................................4-11
Clock Control Block......................................................................................................................4-11
Clock Power Down........................................................................................................................4-14
Clock Enable Signals......................................................................................................................4-14
Cyclone V PLLs..........................................................................................................................................4-16
PLL Physical Counters in Cyclone V Devices............................................................................4-16
PLL Locations in Cyclone V Devices..........................................................................................4-17
PLL Migration Guidelines ...........................................................................................................4-22
Fractional PLL Architecture.........................................................................................................4-22
PLL Cascading................................................................................................................................4-23
PLL External Clock I/O Pins........................................................................................................4-23
PLL Control Signals.......................................................................................................................4-24
Clock Feedback Modes..................................................................................................................4-25
Clock Multiplication and Division..............................................................................................4-31
Programmable Phase Shift............................................................................................................4-32
Programmable Duty Cycle...........................................................................................................4-32
Clock Switchover...........................................................................................................................4-32
PLL Reconfiguration and Dynamic Phase Shift........................................................................4-37
Document Revision History.....................................................................................................................4-38
I/O Features in Cyclone V Devices......................................................................5-1
I/O Resources Per Package for Cyclone V Devices.................................................................................5-1
I/O Vertical Migration for Cyclone V Devices........................................................................................5-4
Verifying Pin Migration Compatibility........................................................................................5-5
I/O Standards Support in Cyclone V Devices..........................................................................................5-5
I/O Standards Support for FPGA I/O in Cyclone V Devices....................................................5-5
I/O Standards Support for HPS I/O in Cyclone V Devices........................................................5-7
I/O Standards Voltage Levels in Cyclone V Devices...................................................................5-8
MultiVolt I/O Interface in Cyclone V Devices..........................................................................5-10
I/O Design Guidelines for Cyclone V Devices.......................................................................................5-11
Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards...........................5-11
PLLs and Clocking.........................................................................................................................5-12
LVDS Interface with External PLL Mode...................................................................................5-15
Guideline: Use the Same VCCPD for All I/O Banks in a Group...............................................5-17
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Cyclone V Device Handbook Volume 1: Device Interfaces and Integration
TOC-4

Guideline: Ensure Compatible VCCIO and VCCPD Voltage in the Same Bank......................5-18
Guideline: VREF Pin Restrictions.................................................................................................5-18
Guideline: Observe Device Absolute Maximum Rating for 3.3 V Interfacing......................5-18
Guideline: Adhere to the LVDS I/O Restrictions and Differential Pad Placement
Rules...........................................................................................................................................5-19
I/O Banks Locations in Cyclone V Devices............................................................................................5-19
I/O Banks Groups in Cyclone V Devices...............................................................................................5-21
Modular I/O Banks for Cyclone V E Devices............................................................................5-22
Modular I/O Banks for Cyclone V GX Devices.........................................................................5-23
Modular I/O Banks for Cyclone V GT Devices.........................................................................5-24
Modular I/O Banks for Cyclone V SE Devices..........................................................................5-25
Modular I/O Banks for Cyclone V SX Devices..........................................................................5-26
Modular I/O Banks for Cyclone V ST Devices..........................................................................5-27
I/O Element Structure in Cyclone V Devices........................................................................................5-27
I/O Buffer and Registers in Cyclone V Devices.........................................................................5-27
Programmable IOE Features in Cyclone V Devices.............................................................................5-29
Programmable Current Strength.................................................................................................5-30
Programmable Output Slew-Rate Control.................................................................................5-31
Programmable IOE Delay.............................................................................................................5-31
Programmable Output Buffer Delay...........................................................................................5-31
Programmable Pre-Emphasis......................................................................................................5-32
Programmable Differential Output Voltage..............................................................................5-32
I/O Pins Features for Cyclone V Devices...............................................................................................5-33
Open-Drain Output.......................................................................................................................5-33
Bus-Hold Circuitry........................................................................................................................5-33
Pull-up Resistor..............................................................................................................................5-34
On-Chip I/O Termination in Cyclone V Devices.................................................................................5-34
RSOCT without Calibration in Cyclone V Devices..................................................................5-35
RSOCT with Calibration in Cyclone V Devices........................................................................5-36
RTOCT with Calibration in Cyclone V Devices.......................................................................5-38
Dynamic OCT in Cyclone V Devices..........................................................................................5-40
LVDS Input RDOCT in Cyclone V Devices..............................................................................5-41
OCT Calibration Block in Cyclone V Devices...........................................................................5-42
External I/O Termination for Cyclone V Devices.................................................................................5-44
Single-ended I/O Termination.....................................................................................................5-45
Differential I/O Termination.......................................................................................................5-47
Dedicated High-Speed Circuitries...........................................................................................................5-52
High-Speed Differential I/O Locations.......................................................................................5-52
LVDS SERDES Circuitry..............................................................................................................5-54
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TOC-5
Cyclone V Device Handbook Volume 1: Device Interfaces and Integration

True LVDS Buffers in Cyclone V Devices..................................................................................5-55
Emulated LVDS Buffers in Cyclone V Devices.........................................................................5-63
Differential Transmitter in Cyclone V Devices.....................................................................................5-63
Transmitter Blocks.........................................................................................................................5-63
Serializer Bypass for DDR and SDR Operations.......................................................................5-64
Differential Receiver in Cyclone V Devices...........................................................................................5-65
Receiver Blocks in Cyclone V Devices........................................................................................5-65
Receiver Mode in Cyclone V Devices.........................................................................................5-67
Receiver Clocking for Cyclone V Devices..................................................................................5-68
Differential I/O Termination for Cyclone V Devices...............................................................5-68
Source-Synchronous Timing Budget......................................................................................................5-69
Differential Data Orientation.......................................................................................................5-69
Differential I/O Bit Position.........................................................................................................5-70
Transmitter Channel-to-Channel Skew.....................................................................................5-71
Receiver Skew Margin for LVDS Mode......................................................................................5-71
Document Revision History.....................................................................................................................5-73
External Memory Interfaces in Cyclone V Devices............................................6-1
External Memory Performance..................................................................................................................6-2
HPS External Memory Performance.........................................................................................................6-2
Memory Interface Pin Support in Cyclone V Devices............................................................................6-2
Guideline: Using DQ/DQS Pins....................................................................................................6-3
DQ/DQS Bus Mode Pins for Cyclone V Devices........................................................................6-3
DQ/DQS Groups in Cyclone V E..................................................................................................6-5
DQ/DQS Groups in Cyclone V GX...............................................................................................6-7
DQ/DQS Groups in Cyclone V GT...............................................................................................6-9
DQ/DQS Groups in Cyclone V SE..............................................................................................6-11
DQ/DQS Groups in Cyclone V SX..............................................................................................6-11
DQ/DQS Groups in Cyclone V ST..............................................................................................6-12
External Memory Interface Features in Cyclone V Devices................................................................6-12
UniPHY IP......................................................................................................................................6-12
External Memory Interface Datapath.........................................................................................6-13
DQS Phase-Shift Circuitry............................................................................................................6-13
PHY Clock (PHYCLK) Networks...............................................................................................6-21
DQS Logic Block............................................................................................................................6-24
Dynamic OCT Control.................................................................................................................6-26
IOE Registers..................................................................................................................................6-26
Delay Chains...................................................................................................................................6-28
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Cyclone V Device Handbook Volume 1: Device Interfaces and Integration
TOC-6

I/O and DQS Configuration Blocks............................................................................................6-29
Hard Memory Controller.........................................................................................................................6-30
Features of the Hard Memory Controller..................................................................................6-30
Multi-Port Front End....................................................................................................................6-32
Bonding Support............................................................................................................................6-33
Hard Memory Controller Width for Cyclone V E....................................................................6-35
Hard Memory Controller Width for Cyclone V GX................................................................6-36
Hard Memory Controller Width for Cyclone V GT................................................................6-37
Hard Memory Controller Width for Cyclone V SE..................................................................6-37
Hard Memory Controller Width for Cyclone V SX.................................................................6-38
Hard Memory Controller Width for Cyclone V ST..................................................................6-38
Document Revision History.....................................................................................................................6-39
Configuration, Design Security, and Remote System Upgrades in Cyclone V
Devices.............................................................................................................7-1
Enhanced Configuration and Configuration via Protocol.....................................................................7-1
MSEL Pin Settings........................................................................................................................................7-2
Configuration Sequence..............................................................................................................................7-3
Power Up...........................................................................................................................................7-4
Reset...................................................................................................................................................7-5
Configuration...................................................................................................................................7-5
Configuration Error Handling.......................................................................................................7-5
Initialization......................................................................................................................................7-6
User Mode.........................................................................................................................................7-6
Device Configuration Pins..........................................................................................................................7-6
Configuration Pin Options in the Quartus II Software..............................................................7-8
Fast Passive Parallel Configuration...........................................................................................................7-9
Fast Passive Parallel Single-Device Configuration......................................................................7-9
Fast Passive Parallel Multi-Device Configuration.....................................................................7-10
Active Serial Configuration......................................................................................................................7-12
DATA Clock (DCLK)....................................................................................................................7-12
Active Serial Single-Device Configuration.................................................................................7-13
Active Serial Multi-Device Configuration..................................................................................7-14
Estimating the Active Serial Configuration Time.....................................................................7-15
Using EPCS and EPCQ Devices..............................................................................................................7-15
Controlling EPCS and EPCQ Devices........................................................................................7-16
Trace Length and Loading............................................................................................................7-16
Programming EPCS and EPCQ Devices....................................................................................7-16
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Cyclone V Device Handbook Volume 1: Device Interfaces and Integration

Passive Serial Configuration.....................................................................................................................7-20
Passive Serial Single-Device Configuration Using an External Host.....................................7-21
Passive Serial Single-Device Configuration Using an Altera Download Cable....................7-21
Passive Serial Multi-Device Configuration................................................................................7-22
JTAG Configuration..................................................................................................................................7-24
JTAG Single-Device Configuration.............................................................................................7-25
JTAG Multi-Device Configuration.............................................................................................7-27
CONFIG_IO JTAG Instruction...................................................................................................7-27
Configuration Data Compression...........................................................................................................7-28
Enabling Compression Before Design Compilation.................................................................7-28
Enabling Compression After Design Compilation...................................................................7-28
Using Compression in Multi-Device Configuration................................................................7-28
Remote System Upgrades.........................................................................................................................7-29
Configuration Images....................................................................................................................7-30
Configuration Sequence in the Remote Update Mode.............................................................7-30
Remote System Upgrade Circuitry..............................................................................................7-31
Enabling Remote System Upgrade Circuitry.............................................................................7-31
Remote System Upgrade Registers..............................................................................................7-32
Remote System Upgrade State Machine.....................................................................................7-34
User Watchdog Timer...................................................................................................................7-34
Design Security...........................................................................................................................................7-34
ALTCHIP_ID Megafunction.......................................................................................................7-35
JTAG Secure Mode........................................................................................................................7-35
Security Key Types.........................................................................................................................7-36
Security Modes...............................................................................................................................7-37
Design Security Implementation Steps.......................................................................................7-37
Document Revision History.....................................................................................................................7-38
SEU Mitigation for Cyclone V Devices...............................................................8-1
Error Detection Features.............................................................................................................................8-1
Configuration Error Detection..................................................................................................................8-1
User Mode Error Detection........................................................................................................................8-1
Specifications................................................................................................................................................8-2
Minimum EMR Update Interval...................................................................................................8-2
Error Detection Frequency.............................................................................................................8-3
CRC Calculation Time....................................................................................................................8-3
Using Error Detection Features in User Mode........................................................................................8-4
Enabling Error Detection................................................................................................................8-4
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Cyclone V Device Handbook Volume 1: Device Interfaces and Integration
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CRC_ERROR Pin.............................................................................................................................8-5
Error Detection Registers................................................................................................................8-5
Error Detection Process..................................................................................................................8-7
Testing the Error Detection Block.................................................................................................8-8
Document Revision History.......................................................................................................................8-9
JTAG Boundary-Scan Testing in Cyclone V Devices.........................................9-1
BST Operation Control ..............................................................................................................................9-1
IDCODE ...........................................................................................................................................9-1
Supported JTAG Instruction .........................................................................................................9-3
JTAG Secure Mode .........................................................................................................................9-6
JTAG Private Instruction ...............................................................................................................9-6
I/O Voltage for JTAG Operation ..............................................................................................................9-7
Performing BST ...........................................................................................................................................9-7
Enabling and Disabling IEEE Std. 1149.1 BST Circuitry ......................................................................9-8
Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing.......................................................................9-9
IEEE Std. 1149.1 Boundary-Scan Register ...............................................................................................9-9
Boundary-Scan Cells of a Cyclone V Device I/O Pin...............................................................9-10
Document Revision History.....................................................................................................................9-12
Power Management in Cyclone V Devices.......................................................10-1
Power Consumption..................................................................................................................................10-1
Dynamic Power Equation.............................................................................................................10-1
Hot-Socketing Feature..............................................................................................................................10-2
Hot-Socketing Implementation...............................................................................................................10-2
Power-Up Sequence..................................................................................................................................10-4
Power-On Reset Circuitry........................................................................................................................10-5
Power Supplies Monitored and Not Monitored by the POR Circuitry.................................10-7
Document Revision History.....................................................................................................................10-7
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TOC-9
Cyclone V Device Handbook Volume 1: Device Interfaces and Integration

1
Logic Array Blocks and Adaptive Logic Modules
in Cyclone V Devices
2014.01.10
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This chapter describes the features of the logic array block (LAB) in the Cyclone®V core fabric.
The LAB is composed of basic building blocks known as adaptive logic modules (ALMs) that you can
configure to implement logic functions, arithmetic functions, and register functions.
You can use a quarter of the available LABs in the Cyclone V devices as a memory LAB (MLAB).
The Quartus®II software and other supported third-party synthesis tools, in conjunction with parameterized
functions such as the library of parameterized modules (LPM), automatically choose the appropriate mode
for common functions such as counters, adders, subtractors, and arithmetic functions.
This chapter contains the following sections:
•LAB
•ALM Operating Modes
Related Information
Cyclone V Device Handbook: Known Issues
Lists the planned updates to the Cyclone V Device Handbook chapters.
LAB
The LABs are configurable logic blocks that consist of a group of logic resources. Each LAB contains dedicated
logic for driving control signals to its ALMs.
MLAB is a superset of the LAB and includes all the LAB features.
ISO
9001:2008
Registered
©2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words
and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
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101 Innovation Drive, San Jose, CA 95134

Figure 1-1: LAB Structure and Interconnects Overview in Cyclone V Devices
This figure shows an overview of the Cyclone V LAB and MLAB structure with the LAB interconnects.
Fast Local Interconnect Is Driven
from Either Sides by Column Interconnect
and LABs, and from Above by Row Interconnect
Column Interconnects of
Variable Speed and Length
Row Interconnects of
Variable Speed and Length
MLABLABLocal Interconnect
ALMs
C2/C4 C12
R14
R3/R6
Direct-Link
Interconnect from
Adjacent Block
Direct-Link
Interconnect to
Adjacent Block
Direct-Link
Interconnect to
Adjacent Block
Direct-Link
Interconnect from
Adjacent Block
Connects to adjacent
LABs, memory blocks,
digital signal processing
(DSP) blocks, or I/O
element (IOE) outputs.
MLAB
Each MLAB supports a maximum of 640 bits of simple dual-port SRAM.
You can configure each ALM in an MLAB as a 32 x 2 memory block, resulting in a configuration of 32 x 20
simple dual-port SRAM block.
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MLAB
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Figure 1-2: LAB and MLAB Structure for Cyclone V Devices
MLAB LAB
LUT-Based-32 x 2
Simple Dual-Port SRAM
LUT-Based-32 x 2
Simple Dual-Port SRAM
LUT-Based-32 x 2
Simple Dual-Port SRAM
LUT-Based-32 x 2
Simple Dual-Port SRAM
LUT-Based-32 x 2
Simple Dual-Port SRAM
LUT-Based-32 x 2
Simple Dual-Port SRAM
LUT-Based-32 x 2
Simple Dual-Port SRAM
LUT-Based-32 x 2
Simple Dual-Port SRAM
LUT-Based-32 x 2
Simple Dual-Port SRAM
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
ALM
ALM
ALM
ALM
ALM
ALM
ALM
ALM
ALM
LAB Control Block
LAB Control Block
You can use an MLAB
ALM as a regular LAB
ALM or configure it as a
dual-port SRAM.
You can use an MLAB
ALM as a regular LAB
ALM or configure it as a
dual-port SRAM.
Local and Direct Link Interconnects
Each LAB can drive 30 ALMs through fast-local and direct-link interconnects. Ten ALMs are in any given
LAB and ten ALMs are in each of the adjacent LABs.
The local interconnect can drive ALMs in the same LAB using column and row interconnects and ALM
outputs in the same LAB.
Neighboring LABs, MLABs, M10K blocks, or digital signal processing (DSP) blocks from the left or right
can also drive the LAB’s local interconnect using the direct link connection.
The direct link connection feature minimizes the use of row and column interconnects, providing higher
performance and flexibility.
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Local and Direct Link Interconnects
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Figure 1-3: LAB Fast Local and Direct Link Interconnects for Cyclone V Devices
MLAB
ALMs ALMs
LAB
Fast Local
Interconnect
Direct Link Interconnect from
Left LAB, Memory Block,
DSP Block, or IOE Output
Direct Link
Interconnect
to Left
Direct Link
Interconnect
to Right
Direct Link Interconnect from
Right LAB, Memory Block,
DSP Block, or IOE Output
LAB Control Signals
Each LAB contains dedicated logic for driving the control signals to its ALMs, and has two unique clock
sources and three clock enable signals.
The LAB control block generates up to three clocks using the two clock sources and three clock enable
signals. Each clock and the clock enable signals are linked.
De-asserting the clock enable signal turns off the corresponding LAB-wide clock.
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Figure 1-4: LAB-Wide Control Signals for Cyclone V Devices
This figure shows the clock sources and clock enable signals in a LAB.
Dedicated Row
LAB Clocks
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclk2 syncload
labclkena0
or asyncload
or labpreset
labclk0 labclk1 labclr1
labclkena1 labclkena2 labclr0 synclr
6
6
6
There are two unique
clock signals per LAB.
ALM Resources
One ALM contains four programmable registers. Each register has the following ports:
•Data
•Clock
•Synchronous and asynchronous clear
•Synchronous load
Global signals, general-purpose I/O (GPIO) pins, or any internal logic can drive the clock and clear control
signals of an ALM register.
GPIO pins or internal logic drives the clock enable signal.
For combinational functions, the registers are bypassed and the output of the look-up table (LUT) drives
directly to the outputs of an ALM.
The Quartus II software automatically configures the ALMs for optimized performance.Note:
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ALM Resources
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Figure 1-5: ALM High-Level Block Diagram for Cyclone V Devices
datac
datad
datae1
dataf1
adder1
datae0
dataf0
dataa
datab
carry_in
carry_out
Combinational/
Memory ALUT0
6-Input
LUT
6-Input
LUT
shared_arith_out
shared_arith_in
Combinational/
Memory ALUT1
adder0
reg0
labclk
reg1
reg2
reg3
D Q
D Q
D Q
D Q
To General or
Local Routing
ALM Output
The general routing outputs in each ALM drive the local, row, and column routing resources. Two ALM
outputs can drive column, row, or direct link routing connections, and one of these ALM outputs can also
drive local interconnect resources.
The LUT, adder, or register output can drive the ALM outputs. The LUT or adder can drive one output
while the register drives another output.
Register packing improves device utilization by allowing unrelated register and combinational logic to be
packed into a single ALM. Another mechanism to improve fitting is to allow the register output to feed back
into the look-up table (LUT) of the same ALM so that the register is packed with its own fan-out LUT. The
ALM can also drive out registered and unregistered versions of the LUT or adder output.
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Figure 1-6: ALM Connection Details for Cyclone V Devices
DQ
CLR
DQ
CLR
Row, Column
Direct Link Routing
DQ
CLR
Local
Interconnect
Local
Interconnect
DQ
CLR
carry_out
GND
VCC
aclr[1:0]
sclr
syncload
clk[2:0]
carry_in
+
shared_arith_out
shared_arith_in
4-Input
LUT
4-Input
LUT
3-Input
LUT
3-Input
LUT
3-Input
LUT
3-Input
LUT
+
dataf0
datae0
dataa
datab
datac1
datae1
dataf1
datac0
Row, Column
Direct Link Routing
Row, Column
Direct Link Routing
Row, Column
Direct Link Routing
ALM Operating Modes
The Cyclone V ALM operates in any of the following modes:
•Normal mode
•Extended LUT mode
•Arithmetic mode
•Shared arithmetic mode
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ALM Operating Modes
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Normal Mode
Normal mode allows two functions to be implemented in one Cyclone V ALM, or a single function of up
to six inputs.
Up to eight data inputs from the LAB local interconnect are inputs to the combinational logic.
The ALM can support certain combinations of completely independent functions and various combinations
of functions that have common inputs.
Extended LUT Mode
In this mode, if the 7-input function is unregistered, the unused eighth input is available for register packing.
Functions that fit into the template, as shown in the following figure, often appear in designs as “if-else”
statements in Verilog HDL or VHDL code.
Figure 1-7: Template for Supported 7-Input Functions in Extended LUT Mode for Cyclone V Devices
datae0
combout0
5-Input
LUT
5-Input
LUT
datac
dataa
datab
datad
dataf0
datae1
dataf1
D Q
reg0
This input is available
for register packing.
To General or
Local Routing
Arithmetic Mode
The ALM in arithmetic mode uses two sets of two 4-input LUTs along with two dedicated full adders.
The dedicated adders allow the LUTs to perform pre-adder logic; therefore, each adder can add the output
of two 4-input functions.
The ALM supports simultaneous use of the adder’s carry output along with combinational logic outputs.
The adder output is ignored in this operation.
Using the adder with the combinational logic output provides resource savings of up to 50% for functions
that can use this mode.
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Normal Mode
1-8 2014.01.10

Figure 1-8: ALM in Arithmetic Mode for Cyclone V Devices
datae0 carry_in
carry_out
dataa
datab
datac
datad
datae1
4-Input
LUT
4-Input
LUT
4-Input
LUT
4-Input
LUT
adder1
dataf0
dataf1
adder0
reg1 To General or
Local Routing
reg0
reg3
reg2
Carry Chain
The carry chain provides a fast carry function between the dedicated adders in arithmetic or shared arithmetic
mode.
The two-bit carry select feature in Cyclone V devices halves the propagation delay of carry chains within
the ALM. Carry chains can begin in either the first ALM or the fifth ALM in a LAB. The final carry-out
signal is routed to an ALM, where it is fed to local, row, or column interconnects.
To avoid routing congestion in one small area of the device when a high fan-in arithmetic function is
implemented, the LAB can support carry chains that only use either the top half or bottom half of the LAB
before connecting to the next LAB. This leaves the other half of the ALMs in the LAB available for
implementing narrower fan-in functions in normal mode. Carry chains that use the top five ALMs in the
first LAB carry into the top half of the ALMs in the next LAB in the column. Carry chains that use the bottom
five ALMs in the first LAB carry into the bottom half of the ALMs in the next LAB within the column. You
can bypass the top-half of the LAB columns and bottom-half of the MLAB columns.
The Quartus II Compiler creates carry chains longer than 20 ALMs (10 ALMs in arithmetic or shared
arithmetic mode) by linking LABs together automatically. For enhanced fitting, a long carry chain runs
vertically, allowing fast horizontal connections to the TriMatrix memory and DSP blocks. A carry chain can
continue as far as a full column.
Shared Arithmetic Mode
The ALM in shared arithmetic mode can implement a 3-input add in the ALM.
This mode configures the ALM with four 4-input LUTs. Each LUT either computes the sum of three inputs
or the carry of three inputs. The output of the carry computation is fed to the next adder using a dedicated
connection called the shared arithmetic chain.
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Shared Arithmetic Mode
CV-52001
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Figure 1-9: ALM in Shared Arithmetic Mode for Cyclone V Devices
datae0
carry_in
shared_arith_in
shared_arith_out
carry_out
dataa
datab
datac
datad
datae1
4-Input
LUT
4-Input
LUT
4-Input
LUT
4-Input
LUT
labclk
reg1 To General or
Local Routing
reg0
reg3
reg2
Shared Arithmetic Chain
The shared arithmetic chain available in enhanced arithmetic mode allows the ALM to implement a 3-input
adder. This significantly reduces the resources necessary to implement large adder trees or correlator
functions.
The shared arithmetic chain can begin in either the first or sixth ALM in a LAB.
Similar to carry chains, the top and bottom half of the shared arithmetic chains in alternate LAB columns
can be bypassed. This capability allows the shared arithmetic chain to cascade through half of the ALMs in
an LAB while leaving the other half available for narrower fan-in functionality. In every LAB, the column
is top-half bypassable; while in MLAB, columns are bottom-half bypassable.
The Quartus II Compiler creates shared arithmetic chains longer than 20 ALMs (10 ALMs in arithmetic or
shared arithmetic mode) by linking LABs together automatically. To enhance fitting, a long shared arithmetic
chain runs vertically, allowing fast horizontal connections to the TriMatrix memory and DSP blocks. A
shared arithmetic chain can continue as far as a full column.
Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices
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Shared Arithmetic Mode
1-10 2014.01.10

Document Revision History
ChangesVersionDate
Added multiplexers for the bypass paths and register outputs in the
following diagrams:
•ALM High-Level Block Diagram for Cyclone V Devices
•Template for Supported 7-Input Functions in Extended LUT Mode for
Cyclone V Devices
•ALM in Arithmetic Mode for Cyclone V Devices
•ALM in Shared Arithmetic Mode for Cyclone V Devices
2014.01.10January 2014
•Added link to the known document issues in the Knowledge Base.
•Removed register chain outputs information in ALM output section.
•Removed reg_chain_in and reg_chain_out ports in ALM high-level
block diagram and ALM connection details diagram.
2013.05.06May 2013
Reorganized content and updated template.2012.12.28December 2012
Updated for the Quartus II software v12.0 release:
•Restructured chapter.
•Updated Figure 1–6.
2.0June 2012
Minor text edits.1.1November 2011
Initial release.1.0October 2011
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Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices
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Document Revision History
CV-52001
2014.01.10