Altera Cyclone V Use and care manual

Cyclone V Hard Processor System
Technical Reference Manual
Last updated for Quartus Prime Design Suite: 16.1
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2016.10.28
101 Innovation Drive
San Jose, CA 95134
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Contents
Introduction to the Hard Processor System....................................................... 1-1
Features of the HPS......................................................................................................................................1-3
HPS Block Diagram and System Integration........................................................................................... 1-4
HPS Block Diagram.........................................................................................................................1-4
Cortex-A9 MPCore..........................................................................................................................1-5
HPS Interfaces.................................................................................................................................. 1-5
System Interconnect.........................................................................................................................1-6
On-Chip Memory............................................................................................................................ 1-7
Flash Memory Controllers..............................................................................................................1-8
Support Peripherals..........................................................................................................................1-9
Interface Peripherals......................................................................................................................1-11
CoreSight Debug and Trace..........................................................................................................1-14
Endian Support.......................................................................................................................................... 1-15
Introduction to the Hard Processor System Address Map...................................................................1-15
HPS Address Spaces.......................................................................................................................1-15
HPS Peripheral Region Address Map..........................................................................................1-17
Document Revision History.....................................................................................................................1-20
Clock Manager.....................................................................................................2-1
Features of the Clock Manager...................................................................................................................2-1
Clock Manager Block Diagram and System Integration........................................................................ 2-2
L4 Peripheral Clocks........................................................................................................................2-3
Functional Description of the Clock Manager.........................................................................................2-4
Clock Manager Building Blocks.....................................................................................................2-4
Hardware-Managed and Soware-Managed Clocks...................................................................2-7
Clock Groups....................................................................................................................................2-7
Resets............................................................................................................................................... 2-17
Safe Mode........................................................................................................................................2-17
Interrupts.........................................................................................................................................2-18
Clock Usage By Module................................................................................................................ 2-18
Clock Manager Address Map and Register Denitions........................................................................2-23
Clock Manager Module Address Map.........................................................................................2-24
Document Revision History.....................................................................................................................2-73
Reset Manager..................................................................................................... 3-1
Reset Manager Block Diagram and System Integration.........................................................................3-2
HPS External Reset Sources............................................................................................................3-3
Reset Controller................................................................................................................................3-4
Module Reset Signals.......................................................................................................................3-5
Slave Interface and Status Register.............................................................................................. 3-10
Functional Description of the Reset Manager....................................................................................... 3-10
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Reset Sequencing............................................................................................................................3-11
Reset Pins........................................................................................................................................ 3-15
Reset Eects.................................................................................................................................... 3-15
Altering Warm Reset System Response...................................................................................... 3-15
Reset Handshaking........................................................................................................................ 3-16
Reset Manager Address Map and Register Denitions.........................................................................3-16
Reset Manager Module Address Map......................................................................................... 3-17
Document Revision History.....................................................................................................................3-32
FPGA Manager.................................................................................................... 4-1
Features of the FPGA Manager..................................................................................................................4-1
FPGA Manager Block Diagram and System Integration........................................................................4-2
Functional Description of the FPGA Manager........................................................................................4-3
FPGA Manager Building Blocks.................................................................................................... 4-3
FPGA Conguration....................................................................................................................... 4-4
FPGA Status......................................................................................................................................4-8
Error Message Extraction................................................................................................................4-8
Boot Handshake............................................................................................................................... 4-8
General Purpose I/O........................................................................................................................4-9
Clock..................................................................................................................................................4-9
Reset...................................................................................................................................................4-9
FPGA Manager Address Map and Register Denitions.........................................................................4-9
FPGA Manager Module Conguration Data Address Map.......................................................4-9
FPGA Manager Module Address Map........................................................................................4-10
Document Revision History.....................................................................................................................4-51
System Manager...................................................................................................5-1
Features of the System Manager.................................................................................................................5-1
System Manager Block Diagram and System Integration...................................................................... 5-2
Functional Description of the System Manager.......................................................................................5-3
Boot Conguration and System Information.............................................................................. 5-3
Additional Module Control............................................................................................................ 5-3
Boot ROM Code...............................................................................................................................5-6
FPGA Interface Enables.................................................................................................................. 5-8
ECC and Parity Control.................................................................................................................. 5-8
Preloader Hando Information..................................................................................................... 5-9
Clocks................................................................................................................................................ 5-9
Resets................................................................................................................................................. 5-9
System Manager Address Map and Register Denitions........................................................................5-9
System Manager Module Address Map.........................................................................................5-9
Document Revision History...................................................................................................................5-237
Scan Manager.......................................................................................................6-1
Features of the Scan Manager.....................................................................................................................6-1
Scan Manager Block Diagram and System Integration.......................................................................... 6-2
ARM JTAG-AP Signal Use in the Scan Manager.........................................................................6-2
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ARM JTAG-AP Scan Chains.......................................................................................................... 6-3
Functional Description of the Scan Manager...........................................................................................6-5
Conguring HPS I/O Scan Chains................................................................................................6-5
Communicating with the JTAG TAP Controller.........................................................................6-6
JTAG-AP FIFO Buer Access and Byte Command Protocol.................................................... 6-6
Clocks................................................................................................................................................ 6-7
Resets................................................................................................................................................. 6-8
Scan Manager Address Map and Register Denitions............................................................................6-8
JTAG-AP Register Name Cross Reference Table......................................................................... 6-8
Scan Manager Module Registers Address Map............................................................................6-9
Document Revision History.....................................................................................................................6-16
System Interconnect............................................................................................ 7-1
Features of the System Interconnect..........................................................................................................7-1
System Interconnect Block Diagram and System Integration............................................................... 7-2
Interconnect Block Diagram.......................................................................................................... 7-2
System Interconnect Architecture..................................................................................................7-2
Main Connectivity Matrix.............................................................................................................. 7-3
Functional Description of the Interconnect............................................................................................. 7-4
Master to Slave Connectivity Matrix.............................................................................................7-4
System Interconnect Address Spaces.............................................................................................7-5
Master Caching and Buering Overrides...................................................................................7-13
Security............................................................................................................................................7-14
Controlling Quality of Service from Soware............................................................................7-14
Cyclic Dependency Avoidance Schemes.....................................................................................7-15
System Interconnect Master Properties...................................................................................... 7-16
Interconnect Slave Properties.......................................................................................................7-17
Upsizing Data Width Function....................................................................................................7-20
Downsizing Data Width Function...............................................................................................7-21
Lock Support...................................................................................................................................7-22
FIFO Buers and Clock Crossing................................................................................................7-22
System Interconnect Resets.......................................................................................................... 7-23
System Interconnect Address Map and Register Denitions...............................................................7-23
L3 (NIC-301) GPV Registers Address Map................................................................................7-23
Document Revision History...................................................................................................................7-134
HPS-FPGA Bridges............................................................................................. 8-1
Features of the HPS-FPGA Bridges...........................................................................................................8-1
HPS-FPGA Bridges Block Diagram and System Integration.................................................................8-3
Functional Description of the HPS-FPGA Bridges.................................................................................8-4
e Global Programmers View......................................................................................................8-4
Functional Description of the FPGA-to-HPS Bridge..................................................................8-4
Functional Description of the HPS-to-FPGA Bridge............................................................... 8-19
Functional Description of the Lightweight HPS-to-FPGA Bridge..........................................8-32
Clocks and Resets...........................................................................................................................8-51
Data Width Sizing..........................................................................................................................8-53
HPS-FPGA Bridges Address Map and Register Denitions................................................................8-53
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Document Revision History.....................................................................................................................8-54
Cortex-A9 Microprocessor Unit Subsystem....................................................... 9-1
Features of the Cortex-A9 MPU Subsystem.............................................................................................9-1
Cortex-A9 MPU Subsystem Block Diagram and System Integration.................................................. 9-2
Cortex-A9 MPU Subsystem with System Interconnect..............................................................9-2
Cortex-A9 MPU Subsystem Internals...........................................................................................9-3
Cortex-A9 MPCore......................................................................................................................................9-4
Functional Description....................................................................................................................9-4
Implementation Details...................................................................................................................9-5
Cortex-A9 Processor........................................................................................................................9-6
Interactive Debugging Features......................................................................................................9-7
L1 Caches.......................................................................................................................................... 9-7
Preload Engine..................................................................................................................................9-7
Floating Point Unit...........................................................................................................................9-8
NEON Multimedia Processing Engine......................................................................................... 9-8
Memory Management Unit............................................................................................................ 9-9
Performance Monitoring Unit......................................................................................................9-12
ARM Cortex-A9 MPCore Timers............................................................................................... 9-12
Generic Interrupt Controller........................................................................................................9-13
Global Timer...................................................................................................................................9-25
Snoop Control Unit....................................................................................................................... 9-26
Accelerator Coherency Port..........................................................................................................9-27
ACP ID Mapper......................................................................................................................................... 9-31
Functional Description..................................................................................................................9-31
Implementation Details.................................................................................................................9-32
ACP ID Mapper Address Map and Register Denitions..........................................................9-37
L2 Cache......................................................................................................................................................9-61
Functional Description..................................................................................................................9-61
CPU Prefetch.............................................................................................................................................. 9-68
Debugging Modules...................................................................................................................................9-68
Program Trace................................................................................................................................ 9-68
Event Trace......................................................................................................................................9-69
Cross-Triggering............................................................................................................................ 9-69
Clocks.......................................................................................................................................................... 9-70
Cortex-A9 MPU Subsystem Register Implementation.........................................................................9-70
Cortex-A9 MPU Subsystem Address Map.................................................................................9-71
L2 Cache Controller Address Map.............................................................................................. 9-72
Document Revision History.....................................................................................................................9-73
CoreSight Debug and Trace...............................................................................10-1
Features of CoreSight Debug and Trace..................................................................................................10-2
ARM CoreSight Documentation............................................................................................................. 10-2
CoreSight Debug and Trace Block Diagram and System Integration.................................................10-3
Functional Description of CoreSight Debug and Trace........................................................................10-4
Debug Access Port......................................................................................................................... 10-4
System Trace Macrocell.................................................................................................................10-4
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Trace Funnel................................................................................................................................... 10-5
CoreSight Trace Memory Controller...........................................................................................10-5
AMBA Trace Bus Replicator.........................................................................................................10-6
Trace Port Interface Unit...............................................................................................................10-6
Embedded Cross Trigger System................................................................................................. 10-6
Program Trace Macrocell............................................................................................................10-11
HPS Debug APB Interface..........................................................................................................10-11
FPGA Interface.............................................................................................................................10-11
Debug Clocks................................................................................................................................10-14
Debug Resets................................................................................................................................ 10-15
CoreSight Debug and Trace Programming Model..............................................................................10-16
Coresight Component Address..................................................................................................10-16
STM Channels..............................................................................................................................10-17
CTI Trigger Connections to Outside the Debug System........................................................10-19
Conguring Embedded Cross-Trigger Connections..............................................................10-20
CoreSight Debug and Trace Address Map and Register Denitions................................................10-22
System Trace Macrocell (STM) Module Address Map........................................................... 10-23
Debug Access Port (DAP) Module Address Map....................................................................10-23
MPU Address Map...................................................................................................................... 10-25
MPU L2 Cache Controller (L2C-310) Module Address Map................................................10-26
Document Revision History...................................................................................................................10-27
SDRAM Controller Subsystem..........................................................................11-1
Features of the SDRAM Controller Subsystem......................................................................................11-1
SDRAM Controller Subsystem Block Diagram.....................................................................................11-2
SDRAM Controller Memory Options.....................................................................................................11-3
SDRAM Controller Subsystem Interfaces.............................................................................................. 11-4
MPU Subsystem Interface.............................................................................................................11-4
L3 Interconnect Interface..............................................................................................................11-4
CSR Interface..................................................................................................................................11-5
FPGA-to-HPS SDRAM Interface.................................................................................................11-5
Memory Controller Architecture.............................................................................................................11-6
Multi-Port Front End.....................................................................................................................11-7
Single-Port Controller................................................................................................................... 11-8
Functional Description of the SDRAM Controller Subsystem..........................................................11-10
MPFE Operation Ordering.........................................................................................................11-10
MPFE Multi-Port Arbitration.................................................................................................... 11-10
MPFE SDRAM Burst Scheduling.............................................................................................. 11-13
Single-Port Controller Operation..............................................................................................11-14
SDRAM Power Management................................................................................................................. 11-24
DDR PHY................................................................................................................................................. 11-25
DDR Calibration..........................................................................................................................11-25
Clocks........................................................................................................................................................ 11-25
Resets......................................................................................................................................................... 11-26
Taking the SDRAM Controller Subsystem Out of Reset .......................................................11-26
Port Mappings.......................................................................................................................................... 11-26
Initialization..............................................................................................................................................11-27
FPGA-to-SDRAM Protocol Details...........................................................................................11-28
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SDRAM Controller Subsystem Programming Model........................................................................ 11-32
HPS Memory Interface Architecture.........................................................................................11-32
HPS Memory Interface Conguration......................................................................................11-32
HPS Memory Interface Simulation........................................................................................... 11-33
Generating a Preloader Image for HPS with EMIF.................................................................11-33
Debugging HPS SDRAM in the Preloader...........................................................................................11-35
Enabling UART or Semihosting Printout.................................................................................11-35
Enabling Simple Memory Test................................................................................................... 11-36
Enabling the Debug Report........................................................................................................ 11-37
Writing a Predened Data Pattern to SDRAM in the Preloader...........................................11-40
SDRAM Controller Address Map and Register Denitions.............................................................. 11-41
SDRAM Controller Address Map..............................................................................................11-41
Document Revision History...................................................................................................................11-77
On-Chip Memory.............................................................................................. 12-1
On-Chip RAM............................................................................................................................................12-1
Features of the On-Chip RAM.....................................................................................................12-1
On-Chip RAM Block Diagram and System Integration...........................................................12-1
Functional Description of the On-Chip RAM...........................................................................12-2
Boot ROM...................................................................................................................................................12-3
Features of the Boot ROM............................................................................................................ 12-3
Boot ROM Block Diagram and System Integration..................................................................12-3
Functional Description of the Boot ROM.................................................................................. 12-3
On-Chip Memory Address Map and Register Denitions.................................................................. 12-4
On-chip RAM Address Map.........................................................................................................12-4
Boot ROM Address Map...............................................................................................................12-4
Document Revision History.....................................................................................................................12-4
NAND Flash Controller.................................................................................... 13-1
NAND Flash Controller Features............................................................................................................ 13-1
NAND Flash Controller Block Diagram and System Integration.......................................................13-2
NAND Flash Controller Signal Descriptions.........................................................................................13-2
Functional Description of the NAND Flash Controller....................................................................... 13-3
Discovery and Initialization......................................................................................................... 13-3
Bootstrap Interface.........................................................................................................................13-4
Conguration by Host...................................................................................................................13-5
Local Memory Buer.....................................................................................................................13-6
Clocks.............................................................................................................................................. 13-6
Resets............................................................................................................................................... 13-7
Indexed Addressing....................................................................................................................... 13-7
Command Mapping...................................................................................................................... 13-8
Data DMA.....................................................................................................................................13-14
ECC................................................................................................................................................13-18
NAND Flash Controller Programming Model....................................................................................13-21
Basic Flash Programming...........................................................................................................13-22
Flash-Related Special Function Operations.............................................................................13-25
NAND Flash Controller Address Map and Register Denitions...................................................... 13-33
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NAND Controller Module Data (AXI Slave) Address Map...................................................13-33
NAND Flash Controller Module Registers (AXI Slave) Address Map.................................13-34
Document Revision History.................................................................................................................13-124
SD/MMC Controller..........................................................................................14-1
Features of the SD/MMC Controller.......................................................................................................14-1
SD Card Support Matrix............................................................................................................... 14-2
MMC Support Matrix....................................................................................................................14-3
SD/MMC Controller Block Diagram and System Integration............................................................ 14-3
SD/MMC Controller Signal Description................................................................................................14-4
Functional Description of the SD/MMC Controller.............................................................................14-5
SD/MMC/CE-ATA Protocol........................................................................................................ 14-5
BIU...................................................................................................................................................14-6
CIU.................................................................................................................................................14-20
Clocks............................................................................................................................................ 14-35
Resets............................................................................................................................................. 14-36
Voltage Switching.........................................................................................................................14-37
SD/MMC Controller Programming Model......................................................................................... 14-39
Soware and Hardware Restrictions†....................................................................................... 14-39
Initialization†................................................................................................................................14-41
Controller/DMA/FIFO Buer Reset Usage..............................................................................14-47
Enabling FIFO Buer ECC.........................................................................................................14-47
Non-Data Transfer Commands................................................................................................. 14-47
Data Transfer Commands...........................................................................................................14-49
Transfer Stop and Abort Commands........................................................................................ 14-56
Internal DMA Controller Operations.......................................................................................14-58
Commands for SDIO Card Devices.......................................................................................... 14-60
CE-ATA Data Transfer Commands.......................................................................................... 14-62
Card Read reshold...................................................................................................................14-70
Interrupt and Error Handling.................................................................................................... 14-73
Booting Operation for eMMC and MMC................................................................................14-74
SD/MMC Controller Address Map and Register Denitions............................................................14-84
SDMMC Module Address Map................................................................................................. 14-84
Document Revision History.................................................................................................................14-143
Quad SPI Flash Controller................................................................................ 15-1
Features of the Quad SPI Flash Controller.............................................................................................15-1
Quad SPI Flash Controller Block Diagram and System Integration...................................................15-2
Interface Signals......................................................................................................................................... 15-3
Functional Description of the Quad SPI Flash Controller...................................................................15-3
Overview......................................................................................................................................... 15-3
Data Slave Interface....................................................................................................................... 15-4
SPI Legacy Mode............................................................................................................................15-7
Register Slave Interface..................................................................................................................15-8
Local Memory Buer.....................................................................................................................15-8
DMA Peripheral Request Controller...........................................................................................15-9
Arbitration between Direct/Indirect Access Controller and STIG....................................... 15-10
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Conguring the Flash Device.....................................................................................................15-10
XIP Mode...................................................................................................................................... 15-12
Write Protection...........................................................................................................................15-12
Data Slave Sequential Access Detection................................................................................... 15-12
Clocks............................................................................................................................................ 15-12
Resets............................................................................................................................................. 15-13
Interrupts...................................................................................................................................... 15-13
Quad SPI Flash Controller Programming Model................................................................................15-14
Setting Up the Quad SPI Flash Controller................................................................................15-15
Indirect Read Operation with DMA Disabled.........................................................................15-15
Indirect Read Operation with DMA Enabled..........................................................................15-16
Indirect Write Operation with DMA Disabled........................................................................15-16
Indirect Write Operation with DMA Enabled.........................................................................15-17
XIP Mode Operations................................................................................................................. 15-17
Quad SPI Flash Controller Address Map and Register Denitions..................................................15-19
QSPI Flash Controller Module Registers Address Map..........................................................15-20
QSPI Flash Module Data (AHB Slave) Address Map............................................................. 15-61
Document Revision History...................................................................................................................15-61
DMA Controller................................................................................................ 16-1
Features of the DMA Controller..............................................................................................................16-1
DMA Controller Block Diagram and System Integration....................................................................16-3
Functional Description of the DMA Controller....................................................................................16-3
AXI Characteristics for a DMA Transfer....................................................................................16-4
Operating States............................................................................................................................. 16-5
Initializing the DMAC...................................................................................................................16-8
Using the Slave Interfaces............................................................................................................. 16-9
Peripheral Request Interface.......................................................................................................16-10
Using Events and Interrupts....................................................................................................... 16-21
Aborts............................................................................................................................................ 16-23
Security Usage.............................................................................................................................. 16-26
Programming Restrictions..........................................................................................................16-29
Constraints and Limitations of Use...........................................................................................16-33
DMA Controller Programming Model.................................................................................................16-34
Instruction Syntax Conventions................................................................................................ 16-34
Instruction Set Summary............................................................................................................16-34
Instructions...................................................................................................................................16-35
Assembler Directives...................................................................................................................16-50
MFIFO Buer Usage Overview..................................................................................................16-52
DMA Controller Address Map and Register Denitions...................................................................16-60
Address Map and Register Denitions..................................................................................... 16-62
Document Revision History...................................................................................................................16-63
Ethernet Media Access Controller.................................................................... 17-1
Features of the Ethernet MAC..................................................................................................................17-2
MAC.................................................................................................................................................17-2
DMA................................................................................................................................................ 17-2
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Management Interface...................................................................................................................17-3
Acceleration.................................................................................................................................... 17-3
PHY Interface................................................................................................................................. 17-3
EMAC Block Diagram and System Integration.....................................................................................17-4
EMAC Signal Description.........................................................................................................................17-5
HPS EMAC I/O Signals.................................................................................................................17-6
FPGA EMAC I/O Signals..............................................................................................................17-8
PHY Management Interface.......................................................................................................17-11
EMAC Internal Interfaces.......................................................................................................................17-12
DMA Master Interface................................................................................................................ 17-12
Timestamp Interface....................................................................................................................17-12
Functional Description of the EMAC...................................................................................................17-14
Transmit and Receive Data FIFO Buers.................................................................................17-15
DMA Controller...........................................................................................................................17-16
Descriptor Overview................................................................................................................... 17-29
IEEE 1588-2002 Timestamps..................................................................................................... 17-46
IEEE 1588-2008 Advanced Timestamps...................................................................................17-52
IEEE 802.3az Energy Ecient Ethernet....................................................................................17-55
Checksum Ooad....................................................................................................................... 17-56
Frame Filtering.............................................................................................................................17-56
Clocks and Resets.........................................................................................................................17-61
Interrupts...................................................................................................................................... 17-63
Ethernet MAC Programming Model.................................................................................................... 17-63
System Level EMAC Conguration Registers..........................................................................17-63
EMAC FPGA Interface Initialization........................................................................................17-65
EMAC HPS Interface Initialization...........................................................................................17-66
DMA Initialization.......................................................................................................................17-66
EMAC Initialization and Conguration...................................................................................17-67
Performing Normal Receive and Transmit Operation........................................................... 17-68
Stopping and Starting Transmission......................................................................................... 17-68
Programming Guidelines for Energy Ecient Ethernet........................................................ 17-69
Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output..............................17-70
Ethernet MAC Address Map and Register Denitions.......................................................................17-72
EMAC Module Address Map.....................................................................................................17-72
Document Revision History.................................................................................................................17-873
USB 2.0 OTG Controller................................................................................... 18-1
Features of the USB OTG Controller...................................................................................................... 18-2
Supported PHYS.............................................................................................................................18-3
USB OTG Controller Block Diagram and System Integration............................................................18-4
USB 2.0 ULPI PHY Signal Description...................................................................................................18-5
Functional Description of the USB OTG Controller............................................................................ 18-6
USB OTG Controller Block Description.................................................................................... 18-6
Local Memory Buer...................................................................................................................18-10
Clocks............................................................................................................................................ 18-10
Resets............................................................................................................................................. 18-10
Interrupts...................................................................................................................................... 18-11
USB OTG Controller Programming Model.........................................................................................18-13
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Enabling SPRAM ECCs.............................................................................................................. 18-13
Host Operation.............................................................................................................................18-13
Device Operation.........................................................................................................................18-15
USB 2.0 OTG Controller Address Map and Register Denitions.....................................................18-17
USB OTG Controller Module Registers Address Map........................................................... 18-17
Document Revision History.................................................................................................................18-841
SPI Controller....................................................................................................19-1
Features of the SPI Controller.................................................................................................................. 19-1
SPI Block Diagram and System Integration...........................................................................................19-2
SPI Block Diagram.........................................................................................................................19-2
SPI Controller Signal Description........................................................................................................... 19-3
Interface to HPS I/O......................................................................................................................19-3
FPGA Routing................................................................................................................................ 19-3
Functional Description of the SPI Controller........................................................................................ 19-4
Protocol Details and Standards Compliance..............................................................................19-4
SPI Controller Overview...............................................................................................................19-5
Transfer Modes...............................................................................................................................19-8
SPI Master....................................................................................................................................... 19-9
SPI Slave........................................................................................................................................ 19-12
Partner Connection Interfaces...................................................................................................19-16
DMA Controller Interface.......................................................................................................... 19-21
Slave Interface...............................................................................................................................19-21
Clocks and Resets.........................................................................................................................19-22
SPI Programming Model........................................................................................................................ 19-23
Master SPI and SSP Serial Transfers..........................................................................................19-24
Master Microwire Serial Transfers.............................................................................................19-26
Slave SPI and SSP Serial Transfers.............................................................................................19-28
Slave Microwire Serial Transfers................................................................................................19-29
Soware Control for Slave Selection......................................................................................... 19-29
DMA Controller Operation........................................................................................................19-30
SPI Controller Address Map and Register Denitions.......................................................................19-33
SPI Master Module Address Map.............................................................................................. 19-33
SPI Slave Module Address Map................................................................................................. 19-61
Document Revision History...................................................................................................................19-85
I2C Controller....................................................................................................20-1
Features of the I2C Controller.................................................................................................................. 20-1
I2C Controller Block Diagram and System Integration........................................................................20-2
I2C Controller Signal Description........................................................................................................... 20-3
Functional Description of the I2C Controller........................................................................................ 20-4
Feature Usage..................................................................................................................................20-4
Behavior...........................................................................................................................................20-5
Protocol Details..............................................................................................................................20-6
Multiple Master Arbitration.......................................................................................................20-11
Clock Frequency Conguration................................................................................................ 20-13
SDA Hold Time............................................................................................................................20-15
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DMA Controller Interface.......................................................................................................... 20-15
Clocks............................................................................................................................................ 20-15
Resets............................................................................................................................................. 20-15
I2C Controller Programming Model.....................................................................................................20-16
Slave Mode Operation.................................................................................................................20-16
Master Mode Operation..............................................................................................................20-19
Disabling the I2C Controller...................................................................................................... 20-20
DMA Controller Operation........................................................................................................20-20
I2C Controller Address Map and Register Denitions.......................................................................20-24
I2C Module Address Map...........................................................................................................20-24
Document Revision History...................................................................................................................20-78
UART Controller............................................................................................... 21-1
UART Controller Features........................................................................................................................21-1
UART Controller Block Diagram and System Integration...................................................................21-2
UART Controller Signal Description...................................................................................................... 21-3
HPS I/O Pins...................................................................................................................................21-3
FPGA Routing................................................................................................................................ 21-3
Functional Description of the UART Controller...................................................................................21-4
FIFO Buer Support......................................................................................................................21-4
UART(RS232) Serial Protocol......................................................................................................21-5
Automatic Flow Control............................................................................................................... 21-5
Clocks.............................................................................................................................................. 21-7
Resets............................................................................................................................................... 21-7
Interrupts.........................................................................................................................................21-7
DMA Controller Operation....................................................................................................................21-10
Transmit FIFO Underow..........................................................................................................21-11
Transmit Watermark Level......................................................................................................... 21-11
Transmit FIFO Overow............................................................................................................ 21-12
Receive FIFO Overow...............................................................................................................21-13
Receive Watermark Level............................................................................................................21-13
Receive FIFO Underow.............................................................................................................21-13
UART Controller Address Map and Register Denitions..................................................................21-14
UART Module Address Map......................................................................................................21-14
Document Revision History...................................................................................................................21-56
General-Purpose I/O Interface......................................................................... 22-1
Features of the GPIO Interface.................................................................................................................22-1
GPIO Interface Block Diagram and System Integration...................................................................... 22-2
Functional Description of the GPIO Interface.......................................................................................22-3
Debounce Operation..................................................................................................................... 22-3
Pin Directions.................................................................................................................................22-3
Taking the GPIO Interface Out of Reset ....................................................................................22-3
GPIO Interface Programming Model..................................................................................................... 22-4
General-Purpose I/O Interface Address Map and Register Denitions.............................................22-4
GPIO Module Address Map.........................................................................................................22-4
Document Revision History...................................................................................................................22-22
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Timer .................................................................................................................23-1
Features of the Timer.................................................................................................................................23-1
Timer Block Diagram and System Integration...................................................................................... 23-1
Functional Description of the Timer.......................................................................................................23-2
Clocks.............................................................................................................................................. 23-3
Resets............................................................................................................................................... 23-3
Interrupts.........................................................................................................................................23-3
FPGA Interface...............................................................................................................................23-3
Timer Programming Model..................................................................................................................... 23-5
Initialization....................................................................................................................................23-5
Enabling the Timer........................................................................................................................ 23-5
Disabling the Timer.......................................................................................................................23-5
Loading the Timer Countdown Value.........................................................................................23-5
Servicing Interrupts....................................................................................................................... 23-6
Timer Address Map and Register Denitions........................................................................................23-6
Timer Module Address Map.........................................................................................................23-6
Document Revision History...................................................................................................................23-16
Watchdog Timer................................................................................................ 24-1
Features of the Watchdog Timer..............................................................................................................24-1
Watchdog Timer Block Diagram and System Integration................................................................... 24-2
Functional Description of the Watchdog Timer....................................................................................24-2
Watchdog Timer Counter.............................................................................................................24-2
Watchdog Timer Pause Mode...................................................................................................... 24-3
Watchdog Timer Clocks................................................................................................................24-3
Watchdog Timer Resets.................................................................................................................24-3
FPGA Interface...............................................................................................................................24-4
Watchdog Timer Programming Model...................................................................................................24-4
Setting the Timeout Period Values.............................................................................................. 24-4
Selecting the Output Response Mode......................................................................................... 24-4
Enabling and Initially Starting a Watchdog Timer....................................................................24-5
Reloading a Watchdog Counter................................................................................................... 24-5
Pausing a Watchdog Timer...........................................................................................................24-5
Disabling and Stopping a Watchdog Timer................................................................................24-5
Watchdog Timer State Machine...................................................................................................24-5
Watchdog Timer Address Map and Register Denitions.....................................................................24-7
L4 Watchdog Module Address Map............................................................................................24-7
Document Revision History...................................................................................................................24-21
CAN Controller................................................................................................. 25-1
Features of the CAN Controller...............................................................................................................25-1
CAN Controller Block Diagram and System Integration.....................................................................25-2
Functional Description of the CAN Controller.....................................................................................25-3
Message Object...............................................................................................................................25-3
Message Interface Registers.......................................................................................................... 25-7
TOC-13
Altera Corporation

DMA Mode.....................................................................................................................................25-8
Automatic Retransmission............................................................................................................25-8
Test Mode........................................................................................................................................25-8
L4 Slave Interface......................................................................................................................... 25-10
Clocks............................................................................................................................................ 25-10
Soware Reset...............................................................................................................................25-10
Hardware Reset............................................................................................................................ 25-11
Interrupts...................................................................................................................................... 25-11
CAN Controller Programming Model..................................................................................................25-12
Soware Initialization................................................................................................................. 25-12
CAN Message Transfer................................................................................................................25-13
Message Object Reconguration for Frame Reception.......................................................... 25-13
Message Object Reconguration for Frame Transmission.................................................... 25-14
CAN Controller Address Map and Register Denitions....................................................................25-14
CAN Controller Module Address Map.....................................................................................25-15
Document Revision History.................................................................................................................25-233
Introduction to the HPS Component............................................................... 26-1
MPU Subsystem......................................................................................................................................... 26-2
ARM CoreSight Debug Components......................................................................................................26-2
Interconnect................................................................................................................................................26-2
HPS-to-FPGA Interfaces...........................................................................................................................26-2
Memory Controllers.................................................................................................................................. 26-3
Support Peripherals....................................................................................................................................26-3
Interface Peripherals..................................................................................................................................26-3
On-Chip Memories....................................................................................................................................26-4
Document Revision History.....................................................................................................................26-4
Instantiating the HPS Component................................................................... 27-1
FPGA Interfaces......................................................................................................................................... 27-1
General Interfaces.......................................................................................................................... 27-2
FPGA-to-HPS SDRAM Interface.................................................................................................27-3
DMA Peripheral Request.............................................................................................................. 27-5
Interrupts.........................................................................................................................................27-5
AXI Bridges.....................................................................................................................................27-7
Conguring HPS Clocks and Resets....................................................................................................... 27-8
User Clocks..................................................................................................................................... 27-8
Reset Interfaces...............................................................................................................................27-9
PLL Reference Clocks..................................................................................................................27-10
Peripheral FPGA Clocks............................................................................................................. 27-11
Conguring Peripheral Pin Multiplexing.............................................................................................27-11
Conguring Peripherals..............................................................................................................27-12
Connecting Unassigned Pins to GPIO......................................................................................27-12
Using Unassigned IO as LoanIO................................................................................................27-13
Resolving Pin Multiplexing Conicts........................................................................................27-13
Peripheral Signals Routed to FPGA ..........................................................................................27-13
Conguring the External Memory Interface........................................................................................27-14
TOC-14
Altera Corporation

Selecting PLL Output Frequency and Phase............................................................................ 27-15
Using the Address Span Extender Component....................................................................................27-15
Generating and Compiling the HPS Component............................................................................... 27-16
Document Revision History...................................................................................................................27-17
HPS Component Interfaces...............................................................................28-1
Memory-Mapped Interfaces.....................................................................................................................28-1
FPGA-to-HPS Bridge.................................................................................................................... 28-1
HPS-to-FPGA and Lightweight HPS-to-FPGA Bridges...........................................................28-2
FPGA-to-HPS SDRAM Interface.................................................................................................28-3
Clocks.......................................................................................................................................................... 28-4
Alternative Clock Inputs to HPS PLLs........................................................................................28-4
User Clocks..................................................................................................................................... 28-4
AXI Bridge FPGA Interface Clocks.............................................................................................28-5
SDRAM Clocks.............................................................................................................................. 28-5
Peripheral FPGA Clocks............................................................................................................... 28-5
Resets........................................................................................................................................................... 28-6
HPS-to-FPGA Reset Interfaces.................................................................................................... 28-6
HPS External Reset Request......................................................................................................... 28-6
Peripheral Reset Interfaces............................................................................................................28-7
Debug and Trace Interfaces...................................................................................................................... 28-7
Trace Port Interface Unit...............................................................................................................28-7
FPGA System Trace Macrocell Events Interface........................................................................28-7
FPGA Cross Trigger Interface...................................................................................................... 28-7
Debug APB Interface.....................................................................................................................28-7
Peripheral Signal Interfaces...................................................................................................................... 28-7
DMA Controller Interface............................................................................................................ 28-7
Other Interfaces..........................................................................................................................................28-8
MPU Standby and Event Interfaces.............................................................................................28-8
General Purpose Signals............................................................................................................... 28-9
FPGA-to-HPS Interrupts.............................................................................................................. 28-9
Boot from FPGA Interface............................................................................................................28-9
Input-only General Purpose Interface........................................................................................ 28-9
Document Revision History.....................................................................................................................28-9
Simulating the HPS Component.......................................................................29-1
Simulation Flows........................................................................................................................................29-2
Setting Up the HPS Component for Simulation........................................................................29-3
Generating the HPS Simulation Model in Qsys........................................................................ 29-5
Running the Simulations...............................................................................................................29-5
Clock and Reset Interfaces........................................................................................................................29-9
Clock Interface............................................................................................................................... 29-9
Reset Interface.............................................................................................................................. 29-10
FPGA-to-HPS AXI Slave Interface........................................................................................................29-11
HPS-to-FPGA AXI Master Interface.....................................................................................................29-11
Lightweight HPS-to-FPGA AXI Master Interface...............................................................................29-12
FPGA-to-HPS SDRAM Interface.......................................................................................................... 29-13
TOC-15
Altera Corporation

HPS Memory Interface Simulation........................................................................................... 29-13
HPS-to-FPGA MPU Event Interface.....................................................................................................29-14
Interrupts Interface..................................................................................................................................29-14
HPS-to-FPGA Debug APB Interface.................................................................................................... 29-16
FPGA-to-HPS System Trace Macrocell Hardware Event Interface...................................................29-16
HPS-to-FPGA Cross-Trigger Interface.................................................................................................29-17
HPS-to-FPGA Trace Port Interface.......................................................................................................29-17
FPGA-to-HPS DMA Handshake Interface...........................................................................................29-18
Boot from FPGA Interface......................................................................................................................29-19
General Purpose Input Interface............................................................................................................29-20
Document Revision History...................................................................................................................29-21
Booting and Conguration................................................................................ A-1
Boot Overview.............................................................................................................................................A-1
FPGA Conguration Overview.................................................................................................................A-1
Booting and Conguration Options.........................................................................................................A-2
Boot Denitions.......................................................................................................................................... A-5
Reset.................................................................................................................................................. A-5
Boot ROM........................................................................................................................................ A-5
Boot Select........................................................................................................................................A-6
Flash Memory Devices for Booting............................................................................................ A-13
Clock Select....................................................................................................................................A-25
I/O Conguration......................................................................................................................... A-25
L4 Watchdog 0 Timer................................................................................................................... A-26
Preloader.........................................................................................................................................A-26
U-Boot Loader...............................................................................................................................A-26
Boot ROM Flow.........................................................................................................................................A-26
Typical Preloader Boot Flow....................................................................................................................A-28
HPS State on Entry to the Preloader...........................................................................................A-31
Shared Memory............................................................................................................................. A-31
Loading the Preloader Image.......................................................................................................A-32
FPGA Conguration.................................................................................................................................A-33
Full Conguration.........................................................................................................................A-33
Partial Reconguration.................................................................................................................A-34
Document Revision History.................................................................................................................... A-35
TOC-16
Altera Corporation

Introduction to the Hard Processor System 1
2016.10.28
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e Cyclone®V system-on-a-chip (SoC) is composed of two distinct portions- a single- or dual-core
ARM®Cortex™-A9 hard processor system (HPS) and an FPGA. e HPS architecture integrates a wide set
of peripherals that reduce board size and increase performance within a system.
e SoC features the FPGA I/O, which is I/O pins dedicated to the FPGA fabric.
Figure 1-1: Altera SoC Device Block Diagram
Altera SoC Device
HPS Portion
Flash
Controllers
SDRAM Controller
Subsystem
Cortex-A9 MPU Subsystem
On-Chip
Memories
Support
Peripherals
PLLs Interface
Peripherals Debug
HPS-FPGA
Interfaces
Control
Block
User
I/O
HSSI
Transceivers
FPGA Fabric
(LUTs, RAMs, Multipliers & Routing)
PLLs Hard
PCIe
Hard Memory
Controllers
FPGA Portion
e HPS consists of the following types of modules:
• Microprocessor unit (MPU) subsystem with single or dual ARM Cortex-A9 MPCore®processors
• Flash memory controllers
• SDRAM controller subsystem
• System interconnect
• On-chip memories
• Support peripherals
• Interface peripherals
• Debug components
• Phase-locked loops (PLLs)
©2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos
are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants
performance of its FPGA and semiconductor products to current specications in accordance with Intel's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of
device specications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134

e HPS incorporates third-party intellectual property (IP) from several vendors.
e dual-processor HPS supports symmetric (SMP) and asymmetric (AMP) multiprocessing.
e FPGA portion of the device contains:
• FPGA fabric
• Control block (CB)
• PLLs
• High-speed serial interface (HSSI) transceivers, depending on the device variant
• Hard PCI Express®(PCI-e) controllers
• Hard memory controllers
e HPS and FPGA communicate with each other through bus interfaces that bridge the two distinct
portions. On a power-on reset, the HPS can boot from multiple sources, including the FPGA fabric and
external ash. e FPGA can be congured through the HPS or an externally supported device.
e HPS and FPGA portions of the device each have their own pins. Pins are not freely shared between
the HPS and the FPGA fabric. e HPS I/O pins are congured by boot soware executed by the MPU in
the HPS. Soware executing on the HPS accesses control registers in the system manager to assign HPS
I/O pins to the available HPS modules. e FPGA I/O pins are congured by an FPGA conguration
image through the HPS or any external source supported by the device.
e MPU subsystem can boot from ash devices connected to the HPS pins. When the FPGA portion is
congured by an external source, the MPU subsystem can boot from ash memory devices available to the
FPGA portion of the device.
e HPS and FPGA portions of the device have separate external power supplies and independently
power on. You can power on the HPS without powering on the FPGA portion of the device. However, to
power on the FPGA portion, the HPS must already be on or powered at the same time as the FPGA
portion. You can also turn o the FPGA portion of the device while leaving the HPS power on.
Table 1-1: Valid SoC Power Modes
HPS FPGA Valid?
O O Yes
O On No
On O Yes
On On Yes
Related Information
•Booting and Conguration on page 30-1
•Cyclone V Device Datasheet
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Features of the HPS
e main modules of the HPS are:
• MPU subsystem featuring a single- or dual-core ARM Cortex-A9 MPCore processor
• General-purpose direct memory access (DMA) controller
• Two ethernet media access controllers (EMACs)
• Two USB 2.0 on-the-go (OTG) controllers
• NAND ash controller
• Quad SPI ash controller
• Secure digital/multimedia card (SD/MMC) controller
• Two serial peripheral interface (SPI) master controllers
• Two SPI slave controllers
• Four inter-integrated circuit (I2C) controllers
• 64 KB on-chip RAM
• 64 KB on-chip boot ROM
• Two UARTs
• Four timers
• Two watchdog timers
•ree general-purpose I/O (GPIO) interfaces
• Two controller area network (CAN) controllers
• ARM Coresight™debug components:
• Debug access port (DAP)
• Trace port interface unit (TPIU)
• System trace macrocell (STM)
• Program trace macrocell (PTM)
• Embedded trace router (ETR)
• Embedded cross trigger (ECT)
• System manager
• Clock manager
• Reset manager
• Scan manager
• FPGA manager
• SDRAM controller subsystem
(1) Two of the four I2Cs, provide support for general purpose.
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HPS Block Diagram and System Integration
HPS Block Diagram
Figure 1-2: HPS Block Diagram
DAP
ETR
SD/MMC
EMAC
(2)
USB
OTG
(2)
NAND
Flash
CAN
(2)
Timer
(4)
Watchdog
Timer
(2)
UART
(2)
GPIO
(3)
SPI
(4)
Clock
Manager
Reset
Manager
I C
(4)
Scan
Manager
System
Manager
L4, 32-Bit Bus
32-Bit
32-Bit
32-Bit
32-Bit
32-Bit
L3 Interconnect
(NIC-301)
L3 Master
Peripheral
Switch 32-Bit
32-Bit
64-Bit
64-Bit
32-Bit
32-Bit
64-Bit
32-Bit
32-Bit
32-Bit
32-Bit
32-Bit 64-Bit
L3 Slave Peripheral Switch
ACP
CPU0 CPU1
SCU
ARM Cortex-A9
MPCore
MPU Subsystem
ACP ID
Mapper
STM
Boot ROM
On-Chip RAM
DMA
Quad
SPI
Flash
FPGA
Manager
FPGA-to-HPS
Bridge
HPS-to-FPGA
Bridge
Lightweight
HPS-to-FPGA Bridge
L4, 32-Bit Bus
32-Bit AXI
2
32-Bit 64-Bit AXI 64-Bit AXI
L3 Main
Switch
FPGA Portion
Control
Block Masters Slaves Slaves
32-, 64-, 128-Bit AXI 32-, 64-, 128-Bit AXI 32-Bit AXI
1 - 6
Masters
FPGA to HPS HPS to FPGA Lightweight HPS to FPGA
32-Bit
L2
Cache
SDRAM Controller Subsystem
Altera PHY
Interface DDR
PHY
SDRAM Controller
Single-Port
Memory
Controller
HPS I/O Pins
External Memory
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