AMD XILINX T2 Telco User manual

T2 Telco Accelerator Card
User Guide
UG1496 (v1.0) June 15, 2022
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Table of Contents
Chapter 1: Introduction.............................................................................................. 3
Hardware Overview.....................................................................................................................4
Software Overview...................................................................................................................... 5
Zynq UltraScale+ RFSoC Specification.......................................................................................5
Chapter 2: Features....................................................................................................... 7
Chapter 3: Pin Mapping...............................................................................................9
PCIe Interface.............................................................................................................................. 9
DDR4 PL Interface..................................................................................................................... 11
DDR4 PS Interface..................................................................................................................... 15
Special Functions.......................................................................................................................18
Chapter 4: Maintenance Port.................................................................................21
Chapter 5: Power...........................................................................................................22
Chapter 6: Xilinx Design Constraints (XDC) File.......................................... 23
Appendix A: Regulatory Compliance Statements...................................... 24
FCC Class A Products.................................................................................................................24
Safety.......................................................................................................................................... 24
EMC Compliance........................................................................................................................25
FCC Class A User Information..................................................................................................25
VCCI Class A Statement............................................................................................................ 26
Appendix B: Additional Resources and Legal Notices............................. 27
Xilinx Resources.........................................................................................................................27
Documentation Navigator and Design Hubs.........................................................................27
References..................................................................................................................................28
Revision History.........................................................................................................................28
Please Read: Important Legal Notices................................................................................... 28
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Chapter 1
Introduction
The Xilinx® T2 Telco accelerator card, shown in the following gure, is a single slot, half height,
half length (HHHL) plug-in card. It is compliant with PCI Express® technology, supporng PCIe
Gen3 x16 and Gen4 x8 bifurcated rates on the host interface.
Figure 1: T2 Telco Accelerator Card
The card features a 16 nm Zynq® UltraScale+™ RFSoC ZU48DR device supporng the following
targeted applicaons:
• 5G NR physical layer funconal ooad, including but not limited to:
○Low-density parity check (LDPC) encoding and decoding
○Rate matching and dematching
○Code block (CB) and CB group (CBG) processing with HARQ buer management logic in
lookaside mode
• 4G LTE physical layer funconal ooad, including but not limited to:
○Turbo encoding and decoding
○Rate matching and dematching
Chapter 1: Introduction
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○CB processing with HARQ buer management in lookaside mode
Note: The Zynq UltraScale+ RFSoC ZU48DR device also supports concurrent 4G LTE/5G NR L1 ooad,
assuming that the necessary hardware resources are available.
The T2 card value proposion is in ooading CPU intensive encode and decode computaons
involving LDPC operaons, thereby reducing costly CPU resources. The Zynq UltraScale+ RFSoC
has hard IP blocks for SD-FEC (eight SD-FEC cores per device) which can be congured to run
LDPC encode and decode operaons.
Hardware Overview
The following high-level block diagram of the T2 card provides an overview of the hardware
features.
Figure 2: T2 Card High-Level Block Diagram
Zynq UltraScale+ RFSoC
SC MSP432
Power
Supply
Unit
NOR
Flash
PL DDR
Controller
(Bank 67,
68, 69)
PS MIO
(Bank
500)
PL GTY PCIe 4
(Bank 128, 129, 130, 131)
HHHL Single Slot
PCIe Gen3 x16 /
PCIe Gen4 x8 Bifurcated
XCZU48DR- 2FSVG1517E
PS DDR
Controller
(Bank 504)
Debug Connector
1GB
DDR4
x16
1GB
DDR4
x16
1GB
DDR4
x16
ECC x8
1GB
DDR4
x16
X8
1GB
DDR4
x16
1GB
DDR4
x16
ECC x8
OSC
50 MHz
OSC
300 MHz
12V 3.3V
8x SD-FEC
(LDPC/Turbo)
X25345-051221
The T2 card hardware features are as follows:
• Zynq UltraScale+ RFSoC device targeng L1 channel coding
• NOR ash (2x 256 MB in dual QSPI mode) for ZU48DR Zynq UltraScale+ RFSoC image
storage
Chapter 1: Introduction
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• 4 GB of DDR4 programmable logic (PL) memory
• 2 GB of DDR4 processor system (PS) memory
• MSP432-based satellite controller (SC) for card monitoring and telemetry
• PCIe Gen 3 x16 or Gen 4 x8 bifurcated host interface
• Low prole (HHHL) single slot (111.15 mm x 167.65 mm) form factor with a 60W power
envelope
• DMB II maintenance and debug port for card maintenance and developer support funcons
Note: The proprietary DMB II interface requires a Xilinx ADK dongle.
Software Overview
The T2 card has a factory image installed that together with the provided host soware
installaon supports the following funcons:
• PCIe Gen3 x16 interface
• User ash image update
• SC rmware update
• DDR4 PL BERT performance and diagnoscs test
• DDR4 PS BERT performance and diagnoscs test
• PCIe performance and diagnoscs test
• In-band telemetry
Zynq UltraScale+ RFSoC Specification
The Zynq UltraScale+ RFSoC device on the T2 card is a XCZU48DR-2FSVG1517E. A comparison
of the features of this device relave to other devices in the same family is shown in the
following gure. Refer to the Zynq® UltraScale+™ RFSoC Product Selecon Guide for further
details.
Chapter 1: Introduction
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Figure 3: Zynq® UltraScale+™ RFSoC XCZU48DR Device
Chapter 1: Introduction
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Chapter 2
Features
The main features of the T2 card are as follows:
•Card over-stress protecon: The T2 card has a card protecon circuit that iniates a fatal
shutdown if either temperature or power consumpon thresholds are crossed.
Before this threshold is reached, however, the SC signals to the Zynq UltraScale+ RFSoC to
reduce the 5G workload power immediately. This indicaon is accomplished using the
RF_CPU_RST and RF_RST_REQ handshake signals.
The precise threshold levels have been determined through tesng and factory sengs to
ensure card safety. They cannot be changed.
•Out-of-band telemetry: Telemetry data for the card is provided to the server board
management controller (BMC) over the PCIe SM bus from the T2 SC. The PLDM over MCTP
protocol is used for this communicaon between server BMC and T2 SC, and implements a
thermal closed loop control mechanism for card cooling.
All required telemetry data, including board temperatures and power consumpon, is
available.
•In-band telemetry: Telemetry data for the card is also available in-band over PCIe. The
following telemetry data is available:
• Zynq UltraScale+ RFSoC
• Board inlet temperature
• Board outlet temperature
• DDR4 vicinity temperature
• PCIe 12V current
• In-band SC rmware update
Note: The PCIe 3.3V current is characterized (2.6A) but not measured.
•In-band FPGA ash update: Updang the user ash image in-band over PCIe is supported
using the flash_app ulity provided in the host soware installaon. Details are found
within the T2 Telco Accelerator Card Installaon Guide (UG1527).
Some design components must be designed into the Zynq UltraScale+ RFSoC PL and PS to
support this funcon.
Chapter 2: Features
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•Developer support: Developer support features for the Zynq UltraScale+ RFSoC on the T2
card are provided through the maintenance port. See Chapter 4: Maintenance Port for details.
•LED: A green power-on LED is present on the I/O bracket to indicate the card is powered and
in operaon.
Chapter 2: Features
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Chapter 3
Pin Mapping
This chapter presents the pin mapping for the ZU48DR Zynq® UltraScale+™ RFSoC on the T2
card.
PCIe Interface
The PCIe® interface on the T2 card has 16 lanes and can operate in Gen 3 x16 mode or Gen 4
x8x8 bifurcated mode.
Using the PCIe Interface
• The PCIe interface is supported with a dedicated IP block that must be instanated in the
design.
• PCIe lane reversal is in use.
• The server slot used with the T2 card must be a x16 capable and congured correctly for card
detecon and use. The Gen 4 x8x8 mode of operaon requires x8 bifurcaon to be enabled,
whereas Gen 3 x16 requires x16 mode.
PCIe Interface Pins
The following table summarizes the ZU48DR PCIe interface pin map.
Table 1: PCIe Interface Pin Map
Pin Number Signal Name Description I/O
W34 PCIE_RF_LOWER_REFCLK_N PCIe Lower Diff Clock (N) I
W33 PCIE_RF_LOWER_REFCLK_P PCIe Lower Diff Clock (P) I
P32 PCIE_RF_UPPER_REFCLK_N PCIe Upper Diff Clock (N) I
P31 PCIE_RF_UPPER_REFCLK_P PCIe Upper Diff Clock (P) I
AJ13 PCIE_RF_PERST_LS PCIe Reset I
AA39 PCIE_RX0_N PCIe RX Data 0 (N) I
AA38 PCIE_RX0_P PCIe RX Data 0 (P) I
W39 PCIE_RX1_N PCIe RX Data 1 (N) I
W38 PCIE_RX1_P PCIe RX Data 1 (P) I
Chapter 3: Pin Mapping
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Table 1: PCIe Interface Pin Map (cont'd)
Pin Number Signal Name Description I/O
U39 PCIE_RX2_N PCIe RX Data 2 (N) I
U38 PCIE_RX2_P PCIe RX Data 2 (P) I
R39 PCIE_RX3_N PCIe RX Data 3 (N) I
R38 PCIE_RX3_P PCIe RX Data 3 (P) I
N39 PCIE_RX4_N PCIe RX Data 4 (N) I
N38 PCIE_RX4_P PCIe RX Data 4 (P) I
M37 PCIE_RX5_N PCIe RX Data 5 (N) I
M36 PCIE_RX5_P PCIe RX Data 5 (P) I
L39 PCIE_RX6_N PCIe RX Data 6 (N) I
L38 PCIE_RX6_P PCIe RX Data 6 (P) I
K37 PCIE_RX7_N PCIe RX Data 7 (N) I
K36 PCIE_RX7_P PCIe RX Data 7 (P) I
J39 PCIE_RX8_N PCIe RX Data 8 (N) I
J38 PCIE_RX8_P PCIe RX Data 8 (P) I
H37 PCIE_RX9_N PCIe RX Data 9 (N) I
H36 PCIE_RX9_P PCIe RX Data 9 (P) I
G39 PCIE_RX10_N PCIe RX Data 10 (N) I
G38 PCIE_RX10_P PCIe RX Data 10 (P) I
F37 PCIE_RX11_N PCIe RX Data 11 (N) I
F36 PCIE_RX11_P PCIe RX Data 11 (P) I
E39 PCIE_RX12_N PCIe RX Data 12 (N) I
E38 PCIE_RX12_P PCIe RX Data 12 (P) I
D37 PCIE_RX13_N PCIe RX Data 13 (N) I
D36 PCIE_RX13_P PCIe RX Data 13 (P) I
C39 PCIE_RX14_N PCIe RX Data 14 (N) I
C38 PCIE_RX14_P PCIe RX Data 14 (P) I
B37 PCIE_RX15_N PCIe RX Data 15 (N) I
B36 PCIE_RX15_P PCIe RX Data 15 (P) I
Y36 PCIE_TX0_N PCIe TX Data 0 (N) O
Y35 PCIE_TX0_P PCIe TX Data 0 (P) O
V36 PCIE_TX1_N PCIe TX Data 1 (N) O
V35 PCIE_TX1_P PCIe TX Data 1 (P) O
T36 PCIE_TX2_N PCIe TX Data 2 (N) O
T35 PCIE_TX2_P PCIe TX Data 2 (P) O
R34 PCIE_TX3_N PCIe TX Data 3 (N) O
R33 PCIE_TX3_P PCIe TX Data 3 (P) O
P36 PCIE_TX4_N PCIe TX Data 4 (N) O
P35 PCIE_TX4_P PCIe TX Data 4 (P) O
N34 PCIE_TX5_N PCIe TX Data 5 (N) O
Chapter 3: Pin Mapping
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Table 1: PCIe Interface Pin Map (cont'd)
Pin Number Signal Name Description I/O
N33 PCIE_TX5_P PCIe TX Data 5 (P) O
L34 PCIE_TX6_N PCIe TX Data 6 (N) O
L33 PCIE_TX6_P PCIe TX Data 6 (P) O
J34 PCIE_TX7_N PCIe TX Data 7 (N) O
J33 PCIE_TX7_P PCIe TX Data 7 (P) O
H32 PCIE_TX8_N PCIe TX Data 8 (N) O
H31 PCIE_TX8_P PCIe TX Data 8 (P) O
G34 PCIE_TX9_N PCIe TX Data 9 (N) O
G33 PCIE_TX9_P PCIe TX Data 9 (P) O
F32 PCIE_TX10_N PCIe TX Data 10 (N) O
F31 PCIE_TX10_P PCIe TX Data 10 (P) O
E34 PCIE_TX11_N PCIe TX Data 11 (N) O
E33 PCIE_TX11_P PCIe TX Data 11 (P) O
D32 PCIE_TX12_N PCIe TX Data 12 (N) O
D31 PCIE_TX12_P PCIe TX Data 12 (P) O
C34 PCIE_TX13_N PCIe TX Data 13 (N) O
C33 PCIE_TX13_P PCIe TX Data 13 (P) O
B32 PCIE_TX14_N PCIe TX Data 14 (N) O
B31 PCIE_TX14_P PCIe TX Data 14 (P) O
A34 PCIE_TX15_N PCIe TX Data 15 (N) O
A33 PCIE_TX15_P PCIe TX Data 15 (P) O
AH12 PCIE_WAKE_LS PCIe Wake O
DDR4 PL Interface
The DDR4 PL interface is 72 bit (64 bits with 8-bit ECC) and operates at a maximum rate of
DDR2666.
Using the DDR4 PL Interface
• The DDR4 PL interface requires the MIG tool to generate a so IP block for integraon into
the design.
• The memory devices on the board are Micron MT40A512M16LY-062E:E (8 Gb 512Mx16).
• The maximum rate of DDR2666 is a Zynq® UltraScale+™ RFSoC -2E device limitaon.
Chapter 3: Pin Mapping
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DDR4 PL Interface Pins
The following table summarizes the ZU48DR DDR4 PL interface pin map.
Table 2: DDR4 PL Interface Pin Map
Pin Number Signal Name Description I/O
G12 RF_CLK_DDR_N DDR4 Diff Clock Input (N) I
G13 RF_CLK_DDR_P DDR4 Diff Clock Input (P) I
G9 PL_DDR4_1_A0 DDR4 Address 0 O
G6 PL_DDR4_1_A1 DDR4 Address 1 O
J8 PL_DDR4_1_A2 DDR4 Address 2 O
H7 PL_DDR4_1_A3 DDR4 Address 3 O
F9 PL_DDR4_1_A4 DDR4 Address 4 O
K9 PL_DDR4_1_A5 DDR4 Address 5 O
G7 PL_DDR4_1_A6 DDR4 Address 6 O
J7 PL_DDR4_1_A7 DDR4 Address 7 O
J9 PL_DDR4_1_A8 DDR4 Address 8 O
H6 PL_DDR4_1_A9 DDR4 Address 9 O
E13 PL_DDR4_1_A10 DDR4 Address 10 O
H12 PL_DDR4_1_A11 DDR4 Address 11 O
E12 PL_DDR4_1_A12 DDR4 Address 12 O
G14 PL_DDR4_1_A13 DDR4 Address 13 O
E14 PL_DDR4_1_BA0 DDR4 Bank Address 0 O
H13 PL_DDR4_1_BA1 DDR4 Bank Address 1 O
F14 PL_DDR4_1_BG0 DDR4 Bank Group 0 O
C12 PL_DDR4_1_DM0# DDR4 Data Mask 0 O
N14 PL_DDR4_1_DM1# DDR4 Data Mask 1 O
J15 PL_DDR4_1_DM2# DDR4 Data Mask 2 O
G17 PL_DDR4_1_DM3# DDR4 Data Mask 3 O
C23 PL_DDR4_1_DM4# DDR4 Data Mask 4 O
D18 PL_DDR4_1_DM5# DDR4 Data Mask 5 O
J23 PL_DDR4_1_DM6# DDR4 Data Mask 6 O
N20 PL_DDR4_1_DM7# DDR4 Data Mask 7 O
F21 PL_DDR4_1_DM8# DDR4 Data Mask 8 O
A14 PL_DDR4_1_DQ0 DDR4 Data I/O 0 Bidirectional
A11 PL_DDR4_1_DQ1 DDR4 Data I/O 1 Bidirectional
B14 PL_DDR4_1_DQ2 DDR4 Data I/O 2 Bidirectional
C13 PL_DDR4_1_DQ3 DDR4 Data I/O 3 Bidirectional
B13 PL_DDR4_1_DQ4 DDR4 Data I/O 4 Bidirectional
D13 PL_DDR4_1_DQ5 DDR4 Data I/O 5 Bidirectional
A15 PL_DDR4_1_DQ6 DDR4 Data I/O 6 Bidirectional
Chapter 3: Pin Mapping
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Table 2: DDR4 PL Interface Pin Map (cont'd)
Pin Number Signal Name Description I/O
A12 PL_DDR4_1_DQ7 DDR4 Data I/O 7 Bidirectional
N15 PL_DDR4_1_DQ8 DDR4 Data I/O 8 Bidirectional
M13 PL_DDR4_1_DQ9 DDR4 Data I/O 9 Bidirectional
M17 PL_DDR4_1_DQ10 DDR4 Data I/O 10 Bidirectional
L12 PL_DDR4_1_DQ11 DDR4 Data I/O 11 Bidirectional
N17 PL_DDR4_1_DQ12 DDR4 Data I/O 12 Bidirectional
N13 PL_DDR4_1_DQ13 DDR4 Data I/O 13 Bidirectional
M15 PL_DDR4_1_DQ14 DDR4 Data I/O 14 Bidirectional
M12 PL_DDR4_1_DQ15 DDR4 Data I/O 15 Bidirectional
J18 PL_DDR4_1_DQ16 DDR4 Data I/O 16 Bidirectional
J16 PL_DDR4_1_DQ17 DDR4 Data I/O 17 Bidirectional
H17 PL_DDR4_1_DQ18 DDR4 Data I/O 18 Bidirectional
K16 PL_DDR4_1_DQ19 DDR4 Data I/O 19 Bidirectional
J19 PL_DDR4_1_DQ20 DDR4 Data I/O 20 Bidirectional
L17 PL_DDR4_1_DQ21 DDR4 Data I/O 21 Bidirectional
K17 PL_DDR4_1_DQ22 DDR4 Data I/O 22 Bidirectional
H16 PL_DDR4_1_DQ23 DDR4 Data I/O 23 Bidirectional
E18 PL_DDR4_1_DQ24 DDR4 Data I/O 24 Bidirectional
F16 PL_DDR4_1_DQ25 DDR4 Data I/O 25 Bidirectional
G18 PL_DDR4_1_DQ26 DDR4 Data I/O 26 Bidirectional
E16 PL_DDR4_1_DQ27 DDR4 Data I/O 27 Bidirectional
H18 PL_DDR4_1_DQ28 DDR4 Data I/O 28 Bidirectional
G15 PL_DDR4_1_DQ29 DDR4 Data I/O 29 Bidirectional
E17 PL_DDR4_1_DQ30 DDR4 Data I/O 30 Bidirectional
F15 PL_DDR4_1_DQ31 DDR4 Data I/O 31 Bidirectional
C22 PL_DDR4_1_DQ32 DDR4 Data I/O 32 Bidirectional
A21 PL_DDR4_1_DQ33 DDR4 Data I/O 33 Bidirectional
B24 PL_DDR4_1_DQ34 DDR4 Data I/O 34 Bidirectional
C20 PL_DDR4_1_DQ35 DDR4 Data I/O 35 Bidirectional
C21 PL_DDR4_1_DQ36 DDR4 Data I/O 36 Bidirectional
B20 PL_DDR4_1_DQ37 DDR4 Data I/O 37 Bidirectional
A24 PL_DDR4_1_DQ38 DDR4 Data I/O 38 Bidirectional
A20 PL_DDR4_1_DQ39 DDR4 Data I/O 39 Bidirectional
C16 PL_DDR4_1_DQ40 DDR4 Data I/O 40 Bidirectional
C17 PL_DDR4_1_DQ41 DDR4 Data I/O 41 Bidirectional
D16 PL_DDR4_1_DQ42 DDR4 Data I/O 42 Bidirectional
B19 PL_DDR4_1_DQ43 DDR4 Data I/O 43 Bidirectional
D15 PL_DDR4_1_DQ44 DDR4 Data I/O 44 Bidirectional
A19 PL_DDR4_1_DQ45 DDR4 Data I/O 45 Bidirectional
Chapter 3: Pin Mapping
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Table 2: DDR4 PL Interface Pin Map (cont'd)
Pin Number Signal Name Description I/O
A16 PL_DDR4_1_DQ46 DDR4 Data I/O 46 Bidirectional
A17 PL_DDR4_1_DQ47 DDR4 Data I/O 47 Bidirectional
L24 PL_DDR4_1_DQ48 DDR4 Data I/O 48 Bidirectional
H23 PL_DDR4_1_DQ49 DDR4 Data I/O 49 Bidirectional
J21 PL_DDR4_1_DQ50 DDR4 Data I/O 50 Bidirectional
H22 PL_DDR4_1_DQ51 DDR4 Data I/O 51 Bidirectional
K24 PL_DDR4_1_DQ52 DDR4 Data I/O 52 Bidirectional
G23 PL_DDR4_1_DQ53 DDR4 Data I/O 53 Bidirectional
G22 PL_DDR4_1_DQ54 DDR4 Data I/O 54 Bidirectional
H21 PL_DDR4_1_DQ55 DDR4 Data I/O 55 Bidirectional
L21 PL_DDR4_1_DQ56 DDR4 Data I/O 56 Bidirectional
L20 PL_DDR4_1_DQ57 DDR4 Data I/O 57 Bidirectional
M20 PL_DDR4_1_DQ58 DDR4 Data I/O 58 Bidirectional
M19 PL_DDR4_1_DQ59 DDR4 Data I/O 59 Bidirectional
N19 PL_DDR4_1_DQ60 DDR4 Data I/O 60 Bidirectional
L19 PL_DDR4_1_DQ61 DDR4 Data I/O 61 Bidirectional
L22 PL_DDR4_1_DQ62 DDR4 Data I/O 62 Bidirectional
L23 PL_DDR4_1_DQ63 DDR4 Data I/O 63 Bidirectional
E22 PL_DDR4_1_DQ64 DDR4 Data I/O 64 (ECC) Bidirectional
G20 PL_DDR4_1_DQ65 DDR4 Data I/O 65 (ECC) Bidirectional
E23 PL_DDR4_1_DQ66 DDR4 Data I/O 66 (ECC) Bidirectional
E21 PL_DDR4_1_DQ67 DDR4 Data I/O 67 (ECC) Bidirectional
F24 PL_DDR4_1_DQ68 DDR4 Data I/O 68 (ECC) Bidirectional
F20 PL_DDR4_1_DQ69 DDR4 Data I/O 69 (ECC) Bidirectional
E24 PL_DDR4_1_DQ70 DDR4 Data I/O 70 (ECC) Bidirectional
D21 PL_DDR4_1_DQ71 DDR4 Data I/O 71 (ECC) Bidirectional
C15 PL_DDR4_1_DQS0 DDR4 Data Strobe 0 (P) Bidirectional
B15 PL_DDR4_1_DQS0# DDR4 Data Strobe 0 (N) Bidirectional
L15 PL_DDR4_1_DQS1 DDR4 Data Strobe 1 (P) Bidirectional
L14 PL_DDR4_1_DQS1# DDR4 Data Strobe 1 (N) Bidirectional
K19 PL_DDR4_1_DQS2 DDR4 Data Strobe 2 (P) Bidirectional
K18 PL_DDR4_1_DQS2# DDR4 Data Strobe 2 (N) Bidirectional
G19 PL_DDR4_1_DQS3 DDR4 Data Strobe 3 (P) Bidirectional
F19 PL_DDR4_1_DQS3# DDR4 Data Strobe 3 (N) Bidirectional
B22 PL_DDR4_1_DQS4 DDR4 Data Strobe 4 (P) Bidirectional
A22 PL_DDR4_1_DQS4# DDR4 Data Strobe 4 (N) Bidirectional
B18 PL_DDR4_1_DQS5 DDR4 Data Strobe 5 (P) Bidirectional
B17 PL_DDR4_1_DQS5# DDR4 Data Strobe 5 (N) Bidirectional
J20 PL_DDR4_1_DQS6 DDR4 Data Strobe 6 (P) Bidirectional
Chapter 3: Pin Mapping
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Table 2: DDR4 PL Interface Pin Map (cont'd)
Pin Number Signal Name Description I/O
H20 PL_DDR4_1_DQS6# DDR4 Data Strobe 6 (N) Bidirectional
K21 PL_DDR4_1_DQS7 DDR4 Data Strobe 7 (P) Bidirectional
K22 PL_DDR4_1_DQS7# DDR4 Data Strobe 7 (N) Bidirectional
D23 PL_DDR4_1_DQS8 DDR4 Data Strobe 8 (P) Bidirectional
D24 PL_DDR4_1_DQS8# DDR4 Data Strobe 8 (N) Bidirectional
K12 PL_DDR4_1_ODT DDR4 On Die Termination O
K10 PL_DDR4_1_PAR DDR4 Parity O
E11 PL_DDR4_1_RAS# DDR4 Row Address Strobe O
F12 PL_DDR4_1_CAS# DDR4 Column Address Strobe O
K11 PL_DDR4_1_ACT# DDR4 Activate O
H8 PL_DDR4_1_CK DDR4 Clock (P) O
G8 PL_DDR4_1_CK# DDR4 Clock (N) O
K13 PL_DDR4_1_CKE DDR4 Clock Enable O
F11 PL_DDR4_1_CS# DDR4 Chip Select O
D14 PL_DDR4_1_WE# DDR4 Write Enable O
J10 PL_DDR4_1_ALERT# DDR4 Alert I
J14 PL_DDR4_1_RST# DDR4 Reset O
J13 PL_DDR4_1_TEN DDR4 Test Enable O
DDR4 PS Interface
The DDR4 PS interface is 40 bit (32 bits with 8-bit ECC) and operates at a maximum rate of
DDR2400.
Using the DDR4 PS Interface
• The DDR4 PS interface is supported with a dedicated IP block that must be enabled in the
design.
• The memory devices on the board are Micron MT40A512M16LY-062E:E (8 Gb 512Mx16).
• The maximum rate of DDR2400 is a Zynq® UltraScale+™ RFSoC -2E device limitaon.
DDR4 PS Interface Pins
The following table summarizes the ZU48DR DDR4 PS interface pin map.
Chapter 3: Pin Mapping
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Table 3: DDR4 PS Interface Pin Map
Pin Number Signal Name Description I/O
AV31 PS_DDR4_1_A0 DDR4 Address 0 O
AW28 PS_DDR4_1_A1 DDR4 Address 1 O
AV28 PS_DDR4_1_A2 DDR4 Address 2 O
AU29 PS_DDR4_1_A3 DDR4 Address 3 O
AW31 PS_DDR4_1_A4 DDR4 Address 4 O
AU28 PS_DDR4_1_A5 DDR4 Address 5 O
AL29 PS_DDR4_1_A6 DDR4 Address 6 O
AM30 PS_DDR4_1_A7 DDR4 Address 7 O
AM29 PS_DDR4_1_A8 DDR4 Address 8 O
AP29 PS_DDR4_1_A9 DDR4 Address 9 O
AT31 PS_DDR4_1_A10 DDR4 Address 10 O
AT32 PS_DDR4_1_A11 DDR4 Address 11 O
AT30 PS_DDR4_1_A12 DDR4 Address 12 O
AU32 PS_DDR4_1_A13 DDR4 Address 13 O
AN30 PS_DDR4_1_BA0 DDR4 Bank Address 0 O
AM32 PS_DDR4_1_BA1 DDR4 Bank Address 1 O
AN32 PS_DDR4_1_BG0 DDR4 Bank Group 0 O
AU23 PS_DDR4_1_DM0# DDR4 Data Mask 0 O
AT27 PS_DDR4_1_DM1# DDR4 Data Mask 1 O
AL24 PS_DDR4_1_DM2# DDR4 Data Mask 2 O
AM27 PS_DDR4_1_DM3# DDR4 Data Mask 3 O
AR38 PS_DDR4_1_DM4# DDR4 Data Mask 4 O
AV22 PS_DDR4_1_DQ0 DDR4 Data I/O 0 Bidirectional
AW24 PS_DDR4_1_DQ1 DDR4 Data I/O 1 Bidirectional
AW23 PS_DDR4_1_DQ2 DDR4 Data I/O 2 Bidirectional
AV25 PS_DDR4_1_DQ3 DDR4 Data I/O 3 Bidirectional
AR23 PS_DDR4_1_DQ4 DDR4 Data I/O 4 Bidirectional
AW25 PS_DDR4_1_DQ5 DDR4 Data I/O 5 Bidirectional
AV23 PS_DDR4_1_DQ6 DDR4 Data I/O 6 Bidirectional
AR24 PS_DDR4_1_DQ7 DDR4 Data I/O 7 Bidirectional
AP26 PS_DDR4_1_DQ8 DDR4 Data I/O 8 Bidirectional
AV27 PS_DDR4_1_DQ9 DDR4 Data I/O 9 Bidirectional
AT25 PS_DDR4_1_DQ10 DDR4 Data I/O 10 Bidirectional
AW26 PS_DDR4_1_DQ11 DDR4 Data I/O 11 Bidirectional
AR27 PS_DDR4_1_DQ12 DDR4 Data I/O 12 Bidirectional
AU27 PS_DDR4_1_DQ13 DDR4 Data I/O 13 Bidirectional
AU25 PS_DDR4_1_DQ14 DDR4 Data I/O 14 Bidirectional
AV26 PS_DDR4_1_DQ15 DDR4 Data I/O 15 Bidirectional
AK24 PS_DDR4_1_DQ16 DDR4 Data I/O 16 Bidirectional
Chapter 3: Pin Mapping
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Table 3: DDR4 PS Interface Pin Map (cont'd)
Pin Number Signal Name Description I/O
AM25 PS_DDR4_1_DQ17 DDR4 Data I/O 17 Bidirectional
AP24 PS_DDR4_1_DQ18 DDR4 Data I/O 18 Bidirectional
AN23 PS_DDR4_1_DQ19 DDR4 Data I/O 19 Bidirectional
AK23 PS_DDR4_1_DQ20 DDR4 Data I/O 20 Bidirectional
AP23 PS_DDR4_1_DQ21 DDR4 Data I/O 21 Bidirectional
AP25 PS_DDR4_1_DQ22 DDR4 Data I/O 22 Bidirectional
AN25 PS_DDR4_1_DQ23 DDR4 Data I/O 23 Bidirectional
AN27 PS_DDR4_1_DQ24 DDR4 Data I/O 24 Bidirectional
AK27 PS_DDR4_1_DQ25 DDR4 Data I/O 25 Bidirectional
AN26 PS_DDR4_1_DQ26 DDR4 Data I/O 26 Bidirectional
AN28 PS_DDR4_1_DQ27 DDR4 Data I/O 27 Bidirectional
AK26 PS_DDR4_1_DQ28 DDR4 Data I/O 28 Bidirectional
AK28 PS_DDR4_1_DQ29 DDR4 Data I/O 29 Bidirectional
AL25 PS_DDR4_1_DQ30 DDR4 Data I/O 30 Bidirectional
AM28 PS_DDR4_1_DQ31 DDR4 Data I/O 31 Bidirectional
AR39 PS_DDR4_1_DQ32 DDR4 Data I/O 32 (ECC) Bidirectional
AP38 PS_DDR4_1_DQ33 DDR4 Data I/O 33 (ECC) Bidirectional
AP39 PS_DDR4_1_DQ34 DDR4 Data I/O 34 (ECC) Bidirectional
AP36 PS_DDR4_1_DQ35 DDR4 Data I/O 35 (ECC) Bidirectional
AT39 PS_DDR4_1_DQ36 DDR4 Data I/O 36 (ECC) Bidirectional
AP35 PS_DDR4_1_DQ37 DDR4 Data I/O 37 (ECC) Bidirectional
AR36 PS_DDR4_1_DQ38 DDR4 Data I/O 38 (ECC) Bidirectional
AT36 PS_DDR4_1_DQ39 DDR4 Data I/O 39 (ECC) Bidirectional
AT24 PS_DDR4_1_DQS0 DDR4 Data Strobe 0 (P) Bidirectional
AU24 PS_DDR4_1_DQS0# DDR4 Data Strobe 0 (N) Bidirectional
AR26 PS_DDR4_1_DQS1 DDR4 Data Strobe 1 (P) Bidirectional
AT26 PS_DDR4_1_DQS1# DDR4 Data Strobe 1 (N) Bidirectional
AM23 PS_DDR4_1_DQS2 DDR4 Data Strobe 2 (P) Bidirectional
AM24 PS_DDR4_1_DQS2# DDR4 Data Strobe 2 (N) Bidirectional
AL26 PS_DDR4_1_DQS3 DDR4 Data Strobe 3 (P) Bidirectional
AL27 PS_DDR4_1_DQS3# DDR4 Data Strobe 3 (N) Bidirectional
AR37 PS_DDR4_1_DQS4 DDR4 Data Strobe 4 (P) Bidirectional
AT37 PS_DDR4_1_DQS4# DDR4 Data Strobe 4 (N) Bidirectional
AV32 PS_DDR4_1_ODT DDR4 On Die Termination O
AN31 PS_DDR4_1_PAR DDR4 Parity O
AP28 PS_DDR4_1_RAS# DDR4 Row Address Strobe O
AP30 PS_DDR4_1_CAS# DDR4 Column Address Strobe O
AL30 PS_DDR4_1_ACT# DDR4 Activate O
AU30 PS_DDR4_1_CK DDR4 Clock (P) O
Chapter 3: Pin Mapping
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Table 3: DDR4 PS Interface Pin Map (cont'd)
Pin Number Signal Name Description I/O
AV30 PS_DDR4_1_CK# DDR4 Clock (N) O
AW30 PS_DDR4_1_CKE DDR4 Clock Enable O
AW29 PS_DDR4_1_CS# DDR4 Chip Select O
AR28 PS_DDR4_1_WE# DDR4 Write Enable O
AL32 PS_DDR4_1_ALERT# DDR4 Alert I
AM33 PS_DDR4_1_RST# DDR4 Reset O
Special Functions
FPGA Program Flash
Flash storage for FPGA images on the T2 card is implemented in dual-QSPI mode (8 bits). The
following signals comprise this interface:
•Chip selects: RF_QSPI_LWR_CS# and RF_QSPI_UPR_CS#
•Data: RF_QSPI_LWR_DQ[3:0] and RF_QSPI_UPR_DQ[3:0]
•Clocks: RF_QSPI_LWR_CLK and RF_QSPI_UPR_CLK
Addional details are as follows:
• The dual-QSPI mode ash has been implemented with two 2 Gb SPI NOR ash devices
(Micron MT25QU02GCBB8E12-0AAT).
• The MT25QU02GCBB8E12-0AAT NOR ash devices are automove grade for thermal
design reasons.
• The ash storage supports a user image and a fallback image.
• The T2 card is shipped with a fallback image that cannot be overwrien (the password is kept
with Xilinx manufacturing).
I2C Bus to Satellite Controller
The I2C bus signals to the Zynq® UltraScale+™ RFSoC are PS_SOC_SCL and PS_SOC_SDA.
These signals are used to support data transfers between the SC and RFSoC in support of the
following funcons:
•In-band telemetry: Provides the host access to board power and temperature telemetry data
using PCIe technology.
Chapter 3: Pin Mapping
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•In-band SC rmware update: Allows the SC rmware to be updated using PCIe technology.
The I2C interface is connected to MIO pins of the Zynq® UltraScale+™ RFSoC PS, meaning that
an integrated IP soluon is available. The I2C interface must be operated in slave mode and
cannot be a master because the SC is the master, and drives an SCL clock.
Reset Request Power Reduction
It might be necessary for the SC to request the Zynq® UltraScale+™ RFSoC to reduce power if a
temperature or power consumpon threshold has been reached. This request is made with the
following handshake signals:
•RF_CPU_RST: This signal is asserted by the SC to indicate to the Zynq® UltraScale+™ RFSoC
to reduce the 5G workload power. The Zynq® UltraScale+™ RFSoC must keep the PCIe
interface funconal to enable any maintenance on telemetry operaons with the ost.
•RF_RST_REQ: This signal is asserted by the Zynq® UltraScale+™ RFSoC to acknowledge the
power reducon request by the SC, and to avoid a fatal power cuto protecon mechanism.
The SC is always powered.
UART – Maintenance Port Accessible
A UART port on the Zynq® UltraScale+™ RFSoC, accessible through the maintenance port, can
be used for development purposes. The UART signals are as follows:
•RF_DBG_RX: Maintenance port UART receive
•RF_DBG_TX: Maintenance port UART transmit
The UART port is connected to MIO pins of the Zynq® UltraScale+™ RFSoC PS, meaning that an
integrated IP soluon is available.
To use the UART through the maintenance port, you need a DMB II dongle. Refer to Chapter 4:
Maintenance Port for more details.
General Purpose Signals
•RF_LED: A yellow LED is available as a general purpose indicator. It is located on the I/O
bracket immediately next to the green power-on LED.
Special Function Pins
The following table summarizes the special funcons pin map.
Chapter 3: Pin Mapping
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Table 4: Special Function Pin Map
Pin Number Signal Name Description I/O
R26 RF_QSPI_LWR_CLK QSPI Lower Clock O
AA26 RF_QSPI_LWR_CS# QSPI Lower Chip Select O
V26 RF_QSPI_LWR_DQ0 QSPI Lower Data 0 Bidirectional
P26 RF_QSPI_LWR_DQ1 QSPI Lower Data 1 Bidirectional
Y26 RF_QSPI_LWR_DQ2 QSPI Lower Data 2 Bidirectional
T27 RF_QSPI_LWR_DQ3 QSPI Lower Data 3 Bidirectional
N29 RF_QSPI_UPR_CLK QSPI Upper Clock O
T26 RF_QSPI_UPR_CS# QSPI Upper Chip Select O
U27 RF_QSPI_UPR_DQ0 QSPI Upper Data 0 Bidirectional
R27 RF_QSPI_UPR_DQ1 QSPI Upper Data 1 Bidirectional
V27 RF_QSPI_UPR_DQ2 QSPI Upper Data 2 Bidirectional
P28 RF_QSPI_UPR_DQ3 QSPI Upper Data 3 Bidirectional
H26 PS_SOC_SCL I2C Bus (to SC & Maintenance Port) I
H27 PS_SOC_SDA I2C Bus (to SC & Maintenance Port) Bidirectional
L25 MSP_RF_GPIO GPIO: SC --> RFSoC PS I
N26 RF_MSP_GPIO GPIO:RFSOC PS --> SC O
AN12 RF_CPU_RST Reset request: SC --> RFSoC I
AM14 RF_RST_REQ Reset request: RFSoC -- >SC O
M26 RF_DBG_RX Maintenance port UART Rx I
J25 RF_DBG_TX Maintenance port UART Tx O
AM10 RF_LED General Purpose LED O
AL10 DNU DNU NA
Chapter 3: Pin Mapping
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