Ampcontrol iMAC2 Use and care manual

Version: 2 –October 2018
Designed and Manufactured in Australia by Ampcontrol Pty Ltd
IntegratedMonitoringandControlSystem
iMAC2ControllerModbusTCP/IPCommunicationsManual

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WARNING!
The warning symbol highlights a potential risk of injury or death.
Please share these warnings with other operators.
CAUTION!
The caution symbol highlights a potential risk of damage to
equipment.
Please share these cautions with other operators.
NOTE
The note symbol highlights key information.
Please share these notes with other operators.
ENVIRO
The enviro (environmental) symbol highlights areas which may have an
impact on the surrounding fauna and/or flora.

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Copyright Notice
The Ampcontrol iMAC Integrated Monitoring and Control system described in this document is the property
of AMPCONTROL PTY LTD. It is furnished under a license agreement and is to be used only in
accordance with the terms of the agreement.
No part of the hardware or documentation may be reproduced, transmitted, transcribed, stored in a retrieval
system, or translated into any language or computer language, in any form or by any means, without prior
written permission of AMPCONTROL PTY LTD.
The iMAC signalling technique is protected by patent.
Disclaimer
While every effort has been made to assure the accuracy and clarity of this document, AMPCONTROL PTY
LTD assumes no liability resulting from any omissions in this document, or from misuse of the information
obtained herein. The information in this document has been carefully checked and is believed to be entirely
reliable with all of the necessary information included. AMPCONTROL PTY LTD reserves the right to make
changes to any products described herein to improve reliability, function, or design, and reserves the right to
revise this document and make changes from time to time in content hereof with no obligation to notify any
persons of revisions or changes. AMPCONTROL PTY LTD does not assume any liability arising out of the
application or any use of any product or circuit described herein; neither does it convey license under its
patent rights or the rights of others.
Before You Begin
Thank you for purchasing the Ampcontrol iMAC System.
WARNING!
In the interests of safety and correct equipment operation, please
take the time to read and understand the content in this manual.
This manual version V2 pertains to iMAC2 Controller Operating System
Firmware v4.1. For superseded Operating System Firmware’s v3.5 or
less, please refer to V1 of this manual.
Ampcontrol Contact Details
7 Billbrooke Close, Cameron Park, NSW, 2285
P [phone] | F [phone]
EMAIL: [e-mail]
WEB: ampcontrolgroup.com

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TABLE OF CONTENTS
DOCUMENT SCOPE.................................................................................................5
Document Scope..............................................................................................5
Supplementary Documents ..............................................................................5
1.2.1 System Documentation...........................................................................5
1.2.2 Module Documentation...........................................................................5
iMAC2 CONTROLLER ETHERNET COMMUNICATIONS OVERVIEW .....................6
Specifications...................................................................................................6
Connecting to the Ethernet Port for the First Time............................................7
Modbus TCP/IP Protocol................................................................................10
THE iMAC2 CONTROLLER’S DATA POINT TABLE................................................11
Data Point Table.............................................................................................11
System Data Segment....................................................................................12
3.2.1 System Data Register...........................................................................13
3.2.2 System Status Register ........................................................................14
3.2.3 EOL Series Resistance Register...........................................................15
3.2.4 Line Shunt Resistance Register............................................................15
Module Data Segment....................................................................................16
3.3.1 Module Data Register...........................................................................16
3.3.2 Module Status Register.........................................................................17
3.3.3 Module Series Resistance Register......................................................18
3.3.4 Module Error Register...........................................................................18
System Runtime Segment..............................................................................19
3.4.1 System Control Register.......................................................................19
3.4.2 System ID and LED Control Register....................................................21
3.4.3 EOL Serial Number Register.................................................................21
3.4.4 L1 Data Block Just Complete Register..................................................22
3.4.5 Application (SLP) Software Loop Timer Counter Register.....................22
3.4.6 Module Rollcall Registers .....................................................................23
3.4.7 Remote Key Press Register..................................................................26
3.4.8 Message System Page Control Register...............................................26
3.4.9 Block Request Register ........................................................................27
3.4.10 EOL Offline Count Register.................................................................27
3.4.11 EOL Clash Count Register..................................................................27

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General Buffer Segments...............................................................................28
Non-Volatile Memory (NVM) System Variables Segment ...............................29
3.6.1 Serial Communication Setup Registers.................................................30
3.6.2 SLP Fault Register................................................................................31
User Non-Volatile Memory (NVM) Segment ...................................................31
Controller Information Segment......................................................................32
3.8.1 Controller Hardware Flags Register......................................................33
3.8.2 Controller Temperature Register...........................................................33
3.8.3 Mimic Keypress Register......................................................................34
3.8.4 LCD Display Data Registers .................................................................35
3.8.5 Unit Name Registers.............................................................................39
3.8.6 Hardware Version Registers.................................................................40
3.8.7 Firmware Version Registers..................................................................41
3.8.8 Software Version Registers...................................................................42
3.8.9 Application (SLP) Software Registers...................................................43
3.8.10 Boot Loader Name..............................................................................44
3.8.11 Boot Loader Revision..........................................................................44
3.8.12 Hardware Name..................................................................................45
3.8.13 Hardware Revision .............................................................................45
3.8.14 Serial Number.....................................................................................46
3.8.15 Software Name...................................................................................47
3.8.16 Software Revision...............................................................................47
TABLE OF FIGURES
Figure 2.1: Location of the Ethernet Communications Port............................................6
Figure 2.2: Location of Ethernet Reset Switch...............................................................7
Figure 2.3: Updating the Ethernet Port Settings of the Connectable Device..................8
Figure 2.4: Updating the iMAC2 Controller Ethernet Port Settings.................................9
Figure 3.1: iMAC2 Controller Data Point Table............................................................11
Figure 3.2: Sub-sections of the iMAC2 Controller’s Data Point Table ..........................12
Figure 3.3: LCD Display Data Character Map..............................................................35
Figure 3.4 Recommended special character Unicode substitutions.............................35
Figure 3.5: Character Map for iMAC2 Controller LCD Screen .....................................36

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DOCUMENT SCOPE
Document Scope
This document is intended to provide a detailed explanation of the communications protocols supported by
the iMAC2 Controller’s Ethernet port.
This document is not intended to provide information on the operation of the overall iMAC System, individual
modules or instruction on programming the iMAC2 Controller or modules. Please refer the relevant
supplementary documents for this information.
Supplementary Documents
The iMAC2 Controller Ethernet Communications Manual is intended to be read in conjunction with the
following documents:
1.2.1 System Documentation
IMAC2B009 iMAC2 System User Manual
IMAC2B011 iMAC2 Controller Web Interface Manual
IMACB094 iMAC System Installation Requirements
IMACB182 iMAC SIL Emergency Stop Qualification
IMACB005 iMAC Module Programming Manual
1.2.2 Module Documentation
IMACB003 iMAC RO4 Module Technical Datasheet
IMACB018 iMAC LPU Module Technical Datasheet
IMACB020 iMAC DI8 Module Technical Datasheet
IMACB045 iMAC IIM Module Technical Datasheet
IMACB046 iMAC DI4 Module Technical Datasheet
IMACB047 iMAC EOL/MEOL Module Technical Datasheet
IMACB060 iMAC LED4 Module Technical Datasheet
IMACB061 iMAC SSW Module Technical Datasheet
IMACB062 iMAC SQM Module Technical Datasheet
IMACB066 iMAC AIM Module Technical Datasheet
IMACB067 iMAC RTD1 Module Technical Datasheet
IMACB141 iMAC ARM Module Technical Datasheet
IMACB142 iMAC CRM Module Technical Datasheet
IMACB143 iMAC EMM Module Technical Datasheet
IMACB144 iMAC GRM Module Technical Datasheet
IMACB146 iMAC IRK Keypad Technical Datasheet
IMACB147 iMAC PIM Module Technical Datasheet
IMACB148 iMAC SIM-G Module Technical Datasheet
IMACB149 iMAC SIM-G2 Module Technical Datasheet
IMACB150 iMAC SIM-T Module Technical Datasheet
IMACB151 iMAC MLB Barrier Technical Datasheet
IMACB152 iMAC SLB Barrier Technical Datasheet
IMACB154 iMAC SIM-P Module Technical Datasheet
IMACB172 iMAC LIM Module Technical Datasheet

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iMAC2 CONTROLLER ETHERNET COMMUNICATIONS OVERVIEW
The iMAC2 Controller is equipped with an Ethernet port and a serial communication port. This manual
details the use of the Ethernet port. For information pertaining to the use of the serial communications
port, refer to the IMACB153 iMAC Controller Serial Communications Manual.
NOTE
The Ethernet port is a read only communications port. The iMAC2
Controller has been manufactured in this way to maintain the SIL
“Proven in Use” statistics of the previous iMAC Controller.
Specifications
Figure 2.1: Location of the Ethernet Communications Port
Table 1: Ethernet Communications Port Specifications
Ethernet TCP/IP Port
Available Interfaces
RJ45 10/100MB
Auto Negotiation
Applicable Standards
IEEE 802.3u, IEEE 802.3x
Cable Requirements
10BASE-T: UTP category 3, 4, 5 cable (maximum 100m)
100BASE-TX: UTP category 5, 5e cable (maximum 100m)
EIA/TIA-568 100Ω STP (maximum 100m)
Supported Protocols
MODBUS TCP/IP (Port 502), NTP (for time synchronisation),
Webserver (for configuration, data viewing and diagnostic functions)
Maximum Request Rate
100ms
Recommended Response
Timeout
200ms
Maximum Concurrent Web
Connections
The iMAC2 Controller allows four users to access the web server.
Ethernet Communications Port
Name
Link Activity
Link Speed
Operation
On when valid link is detected. Blinks when
activity is detected.
On when operating speed is 100Mbps. Off
when the line speed is 10Mbps, or during line
isolation.
Link Activity LED
(Yellow)
Link Speed LED
(Green)
Colour
Yellow
Green

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Connecting to the Ethernet Port for the First Time
The iMAC2 Controller’s factory default Ethernet IPv4 settings are as follows:
Table 2: Default Ethernet Communications Port Settings
Default Ethernet IPv4 Settings
IP Address
10.1.1.10
Subnet Mask
255.255.255.0
If the Controller’s IPv4 settings have been changed, they can be restored to the factory default settings by
pressing the iMAC2 Controller’s Ethernet Reset button for 4 seconds (The internal iMAC2 Controller status
LED will turn on solid while the reset button is depressed, after 4 seconds the LED will change to a fast flash
to indicate settings have been reset to default, after which the button can then be released).
Figure 2.2: Location of Ethernet Reset Switch
Ethernet Reset
Switch

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The iMAC2 Controller’s Ethernet port settings are not configurable via the HMI; they must be altered using
the iMAC2 Web Interface. The Controller’s web server can be accessed using a one-to-one Ethernet
connection with an Ethernet enabled device. Temporarily configure your device’s Ethernet port as follows:
Figure 2.3: Updating the Ethernet Port Settings of the Connectable Device
Once the network adaptor of the external device has been configured as shown in Figure 2.3, connect the
iMAC2 Controller’s Ethernet port directly to your device’s Ethernet port, the iMAC 2 Controller should then
be able to be pinged at 10.1.1.10. Once a successful ping has been performed, open a web browser
(Chrome recommended) and enter the iMAC2 Controller’s IP address into the address bar: http://10.1.1.10;
the iMAC2 Controller web pages should load within a few seconds.

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Navigate to the Ethernet Settings page to configure the IP settings for the iMAC2 Controller:
Figure 2.4: Updating the iMAC2 Controller Ethernet Port Settings
For information on this process, refer to the IMAC2B011 iMAC2 Controller Web Interface Manual.

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Modbus TCP/IP Protocol
The iMAC2 Controller uses industrystandardModbus TCP/IP protocol for exchanging data with compatible
Ethernet devices.
The iMAC2 Controller facilitates a Modbus Slave (server) device.
The default Modbus TCP/IP port number is 502.
The iMAC2 Controller supports up to two Modbus Master (client) device connections.
A single Modbus command is supported by the iMAC2 Controller’s Ethernet TCP/IP port for transferring
register data from the iMAC2 Controller to a compatible Modbus Master (client) device:
Read Holding Registers (03)
A summary of the supported command is as follows:
Read Holding Registers (03)
This command reads registers within the iMAC address space ($0000..$06A1) into the master
device.
Illegal Commands (01, 02, 04, 05, 06 to 127)
The iMAC response to any of these commands is a Modbus exception.
To all other commands (0,128...255) the iMAC controller will not respond.

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THE iMAC2 CONTROLLER’S DATA POINT TABLE
The iMAC2 Controller’s Data Point Table is used for the exchange of all serial and Ethernet communication
data. The Data Point Table is a list of 1697 16-bit registers with each data register having its own address in
the range 0 to 1697 (0000h to 06A1h).
Register addresses >=1536 (600h) can be accessed via the Ethernet port, register address <=1535 (5FFh)
are accessible by both Serial and Ethernet ports.
Data Point Table
Figure 3.1: iMAC2 Controller Data Point Table
The Data Point Table is broken up into a number of segments: System Data, Module Data, System Runtime
Variables, Non-Volatile System Variables, Non-Volatile User Memory, Controller Information & two General
Buffer segments. These are explained in detail in the following sections.
Modbus Address
Block: 000h-0FFh
System
Data Register
Decimal 0 1 2 3 4 5
- - - - - - - - - - - - - - - - - - - - - - - - -
253 254 255
Hexadecimal 0h 1h 2h 3h 4h 5h
- - - - - - - - - - - - - - - - - - - - - - - - -
FDh FEh FFh
Modbus Address
Block: 100h-1FFh
System
Status
Decimal 256 257 258 259 260 261
- - - - - - - - - - - - - - - - - - - - - - - - -
509 510 511
Hexadecimal 100h 101h 102h 103h 104h 105h
- - - - - - - - - - - - - - - - - - - - - - - - -
1FDh 1FEh 1FFh
Modbus Address
Block: 200h-2FFh
EOL Module
Resistance
Decimal 512 513 514 515 516 507
- - - - - - - - - - - - - - - - - - - - - - - - -
765 766 767
Hexadecimal 200h 201h 202h 203h 204h 205h
- - - - - - - - - - - - - - - - - - - - - - - - -
2FDh 2FEh 2FFh
Modbus Address
Block: 300h-3FFh
Line Shunt
Decimal 768 769 770 771 772 773
- - - - - - - - - - - - - - - - - - - - - - - - -
1021 1022 1023
Hexadecimal 300h 301h 302h 303h 304h 305h
- - - - - - - - - - - - - - - - - - - - - - - - -
3FDh 3FEh 3FFh
Modbus Address
Block: 400h-4FFh
System Runtime
Variables
OneShot WORDBIT WORD
Decimal 1024-1046
Hexadecimal 400h-416h
Modbus Address
Block: 500h-5FFh
Decimal
Hexadecimal
Modbus Address
Block: 600h-651h
Decimal
Hexadecimal
600h-6A1h
iMAC2 Controller Data Point Table
Application Software General Buffer 580h – 5FFh
1408-1535
580h-5FFh
NVM System Variables
500h-51Fh
1280-1311
500h-51Fh
User NVM
520h-57Fh
Application Software General Buffer 480h – 4FFh
1152-1279
480h-4FFh
255x Module Status Registers (Modbus Table Address = iMAC Module's Address + 256)
Modbus Table Addresses: 101h-1FFh
255x Module Data Registers (Modbus Table Address = iMAC Module's Address)
Modbus Table Addresses: 001h-0FFh
255x Module Resistance Registers (Modbus Table Address = iMAC Module's Address + 512)
Modbus Table Addresses: 201h – 2FFh
255x Module Error Registers (Modbus Table Address = iMAC Module's Address + 768)
Modbus Table Addresses: 301h – 3FFh
1312-1407
520h-57Fh
1047-1151
417h-47Eh
Controller Information (Ethernet Port Only)
600h-6A1h
1536-1697

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Figure 3.2: Sub-sections of the iMAC2 Controller’s Data Point Table
System Data Segment
The System Data is a group of 4 registers that are addressed as follows:
Address
Register Content
Decimal
Hexadecimal
0
000h
System Data (see bit definitions)
256
100h
System Status (see bit definitions)
512
200h
EOL Module Resistance
768
300h
L1 Fieldbus Shunt Resistance
System
Data
System Runtime
Variables
Non-Volatile
System Variables
Non-Volatile
User Memory
General Buffer
Module Data
Controller Information
(Ethernet Port Only)

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3.2.1 System Data Register
The bits within the System Data register are defined by the Controller’s application (SLP) software. Typical
bit definitions are as below. Please refer to your specific application (SLP) software for actual definitions.
WARNING!
CRM and ARM modules require specific application (SLP) software
to operate, please ensure that your application (SLP) software is
configured correctly if you require CRM and/or ARM functions
Address 0 (000h)
System Data Register
Address
Bit
Name
Description
r/w
SLP Tag
Dec.
Hex.
0
000h
0
CRM Output/
GRM0 Output
Set by specific application (SLP) software
when the CR is closed. CRM or GRM
modules can output this information. LED4 or
RO4 modules can output this information if
set to Address 0
w
1
ARM Output/
GRM1 Output
Set by specific application (SLP) software
when the AR is closed. ARM or GRM
modules can output this information. LED4 or
RO4 modules can output this information if
set to Address 0
w
2
GRM2 Output
Set as required in application (SLP) software.
GRM modules can output this information.
LED4 or RO4 modules can output this
information if set to Address 0
w
3
GRM3 Output
Set as required in application (SLP) software.
GRM modules can output this information.
LED4 or RO4 modules can output this
information if set to Address 0
w
4
GRM4 Output
Set as required in application (SLP) software.
GRM modules can output this information
w
5
GRM5 Output
Set as required in application (SLP) software.
GRM modules can output this information
w
6
GRM6 Output
Set as required in application (SLP) software.
GRM modules can output this information
w
7
GRM7 Output
Set as required in application (SLP) software.
GRM modules can output this information
w
8
to
15
Application (SLP) Software Dependent

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3.2.2 System Status Register
The bits within the System Status register have the following definitions:
Address 256 (100h)
System Status Register
Address
Bit
Name
Description
r/w
SLP Tag
Dec.
Hex.
256
100h
0
Refresh Cycle
Complete
Set by the controller at the end of every
refresh cycle (refresh cycle = all 255
module addresses have been scanned).
May be cleared by writing a 0 into this bit
using application (SLP) software.
r/w
RefreshCycle
1
L1 Checksum
Error Latch
Set by the controller when a checksum
error is detected on L1 fieldbus. May be
cleared by writing a 0 into this bit using
application (SLP) software.
r/w
L1ChksErr
2
L1 OK Latch
Set by the controller when a L1 fieldbus
scan completes with no errors detected.
May be cleared by writing a 0 into this bit
using application (SLP) software.
r/w
L1Ok
3
L2 Checksum
Error Latch
Set by the controller when a checksum
error is detected on L2 fieldbus. May be
cleared by writing a 0 into this bit using
application (SLP) software.
r/w
L2ChksErr
4
Not Used / System Use Only / Do not use
5
Not Used / System Use Only / Do not use
6
Not Used / System Use Only / Do not use
7
L2 Active
Set by controller when it detects an active
fieldbus from another controller on its L2
port.
Often used to condition the operation of
the L2 LED on the controller.
r/w
L2Active
8
Control Relay
(CR) state
Status of the Control Relay.
1 = Energised. 0 = De-energised.
r
CtrlRelayState
9
Auxiliary
Relay (AR)
state
Status of the Auxiliary Relay.
1 = Energised. 0 = De-energised.
r
AuxRelayState
10
EOL OK
Set by controller when EOL module is
being detected on the L1 fieldbus with no
faults, clear otherwise.
r
EOL_OK
11
EOL Open
Circuit
Set by controller when EOL module is not
detected on the L1 fieldbus and the
fieldbus is not short circuited, clear
otherwise.
r
EOL_OC
12
EOL Short
Circuit
Set by controller when the L1 fieldbus is
short circuited (R<1000Ω), clear otherwise
r
EOL_SC
13
EOL Clashed
Set by controller when two EOL modules
are detected on the L1 fieldbus, clear
otherwise.
r
EOL_CLASH

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Address 256 (100h)
System Status Register
Address
Bit
Name
Description
r/w
SLP Tag
Dec.
Hex.
14
Rx Active
Set by controller when its serial port is
receiving data
r
UART_Rx
15
Tx Active
Set by controller when its serial port is
transmitting data
r
UART_Tx
3.2.3 EOL Series Resistance Register
The EOL Module Resistance register can be accessed at Address 512 (200h). This register contains the
iMAC fieldbus loop resistance measured between iMAC controller and connected EOL module.
Address 512 (200h)
EOL Series Resistance Register
Address
Bit
Name
Description
r/w
SLP Tag
Dec.
Hex.
512
200h
0
to
15
EOL
Resistance
Measured series resistance of the L1
fieldbus loop from controller to EOL
Module. Values are one to one, e.g. a
reading of 00FFh (255) corresponds to
a loop resistance of 255Ω
Range: 0..1000
r
EolSeriesRes
3.2.4 Line Shunt Resistance Register
The Line Shunt Resistance register can be accessed at Address 768 (300h). This register contains the
measured shunt resistance of the iMAC L1 fieldbus.
Address 768 (300h)
Line Shunt Resistance Register
Address
Bit
Name
Description
r/w
SLP Tag
Dec.
Hex.
768
300h
0
to
15
Shunt
Resistance
Measured leakage resistance between
controller L1 fieldbus terminals. Values
are one to one, e.g. a reading of 0FFFh
(4095) corresponds to a shunt
resistance of 4095Ω
Range: 0..32768
r
EolShuntRes

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Module Data Segment
The Module Data is a group of 1020 registers. Every iMAC module address (1..255) has four associated
registers: DATA, STATUS, RESISTANCE and ERRORS. The relationship between module address and its
four corresponding registers is defined as:
Module Register
Addresses
Example: Register Addresses
for a Module at Address 1
Register Content
Decimal
Hexadecimal
Module Address (1..255)
1
001h
Module Data (module dependant)
Module Address + 256
257
101h
Module Status (see bit definitions)
Module Address + 512
513
201h
Module Resistance
Module Address + 768
769
301h
Module Error Counters
3.3.1 Module Data Register
The function of the bits within the Module Data register is dependent upon the type of module that is
addressed to that location. For information on bit functionality for each module, refer to the individual iMAC
module datasheets.
Address 001 - 255 (001h - 0FFh)
Module Data Register
Address
Bit
Name
Description
r/w
SLP Tag
Dec.
Hex.
001
to
255
001h
to
0FFh
0
D0 / SYS0
Module Dependent
(Refer to the individual module
datasheets for bit definitions).
Note: depending on corresponding
Module Status Address ownership
flags, this register will be input
(default), output (system owned), or
low-byte input/high-byte output (byte
owned).
Module
Dependent
1
D1 / SYS1
2
D2 / SYS2
3
D3 / SYS3
4
D4 / SYS4
5
D5 / SYS5
6
D6 / SYS6
7
D7 / SYS7
8
D8 / SYS8
9
D9 / SYS9
10
D10 / SYS10
11
D11 / SYS11
12
D12 / SYS12
13
D13 / SYS13
14
D14 / SYS14
15
D15 / SYS15

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3.3.2 Module Status Register
The Module Status register can be accessed at the address in the Data Point Table that corresponds to the
Module Address + 256. The bits within the Module Status register have the following definitions, regardless
of the module type that is configured at that particular address.
Address 257 - 511 (101h - 1FFh)
Module Status Register
Address
Bit
Name
Description
r/w
SLP Tag
Dec.
Hex.
257
to
511
101h
to
1FFh
0
On Scan Bit
Set by the controller when it first detects
an input module address online on its L1
fieldbus. May be cleared by application
(SLP) software. (POR=0)
r/w
OnScanBit
1
L1 Clash Bit
Set by the controller when two input
modules transmit different data on the
same address, clear otherwise.
r
L1ClashBit
2
Global
Select
Must be intentionally set by application
(SLP) software if the corresponding data
address needs to be published up the L2
fieldbus, thus making it a Global Address.
r/w
Global
3
L1 Owned
Bit
Set by the controller when it detects an
input module address on its L1 fieldbus,
cleared if module not detected.
r
L1OwnBit
4
L2 Owned
Bit
Set by the controller when it detects the
corresponding address on its L2 fieldbus.
The Global Select bit for this address must
be set to allow the controller to “see” up its
L2 fieldbus. This should be done during
the STARTUP segment of the application
(SLP) software.
r
L2OwnBit
5
System
Owned Bit
Must be intentionally set application (SLP)
software when the corresponding data
register is to be owned by the system.
Setting this bit forces the corresponding
data register to be an output. All
addresses are assumed to be an input
unless this bit is set. If an input module is
connected to a system owned address on
L1, a L1 clash error will occur.
w
SysOwnBit
6
L2 Clash Bit
Set by the controller when it detects the
address is Online on both its L1 and L2
ports if the address Global Select bit is set.
r
L2ClashBit
7
Byte Owned
Must be intentionally set by application
(SLP) software when the corresponding
data register is to be partially owned by
the system. Low byte of data register
remains as input, but SLP can now write
into high byte for output functions.
w
HighByteBit
8
to
15
-
General purpose use in application (SLP)
software.
w

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3.3.3 Module Series Resistance Register
The Module Series Resistance register can be accessed at the address in the Data Point Table that
corresponds to the Module Address + 512. This register contains the L1 fieldbus loop resistance to the
connected module at the specified address.
Address 513 - 767 (201h - 2FFh)
Module Series Resistance Register
Address
Bit
Name
Description
r/w
SLP Tag
Dec.
Hex.
513
to
767
201h
to
2FFh
0
to
15
Module Series
Resistance
Measured series resistance of the
fieldbus loop between the iMAC
Controller and the closest Module on
the fieldbus with the corresponding
address. Values are one to one, e.g. a
reading of 00FFh (255) corresponds to
a loop resistance of 255Ω
Range: 0..1000Ω
r
User Defined
3.3.4 Module Error Register
The Module Error register can be accessed at the address in the Data Point Table that corresponds to the
Module Address + 768. This register contains two counters that monitor the number of data scans that occur
with an ‘Offline Error’ or ‘Clash Error’ present at this address. The corresponding counter increments each
time there is either an Offline or Clash error detected on the L1 Fieldbus. Once the counter reaches 255 it
will auto-roll over to 0 on the next count.
Address 769 - 1023 (301h - 3FFh)
Module Error Register
Address
Bit
Name
Description
r/w
SLP Tag
Dec.
Hex.
769
to
1023
301h
to
3FFh
0
to
7
Offline Count
This count is incremented every data
scan that there is no owner of the
module address for which there was
once an owner.
r
User Defined
8
to
15
Clash Count
This count is incremented every time
that a data scan occurs when L1 Clash
= 1 (ie increments each time an
address is scanned for which there are
two modules with the same address
that are transmitting different input
data).
r
User Defined

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System Runtime Segment
The System Runtime Registers are located in address range 1024 to 1151 (400h to 47Eh). The first 20
runtime registers are defined below, the remaining registers are reserved for system use and should not be
accessed by the application (SLP) software.
Address 1024 - 1151 (400h –47Eh)
System Runtime Registers
Address
Register Content
Description
SLP Tag
Dec.
Hex.
1024
400h
System Control
Relay Control, Digital Input
Status, Sequence Control
(see individual bit definitions)
SystemControl
1025
401h
System ID and LED
control
Rotary Switch and DIP Switch
status, L1/L2 LED control
(see individual bit definitions)
SysIdLeds
1026
402h
Reserved –Do not use
-
1027
403h
Reserved –Do not use
-
1028
404h
EOL Serial Number
EOL Module Serial Number
EolSerNum
1029
405h
Reserved –Do not use
-
1030
406h
L1 Data Block Just
Complete
Contains block number of last
successfully scanned block
number.
L1BlockJustDone
1031
407h
Reserved –Do not use
-
1032
408h
Application (SLP)
Software Loop Timer
Counter
SLP loop time in milliseconds
LoopTimeSLP
1033
409h
Module Rollcall Control
Used for roll calling and
programming iMAC modules
(see individual register
definitions)
RollcallControl
1034
40Ah
Rollcall Address
RollcallAddress
1035
40Bh
Rollcall Serial Number
RollcallSerNum
1036
40Ch
Rollcall Type Register
RollcallModType
1037
40Dh
Rollcall Block Number
RollcallBlckNum
1038
40Eh
Rollcall Parameter 1
RollcallParam1
1039
40Fh
Rollcall Parameter 2
RollcallParam2
1040
410h
Rollcall Parameter 3
RollcallParam3
1041
411h
Rollcall Parameter 4
RollcallParam4
1042
412h
Remote Key Press
Valid Key Press codes will mimic
the front panel keystrokes.
KeyBoardOut
1043
413h
Message System Page
Control
Contains page number of
currently shown LCD display.
PageTransfer
1044
414h
Reserved –Do not use
-
1045
415h
EOL Offline Count
Incremental counter for the
number of scans the EOL module
has been detected as offline.
EOLS_OC
1046
416h
EOL Clash Count
Incremental counter for the
number of scans the EOL module
has been detected as clashed.
EOLS_Clash
3.4.1 System Control Register
The bits within the System Control register, Address 1024 (400h), have the following definitions: