Analog Devices ADIS16360 User manual

Six Degrees of Freedom Inertial Sensor
ADIS16360/ADIS16365
Rev. B
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FEATURES
Triaxis digital gyroscope with digital range scaling
±75°/sec, ±150°/sec, ±300°/sec settings
Tight orthogonal alignment: <0.05°
Triaxis digital accelerometer: ±18 g
Autonomous operation and data collection
No external configuration commands required
Start-up time: 180 ms
Sleep mode recovery time: 4 ms
Factory-calibrated sensitivity, bias, and axial alignment
Calibration temperature range
ADIS16360: +25°C
ADIS16365: −40°C to +85°C
SPI-compatible serial interface
Wide bandwidth:330 Hz
Embedded temperature sensor
Programmable operation and control
Automatic and manual bias correction controls
Bartlett window FIR filter length, number of taps
Digital I/O: data ready, alarm indicator, general-purpose
Alarms for condition monitoring
Sleep mode for power management
DAC output voltage
Enable external sample clock input: up to 1.2 kHz
Single-command self-test
Single-supply operation: 4.75 V to 5.25 V
2000 gshock survivability
Operating temperature range: −40°C to +105°C
APPLICATIONS
Medical instrumentation
Robotics
Platform control
Navigation
GENERAL DESCRIPTION
The ADIS16360/ADIS16365 iSensor® devices are complete inertial
systems that include a triaxis gyroscope and triaxis accelerometer.
Each sensor in the ADIS16360/ADIS16365 combines industry-
leading iMEMS® technology with signal conditioning that optimizes
dynamic performance. The factory calibration characterizes each
sensor for sensitivity, bias, alignment, and linear acceleration (gyro
bias). As a result, each sensor has its own dynamic compensation
formulas that provide accurate sensor measurements.
The ADIS16360/ADIS16365 provide a simple, cost-effective
method for integrating accurate, multiaxis inertial sensing into
industrial systems, especially when compared with the complexity
and investment associated with discrete designs. All necessary
motion testing and calibration are part of the production process
at the factory, greatly reducing system integration time. Tight
orthogonal alignment simplifies inertial frame alignment in naviga-
tion systems. An improved SPI interface and register structure
provide faster data collection and configuration control.
The ADIS16360/ADIS16365 use a compatible pinout and the same
package as the ADIS1635x family. Therefore, systems that currently
use the ADIS1635x family can upgrade their performance with
minor firmware adjustments in their processor designs. These
compact modules are approximately 23 mm × 23 mm × 23 mm
and provide a flexible connector interface that enables multiple
mounting orientation options.
FUNCTIONAL BLOCK DIAGRAM
TRI-AXIS MEMS
ANGULAR RATE
SENSOR SIGNAL
CONDITIONING
AND
CONVERSION
CALIBRATION
AND
DIGITAL
PROCESSING
DIGITAL
CONTROL
POWER
MANAGEMENT
OUTPUT
REGISTERS
AND SPI
INTERFACE
AUX_ADC AUX_DAC
RST
CS
SCLK
DIN
DOUT
TRI-AXIS MEMS
ACCELERATION
SENSOR
VCC
GND
DIO4/CLKIN
SELF-TEST
ADIS16360/
ADIS16365
TEMPERATURE
SENSOR
ALARMS
DIO3DIO2DIO1
07570-001
Figure 1.

ADIS16360/ADIS16365
Rev. B | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Timing Diagrams.......................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ........................................................................ 9
Basic Operation ............................................................................ 9
Reading Sensor Data.................................................................... 9
Device Configuration .................................................................. 9
Memory Map .............................................................................. 10
Burst Read Data Collection ...................................................... 11
Output Data Registers ............................................................... 11
Calibration................................................................................... 12
Operational Control................................................................... 12
Input/Output Functions ............................................................ 14
Diagnostics.................................................................................. 15
Product Identification................................................................ 16
Applications Information .............................................................. 17
Installation/Handling................................................................. 17
Gyroscope Bias Optimization................................................... 17
Input ADC Channel................................................................... 17
Interface Printed Circuit Board (PCB).................................... 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
12/09—Rev. A to Rev. B
Reorganized Layout............................................................Universal
Changes to Features Section............................................................ 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 5
Changes to Table 5............................................................................ 7
Changes to Table 7, Device Configuration Section ..................... 9
Changes to Table 8.......................................................................... 10
Changes to Burst Read Data Collection Section, Output
Data Registers Section, Table 9..................................................... 11
Added Table 10, Table 11, Table 12, Table 13, and Table 14;
Renumbered Tables Sequentially.................................................. 11
Added Sensor Bandwidth Section and Figure 14;
Renumbered Figures Sequentially................................................ 13
Changes to Digital Filtering Section ............................................ 13
Changes to General-Purpose I/O Section................................... 14
Changes to Table 26........................................................................ 15
Changes to Table 29 and Table 31 ................................................ 16
Added Product Identification Section ......................................... 16
Added Applications Information Section, Figure 15,
Figure 16, Figure 17; Renumbered Figures Sequentially........... 17
4/09—Rev. 0 to Rev. A
Changes to Features Section ............................................................1
Changes to Scale Factor, Table 1......................................................3
Changes to Figure 5 and Figure 6....................................................7
Changes to Figure 7 and Figure 8....................................................8
Changes to Device Configuration Section.....................................9
Changes to Figure 12...................................................................... 10
Changes to Operational Control Section .................................... 12
1/09—Revision 0: Initial Version

ADIS16360/ADIS16365
Rev. B | Page 3 of 20
SPECIFICATIONS
TA= 25°C, VCC = 5.0 V, angular rate = 0°/sec, dynamic range = ±300°/sec ± 1 g, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
GYROSCOPES
Dynamic Range ±300 ±350 °/sec
Initial Sensitivity Dynamic range = ±300°/sec 0.0495 0.05 0.0505 °/sec/LSB
Dynamic range = ±150°/sec 0.025 °/sec/LSB
Dynamic range = ±75°/sec 0.0125 °/sec/LSB
Sensitivity Temperature Coefficient ADIS16360, −40°C ≤ TA≤ +85°C ±350 ppm/°C
ADIS16365, −40°C ≤ TA≤ +85°C ±40 ppm/°C
Misalignment Reference to z-axis accelerometer ±0.05 Degrees
Axis-to-frame (package) ±0.5 Degrees
Nonlinearity Best fit straight line ±0.1 % of FS
Initial Bias Error ±1 σ ±3 °/sec
In-Run Bias Stability 1 σ, SMPL_PRD = 0x0001 0.007 °/sec
Angular Random Walk 1 σ, SMPL_PRD = 0x0001 2.0 °/√hr
Bias Temperature Coefficient ADIS16360, −40°C ≤ TA≤ +85°C ±0.025 °/sec/°C
ADIS16365, −40°C ≤ TA≤ +85°C ±0.01 °/sec/°C
Linear Acceleration Effect on Bias Any axis, 1 σ (MSC_CTRL[7] = 1) 0.05 °/sec/g
Bias Voltage Sensitivity VCC = 4.75 V to 5.25 V ±0.3 °/sec/V
Output Noise ±300°/sec range, no filtering 0.8 °/sec rms
Rate Noise Density f = 25 Hz, ±300°/sec range, no filtering 0.044 °/sec/√Hz rms
3 dB Bandwidth 330 Hz
Sensor Resonant Frequency 14.5 kHz
Self-Test Change in Output Response ±300°/sec range setting ±696 ±1400 ±2449 LSB
ACCELEROMETERS Each axis
Dynamic Range ±18 g
Initial Sensitivity 3.285 3.33 3.38 mg/LSB
Sensitivity Temperature Coefficient ADIS16360, −40°C ≤ TA≤ +85°C ±120 ppm/°C
ADIS16365, −40°C ≤ TA≤ +85°C ±50 ppm/°C
Misalignment Axis-to-axis, ∆ = 90° ideal 0.2 Degrees
Axis-to-frame (package) ±0.5 Degrees
Nonlinearity Best fit straight line 0.1 % of FS
Initial Bias Error ±1 σ ±50 mg
In-Run Bias Stability 1 σ 0.2 mg
Velocity Random Walk 1 σ 0.2 m/sec/√hr
Bias Temperature Coefficient ADIS16360, −40°C ≤ TA≤ +85°C ±4 mg/°C
ADIS16365, −40°C ≤ TA≤ +85°C ±0.3 mg/°C
Bias Voltage Sensitivity VCC = 4.75 V to 5.25 V 2.5 mg/V
Output Noise No filtering 9 mgrms
Noise Density No filtering 0.5 mg/√Hz rms
3 dB Bandwidth 330 Hz
Sensor Resonant Frequency 5.5 kHz
Self-Test Change in Output Response X-axis and y-axis 59 151 LSB
TEMPERATURE SENSOR
Scale Factor Output = 0x0000 at 25°C (±5°C) 0.136 °C/LSB
ADC INPUT
Resolution 12 Bits
Integral Nonlinearity ±2 LSB
Differential Nonlinearity ±1 LSB
Offset Error ±4 LSB

ADIS16360/ADIS16365
Rev. B | Page 4 of 20
Parameter Test Conditions/Comments Min Typ Max Unit
Gain Error ±2 LSB
Input Range 0 3.3 V
Input Capacitance During acquisition 20 pF
DAC OUTPUT 5 kΩ/100 pF to GND
Resolution 12 Bits
Relative Accuracy 101 LSB ≤ input code ≤ 4095 LSB ±4 LSB
Differential Nonlinearity ±1 LSB
Offset Error ±5 mV
Gain Error ±0.5 %
Output Range 0 3.3 V
Output Impedance 2 Ω
Output Settling Time 10 µs
LOGIC INPUTS1
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
CS signal to wake up from sleep mode 0.55 V
CS Wake-Up Pulse Width 20 µs
Logic 1 Input Current, IIH V
IH = 3.3 V ±0.2 ±10 µA
Logic 0 Input Current, IIL V
IL = 0 V
All Pins Except RST 40 60 A
RST Pin 1 mA
Input Capacitance, CIN 10 pF
DIGITAL OUTPUTS1
Output High Voltage, VOH I
SOURCE = 1.6 mA 2.4 V
Output Low Voltage, VOL I
SINK = 1.6 mA 0.4 V
FLASH MEMORY Endurance210,000 Cycles
Data Retention3TJ= 85°C 20 Years
FUNCTIONAL TIMES4Time until data is available
Power-On Start-Up Time Normal mode, SMPL_PRD ≤ 0x09 180 ms
Low power mode, SMPL_PRD ≥ 0x0A 250 ms
Reset Recovery Time Normal mode, SMPL_PRD ≤ 0x09 60 ms
Low power mode, SMPL_PRD ≥ 0x0A 130 ms
Sleep Mode Recovery Time Normal mode, SMPL_PRD ≤ 0x09 4 ms
Low power mode, SMPL_PRD ≥ 0x0A 9 ms
Flash Memory Test Time Normal mode, SMPL_PRD ≤ 0x09 17 ms
Low power mode, SMPL_PRD ≥ 0x0A 90 ms
Automatic Self-Test Time SMPL_PRD = 0x0001 12 ms
CONVERSION RATE SMPL_PRD = 0x0001 to 0x00FF 0.413 819.2 SPS
Clock Accuracy ±3 %
Sync Input Clock 0.851.2 kHz
POWER SUPPLY Operating voltage range, VCC 4.75 5.0 5.25 V
Power Supply Current Low power mode 24 mA
Normal mode 49 mA
Sleep mode 500 µA
1The digital I/O signals are driven by an internal 3.3 V supply, and the inputs are 5 V tolerant.
2Endurance is qualified as per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, +85°C, and +125°C.
3The data retention lifetime equivalent is at a junction temperature (TJ) of 85°C as per JEDEC Standard 22, Method A117. Data retention lifetime decreases with junction
temperature.
4These times do not include thermal settling and internal filter response times (330 Hz bandwidth), which may affect overall accuracy.
5The sync input clock functions below the specified minimum value, at reduced performance levels.

ADIS16360/ADIS16365
Rev. B | Page 5 of 20
TIMING SPECIFICATIONS
TA= 25°C, VCC = 5 V, unless otherwise noted.
Table 2.
Normal Mode
(SMPL_PRD ≤ 0x09)
Low Power Mode
(SMPL_PRD ≥ 0x0A) Burst Read
Parameter Description Min1Typ Max Min1 Typ Max Min1Typ Max Unit
fSCLK Serial clock 0.01 2.0 0.01 0.3 0.01 1.0 MHz
tSTALL Stall period between data 9 75 1/fSCLK µs
tREADRATE Read rate 40 100 µs
tCS Chip select to clock edge 48.8 48.8 48.8 ns
tDAV DOUT valid after SCLK edge 100 100 100 ns
tDSU DIN setup time before SCLK rising edge 24.4 24.4 24.4 ns
tDHD DIN hold time after SCLK rising edge 48.8 48.8 48.8 ns
tSCLKR, tSCLKF SCLK rise/fall times 5 12.5 5 12.5 5 12.5 ns
tDR, tDF DOUT rise/fall times 5 12.5 5 12.5 5 12.5 ns
tSFS CS high after SCLK edge 5 5 5 ns
t1 Input sync positive pulse width 5 5 µs
txInput sync low time 100 100 µs
t2 Input sync to data ready output 600 600 µs
t3 Input sync period 833 833 µs
DIN
1Guaranteed by design and characterization, but not tested in production.
TIMING DIAGRAMS
CS
SCLK
DOUT
1 2 3 4 5 6 15 16
R/W A5A6 A4 A3 A2 D2
MSB DB14
D1 LSB
DB13 DB12 DB10DB11 DB2 LSBDB1
t
CS
t
SFS
t
DAV
t
DHD
t
DSU
07570-002
Figure 2. SPI Timing and Sequence
CS
SCLK
tREADRATE
tSTALL
07570-003
Figure 3. Stall Time and Data Rate
t3
tX
t2
t1
SYNC
CLOCK (DIO4)
DATA
READY
07570-004
Figure 4. Input Clock Timing Diagram

ADIS16360/ADIS16365
Rev. B | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Acceleration
Any Axis, Unpowered 2000 g
Any Axis, Powered 2000 g
VCC to GND −0.3 V to +6.0 V
Digital Input Voltage to GND −0.3 V to +5.3 V
Digital Output Voltage to GND −0.3 V to VCC + 0.3 V
Analog Input to GND −0.3 V to +3.6 V
Operating Temperature Range −40°C to +105°C
Storage Temperature Range −65°C to +125°C1, 2
1Extended exposure to temperatures outside the specified temperature
range of −40°C to +105°C can adversely affect the accuracy of the factory
calibration. For best accuracy, store the parts within the specified operating
range of −40°C to +105°C.
2Although the device is capable of withstanding short-term exposure to
150°C, long-term exposure threatens internal mechanical integrity.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4. Package Characteristics
Package Type θJA θ
JC Device Weight
24-Lead Module
(ML-24-2)
39.8°C/W 14.2°C/W 16 grams
ESD CAUTION

ADIS16360/ADIS16365
Rev. B | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. THIS REPRESENTATION DISPLAYS THE TOP VIEW PINOUT
FOR THE MATING SOCKET CONNECTOR.
2. THE ACTUAL CONNECTOR PINS ARE NOT VISIBLE FROM
THE TOP VIEW.
3. MATING CONNECTOR: SAMTEC CLM-112-02
OR EQUIVALENT.
4. DNC = DO NOT CONNECT.
1
DIO3 SCLK DIN DIO1 DIO2 VCC GND GND DNC DNC AUX_ADC DNC
DIO4/CLKIN
DOUT
CS
RST
VCC VCC
GND
DNC DNC
AUX_DAC
DNC DNC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A
DIS16360/ADIS16365
TOP VIEW
(Not to Scale)
07570-005
Figure 5. Pin Configuration
Y
-AXIS
a
Y
g
Y
g
X
PIN 1
PIN 23
X-AXIS
a
X
Z-AXIS
a
Z
g
Z
ORIGIN ALIGNMENT REFERENCE POINT
SEE MSC_CTRL[6].
NOTES
1. ACCELERATION (
a
X
, a
Y
, a
Z
) AND ROTATIONAL ( g
X
, g
Y
, g
Z
) ARROWS
INDICATE THE DIRECTION OF MOTION THAT PRODUCES
A POSITIVE OUTPUT.
07570-006
Figure 6. Axial Orientation
Table 5. Pin Function Descriptions
Pin No. Mnemonic Type1Description
1 DIO3 I/O Configurable Digital Input/Output.
2 DIO4/CLKIN I/O Configurable Digital Input/Output or Sync Clock Input.
3 SCLK I SPI Serial Clock.
4 DOUT O SPI Data Output. Clocks output on SCLK falling edge.
5 DIN I SPI Data Input. Clocks input on SCLK rising edge.
6 CS I SPI Chip Select.
7, 9 DIO1, DIO2 I/O Configurable Digital Input/Output.
8 RST I Reset.
10, 11, 12 VCC S Power Supply.
13, 14, 15 GND S Power Ground.
16, 17, 18, 19, 22, 23, 24 DNC N/A Do Not Connect.
20 AUX_DAC O Auxiliary, 12-Bit DAC Output.
21 AUX_ADC I Auxiliary, 12-Bit ADC Input.
1I/O is input/output, I is input, O is output, S is supply, N/A is not applicable.

ADIS16360/ADIS16365
Rev. B | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
0.001
0.01
0.1
0.1 1 10 100 1k 10k
Tau (Seconds)
ROOT
A
LLAN VARIANCE (°/sec)
–1σ
MEAN
+1σ
07570-007
Figure 7. Gyroscope Allan Variance
0.0001
0.001
0.01
0.1 1 10 100 1k 10k
Tau (Seconds)
ROOT
A
LLAN VARIANCE (g)
–1σ
MEAN
+1σ
0
7570-008
Figure 8. Accelerometer Allan Variance

ADIS16360/ADIS16365
Rev. B | Page 9 of 20
THEORY OF OPERATION
BASIC OPERATION
The ADIS16360/ADIS16365 are autonomous sensor systems
that start up after they have a valid power supply voltage and
begin producing inertial measurement data at the factory default
sample rate setting of 819.2 SPS. After each sample cycle, the
sensor data is loaded into the output registers, and DIO1 pulses
high, which provides a new data ready control signal for driving
system-level interrupt service routines. In a typical system, a
master processor accesses the output data registers through the
SPI interface, using the connection diagram shown in Figure 9.
Table 6 provides a generic functional description for each pin on
the master processor. Table 7 describes the typical master processor
settings that are normally found in a configuration register and
used for communicating with the ADIS16360/ADIS16365.
SYSTEM
PROCESSOR
SPI MASTER ADIS16360/
ADIS16365
SPI SLAVE
SCLK
CS
DIN
DOUT
SCLK
SS
MOSI
MISO
5V
IRQ DIO1
VDD I/O LINES ARE COMPATIBLE WITH
3.3V OR 5V LOGIC LEVELS
10
6
3
5
4
7
11 12
13 14 15
0
7570-009
Figure 9. Electrical Connection Diagram
Table 6. Generic Master Processor Pin Names and Functions
Pin Name Function
SS Slave select
IRQ Interrupt request
MOSI Master output, slave input
MISO Master input, slave output
SCLK Serial clock
Table 7. Generic Master Processor SPI Settings
Processor Setting Description
Master The ADIS16360/ADIS16365 operate as slaves
SCLK Rate ≤ 2 MHz1Normal mode, SMPL_PRD[7:0] ≤ 0x09
SPI Mode 3 CPOL = 1 (polarity), CPHA = 1 (phase)
MSB First Mode Bit sequence
16-Bit Mode Shift register/data length
1For burst read, SCLK rate ≤ 1 MHz. For low power mode, SCLK rate ≤ 300 kHz.
The user registers provide addressing for all input/output
operations on the SPI interface. Each 16-bit register has two
7-bit addresses: one for its upper byte and one for its lower
byte. Table 8 lists the lower byte address for each register, and
Figure 10 shows the generic bit assignments.
UPPER BYTE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOWER BYTE
07570-010
Figure 10. Generic Register Bit Assignments
READING SENSOR DATA
Although the ADIS16360/ADIS16365 produce data indepen-
dently, they operate as SPI slave devices that communicate with
system (master) processors using the 16-bit segments displayed
in Figure 11. Individual register reads require two of these 16-bit
sequences. The first 16-bit sequence contains the read command
bit (R/W = 0) and the target register address (A6 to A0); the last
eight bits are “don’t care” bits when requesting a read. The second
16-bit sequence transmits the register contents (D15 to D0) on
the DOUT line. For example, if DIN = 0x0A00, the contents of
XACCL_OUT are shifted out on the DOUT line during the next
16-bit sequence.
The SPI operates in full-duplex mode, which means that the
master processor can read the output data from DOUT while
using the same SCLK pulses to transmit the next target address
on DIN.
DEVICE CONFIGURATION
The user register memory map (see Table 8) identifies configu-
ration registers with either a W or R/W. Configuration commands
also use the bit sequence shown in Figure 11. If the MSB = 1, the
last eight bits (DC7 to DC0) in the DIN sequence are loaded into
the memory address associated with the address bits (A6 to A0).
For example, if DIN = 0xA11F, 0x1F is loaded into Address 0x21
(XACCL_OFF, upper byte) at the conclusion of the data frame.
The master processor initiates the backup function by setting
GLOB_CMD[3] = 1 (DIN = 0xBE04). This command copies
the user registers into their assigned flash memory locations
and requires the power supply to stay within its normal operating
range for the entire 50 ms process. The FLASH_CNT register
provides a running count of these events for monitoring the
long-term reliability of the flash memory.
0
7570-011
R/W R/W A6 A5 A4 A3 A2 A1 A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15
CS
SCLK
DIN
DOUT
A6 A5
D13D14D15
NOTES
1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0.
Figure 11. SPI Communication Bit Sequence

ADIS16360/ADIS16365
Rev. B | Page 10 of 20
MEMORY MAP
Table 8. User Register Memory Map
Name R/W Flash Backup Address1Default Register Description Bit Function
FLASH_CNT R Yes 0x00 N/A Flash memory write count N/A
SUPPLY_OUT R No 0x02 N/A Power supply measurement See Table 9
XGYRO_OUT R No 0x04 N/A X-axis gyroscope output See Table 9
YGYRO_OUT R No 0x06 N/A Y-axis gyroscope output See Table 9
ZGYRO_OUT R No 0x08 N/A Z-axis gyroscope output See Table 9
XACCL_OUT R No 0x0A N/A X-axis accelerometer output See Table 9
YACCL_OUT R No 0x0C N/A Y-axis accelerometer output See Table 9
ZACCL_OUT R No 0x0E N/A Z-axis accelerometer output See Table 9
XTEMP_OUT R No 0x10 N/A X-axis gyroscope temperature measurement See Table 9
YTEMP_OUT R No 0x12 N/A Y-axis gyroscope temperature measurement See Table 9
ZTEMP_OUT R No 0x14 N/A Z-axis gyroscope temperature measurement See Table 9
AUX_ADC R No 0x16 N/A Auxiliary ADC output See Table 9
Reserved N/A N/A 0x18 N/A Reserved N/A
XGYRO_OFF R/W Yes 0x1A 0x0000 X-axis gyroscope bias offset factor See Table 15
YGYRO_OFF R/W Yes 0x1C 0x0000 Y-axis gyroscope bias offset factor See Table 15
ZGYRO_OFF R/W Yes 0x1E 0x0000 Z-axis gyroscope bias offset factor See Table 15
XACCL_OFF R/W Yes 0x20 0x0000 X-axis acceleration bias offset factor See Table 16
YACCL_OFF R/W Yes 0x22 0x0000 Y-axis acceleration bias offset factor See Table 16
ZACCL_OFF R/W Yes 0x24 0x0000 Z-axis acceleration bias offset factor See Table 16
ALM_MAG1 R/W Yes 0x26 0x0000 Alarm 1 amplitude threshold See Table 27
ALM_MAG2 R/W Yes 0x28 0x0000 Alarm 2 amplitude threshold See Table 27
ALM_SMPL1 R/W Yes 0x2A 0x0000 Alarm 1 sample size See Table 28
ALM_SMPL2 R/W Yes 0x2C 0x0000 Alarm 2 sample size See Table 28
ALM_CTRL R/W Yes 0x2E 0x0000 Alarm control See Table 29
AUX_DAC R/W No 0x30 0x0000 Auxiliary DAC data See Table 23
GPIO_CTRL R/W No 0x32 0x0000 Auxiliary digital input/output control See Table 21
MSC_CTRL R/W Yes 0x34 0x0006 Miscellaneous control: data ready, self-test See Table 22
SMPL_PRD R/W Yes 0x36 0x0001 Internal sample period (rate) control See Table 18
SENS_AVG R/W Yes 0x38 0x0402 Dynamic range and digital filter control See Table 20
SLP_CNT W No 0x3A 0x0000 Sleep mode control See Table 19
DIAG_STAT R No 0x3C 0x0000 System status See Table 26
GLOB_CMD W No 0x3E 0x0000 System command See Table 17
Reserved N/A N/A 0x40 to 0x51 N/A Reserved N/A
LOT_ID1 R Yes 0x52 N/A Lot Identification Code 1 See Table 32
LOT_ID2 R Yes 0x54 N/A Lot Identification Code 2 See Table 32
SERIAL_NUM R Yes 0x56 N/A Serial number See Table 32
PROD_ID R Yes 0x58 0x3FE8 Product identification, ADIS16360 See Table 32
PROD_ID R Yes 0x58 0x3FED Product identification, ADIS16365 See Table 32
1Each register contains two bytes. The address of the lower byte is displayed. The address of the upper byte is equal to the address of the lower byte plus 1.