Analog Devices EVAL AD5933-U1 Instruction manual

Evaluation Board for the 1 MSPS 12-Bit
Impedance Converter Network Analyzer
Preliminary Technical Data
EVAL AD5933-U1
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Full-featured evaluation board for the AD5933
Graphic user interface software with frequency sweep
capability for board control and data analysis
Various linking options
Standalone capability with serial I2C loading for selectable
system clock from PLL, RC oscillator, external clock
APPLICATIONS
Complex impedance measurement
Corrosion monitoring
Impedance spectrometry
Biomedical and automotive sensors
Proximity sensors
DFT processing
GENERAL DESCRIPTION
This data sheet describes the evaluation board for the AD5933
and the application software developed to interface to the
device. The AD5933 is a 1MSPS 12-bit high precision
impedance converter systems. The AD5933 combines an on
board frequency generator with a 12-bit 1 MSPS ADC. The
frequency generator allows an unknown external impedance to
be excited with a known frequency. The response signal from
the impedance is sampled by the on board ADC, and the DFT is
processed by an on board DSP engine. The AD5933 also
contains an internal temperature sensor with 13-bit resolution.
The part operates from a 3.0 V to 5.5 V supply. Other on board
components include two ADP3303 ultrahigh precision
reference to provide stable 3.3 V references to act as a stable
supply voltages for the separate analog and digital sections of
the device and to act as a supply to the on board universal serial
bus controller, which interfaces to the device. The evaluation
board also has a high performance trimmed 16 MHz surface-
mount crystal as a system clock to the AD5933, if required.
The various link options located around the evaluation board
are explained in Table 2. Interfacing to the AD5933 is through a
Cypress USB microcontroller, which generates the I2C signals
necessary to communicate to the AD5933.The user interfaces to
the USB microcontroller through a Visual Basic® graphic user
interface located on and run from the user PC.
More information on the AD5933 is available from Analog
Devices at www.analog.com and should be consulted when
using the evaluation board.
FUNCTIONAL BLOCK DIAGRAM
05435-001
USB HUB USB
MICROCONTROLLER
ADP3303
REFERENCE
V
BIAS
SCL
SDA
D
GND
A
GND
1
A
GND
2
V
BIAS
VIN
V
OUT
R
FB
16MHz
CRYSTAL
M
CLK
D
VDD
A
VDD
1
A
VDD
2
DIGITAL SUPPLY
EXTERNAL
AMPLIFIER
AD5933
ADP3303
REFERENCE
ANALOG
SUPPLY1
ANALOG
SUPPLY2
AMPLIFIER
SUPPLY
EXTERNAL
CLOCK
Figure 1.

EVAL AD5933-U1 Preliminary Technical Data
Rev. PrA | Page 2 of 16
TABLE OF CONTENTS
Evaluation Board Hardware............................................................ 3
Termina l Block Func tions ........................................................... 3
Link Functions.............................................................................. 3
SMB Jumper Functions................................................................ 4
Pin Configuration and Function Descriptions......................... 5
Getting Started .................................................................................. 6
Setup Sequence Summary ........................................................... 6
Step 1—Install the Software ........................................................ 6
Step 2—Connect the USB Cable ................................................ 7
Step 3—Verify the Links and Power Up The Evaluation Board
..........................................................................................................7
Step 4—Perform a Frequency Sweep..........................................8
Frequently Asked Questions..................................................... 10
Evaluation Board Schematic ......................................................... 12
Ordering Information.................................................................... 15
Ordering Guide .......................................................................... 15
ESD Caution................................................................................ 15
REVISION HISTORY
3/05—Revision PrA

Preliminary Technical Data EVAL AD5933-U1
Rev. PrA | Page 3 of 16
EVALUATION BOARD HARDWARE
TERMINAL BLOCK FUNCTIONS
Table 1.
Pin Name Description
J1-1 VDD-REF Terminal Block. ADP3303 Voltage Regulator Input Connection. DVDD-REF is decoupled to the analog ground
plane AGND (J1-2) via standard 0.1 µF and 10 µF suppression capacitors.
J1-2 AGND
Terminal Block. Analog Ground Connection. Decoupled to J1-1 using standard 0.1 µF and 10 µF suppression
capacitors. The analog ground plane is connected to the digital ground plane at a single point underneath the
board.
J2 -1 DVDD_5v Terminal Block. AD5933 Digital Circuitry Supply Connection. This connector is decoupled to the digital ground
plane via standard 0.1 µF and 10 µF suppression capacitors. This connector also supplies the high performance
16 MHz surface-mount crystal with the required operating supply voltage.
J2-2 DGND
Terminal Block. Digital Ground Connection. Decoupled to J2-1 using standard 0.1 µF and 10 µF suppression
capacitors. The analog ground plane is connected to the digital ground plane at a single point underneath the
board.
J8-1 VDD-AMP
Terminal Block. There is a facility to place a single-supply operational amplifier on the output voltage terminal
(Pin 6) of the AD5933. This terminal block is a connection to the single-supply positive rail of the operation
amplifier. The connector is decoupled to the analog ground plane via standard 0.1 µF and 10 µF suppression
capacitors.
J8-2 AGND
Terminal Block. Analog Ground Connection. Decoupled to J8-1 using standard 0.1 µF and 10 µF suppression
capacitors. The analog ground plane is connected to the digital ground plane at a single point underneath the
board
J9-1 AVDD-REF
Terminal Block. AD5933 Analog Circuitry Reference Input Supply. AVDD-REF is decoupled to the analog ground
plane AGND (J9-2) via standard 0.1 µF and 1 0 µF suppression capacitors.
J9-2 AGND
Terminal Block. Analog Ground Connection. Decoupled to J8-1 using standard 0.1 µF and 10 µF suppression
capacitors. The analog ground plane is connected to the digital ground plane at a single point underneath the
board
J10-1 AVDD-SIG
Terminal Block. AD5933 Analog Circuitry Input Supply. AVDD-REF is decoupled to the analog ground plane
AGND (J9-2) via standard 0.1 µF and 10 µF suppression capacitors.
J10-2 AGND Terminal Block. Analog Ground Connection. Decoupled to J10-1 using standard 0.1 µF and 10 µF suppression
capacitors. The analog ground plane is connected to the digital ground plane at a single point underneath the
board.
LINK FUNCTIONS
Table 2.
Link No. Function
LK1 Selects the output of the optional operational amplifier U1. Used to amplify the output excitation voltage from the AD5933
and which is available at SMB connector, TF1_OUT. This link is used in conjunction with Link 6. When Link 1 is inserted, Link 6
(LK6) should be removed and vice versa.
When this link is inserted, the output of the user-supplied amplifier is applied to the SMB output, TF1_OUT.
When this link is removed, the output of the user-supplied amplifier is not applied to the SMB output, TF1_OUT.
LK2 This link option is used to connect the output excitation signal from Pin 6 of the AD5933 to the noninverting terminal of the
user-supplied operational amplifier. This link is used in conjunction with Link 6. When Link 2 is inserted, Link 6 should be
removed and vice versa.
When this link is inserted, the output of the AD5933 excitation voltage pin (Pin 6) is applied to the noninverting terminal (Pin 3
of U1) of the user-supplied operational amplifier.
When this link is removed, the output of the AD5933 excitation voltage pin (Pin 6) is no longer applied to the noninverting
terminal (Pin 3 of U1) of the user-supplied operational amplifier.
LK3 The AD5933 can have an external 16 MHz clock signal or can be clocked internally using the internal RC oscillator. A high
performance 16 MHz surface-mount crystal is supplied with the evaluation board. However, the user can override this clock
signal by applying another system clock signal through the SMB connector CLK1. The surface-mount crystal has to be
removed when an external clock signal is being applied through CLK1.
When this link is inserted, the external clock applied to SMB connector CLK1 is routed to the external clock pin (Pin 8) of the
AD5933.
When this link is removed, the external clock applied to SMB connector CLK1 is not routed to the external clock pin (Pin 8) of
the AD5933. The surface-mount crystal is still connected.

EVAL AD5933-U1 Preliminary Technical Data
Rev. PrA | Page 4 of 16
LK4 The analog circuitry section of the AD5933 is powered through Terminal Block J10-1 (AVDD-SIG). This terminal block is
supplied with an external voltage source. The user can use the on board high performance voltage regulator, AD3303, to act
as the voltage supply to the AVDD_SIG pin of the AD5933.
When this link is inserted, the output of the ADP3303 3.3 V regulator (U4) is connected to the analog voltage supply pin of the
AD5933 (Pin 10).
When this link is removed, the output of the ADP3303 3.3 V regulator (U4) is disconnected from the analog voltage supply pin
of the AD5933 (Pin 10). In this case, the AVDD-SIG pin has to have an external supply voltage supplied applied via J10-1.
LK5 The analog circuitry section of the AD5933 is powered through Terminal Block J10-1 (AVDD-SIG). This terminal block is
supplied with an external voltage source. The user has the facility of using the on board high performance voltage regulator
AD3303 to act as the voltage supply to the AVDD_SIG pin of the AD5933.
When this link is inserted, the output of the ADP3303 3.3 V regulator (U4) is connected to the analog voltage supply pin of the
AD5933 (Pin 10).
When this link is removed, the output of the ADP3303 3.3 V regulator (U4) is disconnected to the analog voltage supply pin of
the AD5933 (Pin 10). In this case, the AVDD-SIG pin has to have a external supply voltage supplied applied via J10-1.
LK6 This link is used in conjunction with Link 1 and Link 2. The output excitation voltage can be directly applied to the TF1-OUT
SMB connector by inserting Link 6 and removing both Link 1 and Link 2.This output excitation voltage may be post amplified
by routing the signal through a noninverting amplifier by removing Link 6 and inserting Link 1 and Link 2.
When this link is inserted, the output of the AD5933 is connected directly to the input of the TF1_OUT SMB connector.
When this link is removed, the output the AD5933 is not connected directly to the input of the TF1_OUT SMB connector.
When this link is removed, Link 1 and Link 2 must be inserted. This is assuming that the user has inserted an operational
amplifier.
LK7 This link is inserted to connect the Tf2-OUT SMB connector to the inverting terminal of the transimpedance amplifier within
the AD5933. This link is required to complete the signal path and should be inserted while running a sweep.
When Link 7 is inserted, TF2-OUT is connected to the inverting terminal of the transimpedance amplifier in the AD5933.
When Link 7 is removed, TF2-OUT is connected to the inverting terminal of the transimpedance amplifier in the AD5933.
LK8 This is an applications sweep test link. When this link is inserted, one end of a 15 pF capacitor is connected across the tf2 pin of
the AD5933. This link should be removed when running a normal sweep across TF1-OUT/TF2-OUT SMB connectors.
LK9 This is an applications sweep test link. When this link is inserted, one end of a 15 pF capacitor is connected across the tf1 pin of
the AD5933. This link should be removed when running a normal sweep across TF1-OUT/TF2-OUT SMB connectors.
SMB JUMPER FUNCTIONS
Table 3.
SMB Function
CLK1 The user can apply an external 16 MHz clock signal to the AD5933 Pin 8. Link 3 is inserted and the external clock signal is
applied to this SMB connector. Alternatively, Link 3 can be removed and either the on board high performance 16 MHz
surface-mount crystal or the internal RC oscillator can be used to clock the system.
CLK2 This link is for test purposes only. It provides a direct link to the output of the internal direct digital synthesizer, which
generates the initial external excitation signal. This signal is subsequently signal conditioned before being output on Pin 6. In
test mode, the DDS output is available externally on the CLK2 SMB connector. This signal path is not connected to the DDS
output in normal standby mode.
TF1_OUT The signal available on this connector, which is to be connected to some unknown impedance whose value is to be
determined, is either the direct excitation voltage output from Pin 6 from the AD5933 or an amplified version, depending on
the status of Links 1, 2, and 6.
TF2_OUT This connector takes the response signal from across the unknown impedance and provides a path back to the input pin (tf2,
Pin 5). Link 7 must be inserted for the path to be complete. The external feedback resistor has one point connected to this
signal path as shown the board schematic (Figure 24).

Preliminary Technical Data EVAL AD5933-U1
Rev. PrA | Page 5 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC 1
NC 2
NC
3
RFB_PIN 4
SCL 16
SDA 15
AGND2
14
AGND1 13
VOUT 5 DGND 12
VIN
6
AVDD2
11
NC 7 AVDD1 10
MCLK 8 DVDD 9
NC = NO CONNECT
AD5933
TOP VIEW
(Not to Scale)
05435-029
Figure 2. Pin Configuration
Table 4. Recommended Pin Connections for System Development
Pin No. Mnemonic Description
1, 2, 3, 7 N/C No Connect.
4 RFB_PIN
External Feedback Resistor. This is used to set the gain of the input signal of the VIN node. Feedback resistor
connected between TF2 and RFB. The resistor connects to the out put of internal trans impedance amplifier.
5 VIN
Input Signal to Transimpedance Amplifier. External feedback resistor will control gain of transimpedance
amplifier. Test impedance is connected between this pin and the VOUT pin.
6 VOUT
Output AC Excitation Signal. Programmable frequency range 0 Hz to 50 kHz. Test impedance is connected
between this pin and the VIN pin.
8 MCLK
Master Clock for the System. Used to provide output excitation signal and as sampling of ADC. External clock
pad. Used only if external clock option is selected.
9 DVDD Digital Supply Voltage. Recommended to be tied to 3.3 V.
10 AVDD1 Analog Supply Voltage 1. Recommended to be tied to 3.3 V.
11 AVDD2 Analog Supply Voltage 2. Recommended to be tied to 3.3 V.
12 DGND Digital Ground. Must be tied to GND.
13 AGND1 Analog GND 1. Must be tied to GND.
14 AGND2 Analog GND 2. Must be tied to GND.
15 SDA I2C Data Input.
16 SCL I2C Clock Input.
It is recommended to tie all supply connections (Pins 9, 10, 11) and run from a single supply between 3.0 V and 5.5 V. Also, it is
recommended to connect all ground signals together (Pins 12, 13, 14).

EVAL AD5933-U1 Preliminary Technical Data
Rev. PrA | Page 6 of 16
GETTING STARTED
SETUP SEQUENCE SUMMARY
This installation was done using the Windows XP operating
system. The installation consists of the following steps, which
are described in detail in the sections that follow.
1. Install the graphical user interface software. Do not
connect the USB cable from the AD5933 evaluation board
to the computer USB hub at this stage. See Step 1—Install
the Software.
2. Connect the USB port from the computer to the evaluation
board, and run the USB installation wizard. See Step 2—
Connect the USB Cable.
3. Ensure that the appropriate links are made through out the
evaluation board. Power up the evaluation board. See Step
3—Verify the Links and Power Up.
4. Use the evaluation board software to run the sweep
function. See Step 4—Perform a Frequency Sweep.
STEP 1—INSTALL THE SOFTWARE
Place the CD accompanying the evaluation board into the CD
drive of the user computer and open My Computer. Double-
click the disk drive icon. Go to AD5933 Installation >
Setup.exe (Figure 3).
05435-002
Figure 3.
Double-click Setup.exe and install the software on the hard
drive of your computer through the installation wizard (Figure 4).
05435-003
Figure 4.
It is recommended to install the software in the default
destination folder path, c\Program Files\Analog
Devices\AD5933 Demo (Figure 5).
05435-004
Figure 5.
Choose Analog Devices (Figure 6). If the Analog Devices
folder does not yet exist, create a folder called Analog Devices
and add the program icon to this new folder.
05435-005
Figure 6.
After installing the software, remove the CD from the disk
drive.
Go to Start > All Programs > Analog Devices > AD5933 >
AD5933 Software (Figure 7).
05435-006
Figure 7.

Preliminary Technical Data EVAL AD5933-U1
Rev. PrA | Page 7 of 16
The following message appears (Figure 8) because the firmware
code, which is downloaded to the evaluation board EPROM
memory each time the interface software program is opened,
has not yet been downloaded. Because there is no USB
connection between the computer and the AD5933 evaluation
board at this stage, this error message is to be expected. Click
OK and proceed to Step 2.
05435-007
Figure 8.
STEP 2—CONNECT THE USB CABLE
Plug the USB cable into the computer USB hub and into the
AD5933 evaluation board. A message tells you that a USB
device has been detected and that new hardware has been found
(Figure 9).
05435-008
Figure 9.
The Found New Hardware Wizard appears (Figure 10). This
wizard installs software for the AD5933 evaluation kit. Check
Install the software automatically (Recommended)(Figure
10). Click Next to continue.
05435-010
Figure 10.
An error warning appears (Figure 11). It indicates that the new
hardware you are installing (AD5933 evaluation kit) has not
passed the Windows logo testing to verify compatibility with
Windows XP. This error appears because this is an evaluation
setup installation and not meant to be used in a production
environment. Click Continue Anyway and click Finish.
05435-011
Figure 11.
You see the message, Found New Hardware. Your new
hardware is installed and ready to use (Figure 12).
05435-012
Figure 12.
To learn more about your installation, refer to the Frequently
Asked Questions section.
STEP 3—VERIFY THE LINKS AND POWER UP THE
EVALUATION BOARD
Ensure that the relevant links are in place on the evaluation
board (see Table 2) and that the proper power connections have
been made before powering up evaluation board. The
recommended power supply connections in Table 4. It is
important that the USB connector supply power only to the
Cypress USB controller chip that interfaces to the AD5933. It
does not act as a supply source to the AD5933. The user must
ensure that all other relevant power connections are made, for
example, avdd_sig, avdd_ref, to ensure correct functionality of
the part. The user can supply these signals from an external
supply via the power supply connections on the board or use
the on board ADP3303 precision voltage reference.

EVAL AD5933-U1 Preliminary Technical Data
Rev. PrA | Page 8 of 16
STEP 4—PERFORM A FREQUENCY SWEEP
Go to Start > Programs > Analog Devices > AD5933 and click
Interface Software.
The sequence for performing a frequency sweep across a 15 pF
ceramic capacitive impedance connected across VOUT and
VIN pins in the frequency range 30 kHz to 40.22 kHz is
outlined in this section.
When the graphic user interface program is run, it appears as
shown in Figure 13. The figure shows the interface along with
an impedance profile for a sweep across 15 pF ceramic
capacitive impedance.
This section describes how to set up a typical sweep across a
similar impedance using the installed AD5933 software. The
theory of operation and the internal system architecture of the
AD5933 is described in detail in the AD5933 data sheet. This is
available at www.analog.com and should be consulted when
using the evaluation board.
05435-019
1A 1B 2 3A 3B 4
Impedance at start
frequency Impedance at stop frequency
Figure 13.

Preliminary Technical Data EVAL AD5933-U1
Rev. PrA | Page 9 of 16
To set the frequency sweep step size, enter 20 (Hz) in the Delta
Frequency box (Arrow 1A). The frequency step size is 24-bit
accurate.
To set the number of increments along the sweep, enter 511 in
the Number Increments box (Arrow 1A). 511 is the maximum
number of increments that the device can sweep across. The
value is stored in a register as a 9-bit value.
To determine the delay between the time a frequency increment
has taken place on the output of the internal DDS core and the
time the ADC samples the response signal, enter 15 (cycles) in
the Number of Settling Time cycles box (Arrow 1A). For
example, if the next output frequency is 32 kHz, the delay
between the time the DDS output this frequency and the time
the ADC samples the response signal is 15 × (1/32 kHz). The
maximum number of settling time cycles delay that can be
programmed to the board is 511 cycles. The value is stored in a
register as a 9-bit value. This value can be further multiplied by
a factor of 2 or 4, as explained next. If you are sweeping across a
high Q structure such as tuning fork or resonant circuit, make
sure that the settling time is sufficient such that the structure
settles before incrementing the frequency step. This is achieved
by increasing the settling time.
Set the output excitation voltage gain control (either
2/1/0.5/0.2 V p-p) of the AD5933 (at Pin 6,VOUT1 which is
connected to evaluation board test pin T8 to 1 V p-p (see the
Evaluation Board Schematic). Set the post gain of the ADC
response stage (either X1 or X5) to X1 (Arrow 1B). To choose
the internal RC oscillator as the system clock, check Internal
RC Oscillator in the System clock panel. NOTE: For a narrow
bandwidth/high Q response, for example, tuning fork, make
sure that the ADC gain is set to a gain of 5 and the output
voltage is set to 1 V p-p.
Choose a series resistor or a resistor in parallel with a capacitor
in the Calibration Impedance panel (Arrow 1B). For this
example, choose capacitor only to measure the impedance
sweep across a capacitor. For this example, enter 0(Ω) the
Resistor Value box, and 15E-12in the Capacitor Value box.
To program the sweep conditions register values into the
AD5933 RAM through the I2C interface, click Program
Registers (Arrow 2). As explained in previously, the value
programmed into the settling time cycles can be further
multiplied by a factor of 2 or 4 for a sweep (Arrow 3A). Click
X1 (the default), X2, or X4. To place the AD5933 into standby
or power-down mode, click Enter Standby Mode or Enter
Power Down Mode.
Click Calculate Gain Factor (Arrow 3B). An explanation of the
gain factor, which is the admittance per code of the calibrated
system, is provided in detail in the product data sheet. This
results in the gain factor being calculated for the calibration
impedance, which is returned to the interface and subsequently
used for the sweep across either the impedance under test. If
you want to use a gain factor that has been previously
calculated, click the returned gain factor and enter the new gain
factor.
05435-020
Figure 14.
After the system calculates the gain factor for the current
system setup, it appears in the calculated gain factor box.
To re-use the sweep setup under conditions other than those
that were initially programmed, or to reprogram different sweep
conditions, recalculate a new gain factor and re-enter it into the
interface to read back any significant results. The gain factor
calculated in software is not programmed into the AD5933
RAM and is valid only when the software program is running.
It is not retained when the software program is closed. However,
it is retained when the part is placed into power-down mode.
To begin t he s weep, click Start Sweep (Arrow 4). This returns
a plot of the impedance vs. frequency for the impedance
(Figure 13).The progress of the sweep is outlined with a
progress bar (Figure 15).
05435-028
Figure 15.
A message indicates that the sweep is complete.
To take a reading from the on board temperature sensor, click
Read Temperature. This returns the 13-bit temperature of the
device. See product data sheet for more information on the
temperature sensor.

EVAL AD5933-U1 Preliminary Technical Data
Rev. PrA | Page 10 of 16
To download the imaginary, real, phase and magnitude data
from the DFT of the response sweep, click Download
Imaginary Data, Download Real Data, Download phase or
Download Magnitude Data. Choose a file name in the current
directory and click Save File (Figure 16)
05435-021
1: CHOOSE
DIRECTORY
2: CHOOSE
FILE NAME
3: SAVE THE FILE 4: CLOSE
PROGRAM FILE
Figure 16.
This saves the sweep data to a data file located in the directory
of you choice. You can access this file content by using Notepad
or Microsoft Excel to plot the data. Each file contains a single
column of data. Each data entry corresponds to each single
sweep point so, if you program 511 point as the value for the
number of increments, the array contains a single column of
data with 511 data points, starting at the start frequency and
ending at stop frequency value, which is determined by
Start frequency + (number of increments × delta frequency)
The impedance profile with frequency appears after the sweep
finishes. This shows how the impedance of the network under
analysis varies across the programmed frequency range. To view
how the relative phase across the network under analysis varies,
click relative phase vs. frequency. The plot in Figure 17
appears. Click Run plot to display the plot.
The relative phase takes into account the phase introduced
through the entire signal path, that is, the phase through the
output amplifiers, transimpedance amplifiers, along with the
phase through the impedance under analysis connected
between VOUT and VIN (Pin 6 and Pin 5 of the AD5933).
05435-023
PRESS THIS BUTTON
TO RUN THE PLOT
Figure 17.
FREQUENTLY ASKED QUESTIONS
Q: How can I confirm that the hardware has been correctly
installed in my computer?
A: Right-click My Computer and left-click Properties. On the
Hardware tab, click Device Manager.
05435-013
Figure 18.
Scroll to Universal Serial Bus Controllers and expand this
directory root (Figure 19). When the AD5933 hardware is
correctly installed, each time you plug the USB cable into the
evaluation board, the items under the Universal Serial Bus
Controllers root are refreshed. This indicates that the AD5933
is present each time the evaluation board USB cable is plugged
in correctly. It is subsequently refreshed when the USB cable is

Preliminary Technical Data EVAL AD5933-U1
Rev. PrA | Page 11 of 16
unplugged from evaluation board and the AD5933 evaluation
kit connection is removed from the root.
05435-014
EXPAND ROOT
DIRECTORY
Figure 19.
Q: During the installation, the message in Figure 20 appears.
05435-015
Figure 20.
When I click Finish, the message in Figure 21 appears. What do
I do next?
05435-016
Figure 21.
A: Assuming that the software is installed correctly, this
message simply indicates that the AD5933 device drivers have
not been correctly installed. To install them, right-click My
Computer and left-click Properties. On the Hardware tab,
choose Device Manager. Expand Other devices (Figure 22).
05435-017
1: EXPAND THIS
DIRECTORY 2: RIGHT CLICK
ON THIS DEVICE
Figure 22.
The computer has not recognized the USB device, that is, the
AD5933 evaluation board that is plugged in. Right-click USB
Device and choose Uninstall Driver. Unplug the evaluation
board and wait for approximately 30 seconds before plugging it
in again. Proceed through the installation wizard a second time.
A correct installation is indicated by the expanded root
directory in Figure 23. If you encounter the same error message
the second time, uninstall the device driver and uninstall the
software and start the complete process again. Contact the
Analog Devices applications department for further
instructions and help.
05435-018
CORRECTLY INSTALLED
HARDWARE
CORRECTLY INSTALLED
HARDWARE
Figure 23.

EVAL AD5933-U1 Preliminary Technical Data
Rev. PrA | Page 12 of 16
EVALUATION BOARD SCHEMATIC
05435-024
EXT_OUT
CS
DOUT
RFB
TF2
TF1
NC
EXT_CLK
SCL
SDA
AGND_REF
AGND_SIG
DGND
AVDD_REF
AVDD_SIG
DVDD
U7
AD11_2043
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
T1
T2
T5
T6
R2
50Ω
LK7
OP97
U1
OUT
6
7
4
2
3
+VIN
TRIM
VOUT
GND
U4
ADR425
C32
0.1µFC31
10µF
2
5
6
4
CLK2
LK6
LK2
LK3
LK4 LK5
C25
10µF
C26
0.1µF
C30
10µF
C28
0.1µF
C2
10µF
C24
0.1µF
C29
10µF
C27
0.1µF
LK8
LK9
C42
15pF
TF1_OUT
TF2_OUT
VDD_AMP
R5
50Ω
R3
50Ω
R1
50Ω
DGND
CLK1
DGND
VDD O/P
GND
XTAL1
C1
0.1nF
43
2
DVDD_5V
AVDD_SIG
AVDD_REF
DGND
DVDD_5V
LK1
DGND
DGND
T7
T8
C41
SCL
SDA
VDD_REF
AGND DGND
Figure 24.

Preliminary Technical Data EVAL AD5933-U1
Rev. PrA | Page 13 of 16
05435-025
PB0/FD0
PB1/FD1
PB2/FD2
PB3/FD3
PB4/FD4
PB5/FD5
PB6/FD6
PB7/FD7
PB8/FD8
PB9/FD9
PB10/FD10
PB11/FD11
PB12/FD12
PB13/FD13
PB14/FD14
PB7/FD15
U3
CY7C58013–CSP
C20
0.1µF
C19
0.1µF
C8
0.1µF
C7
0.1µF
C6
0.1µF
C5
0.1µF
+3.3V
C21
0.1µF
CTL0/*FLAGA
CTL1/*FLAGB
CTL2/*FLAGC
SDA
SCL
XTALOUT
XTALIN
RESET
WAKEUP
CLKOUT
D–
D+
PA0/INT0
PA1/INT1
PA2/*SLOE
PA3/*WU2
PA4/FIFOADR0
PA5/FIFOADR1
PA6/*PKTEND
PA7/*FLO/SLCS
RDY0/*SLRD
RDY1/*SLWR
IFCLK
RSVD
AGND GND GND GND GND GND GND GND
AVCC
VCC VCC VCC VCC VCC VCC VCC
VCC
WP
SCL
SDA
U2
24LC64
C22
0.1µF
+3.3V
8
A0
A1
A2
VSS
7
6
5
+3.3V
+3.3V +3.3V
C23
2.2µF
C18
0.1µF
R11
0Ω
+3.3V
+3.3V
3 7 11 17 27 32 43 55
C9
0.1µF
R12
100kΩ
+3.3V
C4
10µF
R13
100kΩ
+3.3V
SCL
SDA
5
4
15
16
31
30
29
18
19
20
21
 22
23
24
25
45
46
47
48
49
 50
51
52
14
13
2
1
VCC
D–
D+
GND
SH
SH
1
2
3
4
5
6
5V USB
T1
T2
42
44
54
9
8
33
34
35
36
37
38
39
40
C10
2.2µF
C17
0.1µF
6
10 12 26 28 41 53 56
R15
2.2kΩ
R14
2.2kΩ
1
2
3
4
J7
USB
R16
10kΩ
Y1
24MHz
Figure 25.

EVAL AD5933-U1 Preliminary Technical Data
Rev. PrA | Page 14 of 16
05435-026
C3
0.1µF
C13
10µF
5VUSB
NR
U5
ADP3300
5
3
2
IN 4
6
SD
GND
OUT
ERR
OUT1
U8
ADP3300-3.3
8
71
IN1 2
6
3
SD
GND
OUT2
ERROR
NR
IN2
5
1
4C16
0.1µF
T1 T2 T3 T4
C15
0.1µF
C14
10µF
+3.3V
D4
3.3V
R24
1kΩ
Figure 26.
05435-027
C12
10µF
C11
0.1µF
DVDD_5V
DGND
J2-2
J2-1
C35
10µF
C36
0.1µF
VDD_AMP
JB-1
JB-2
 C38
10µF
C37
0.1µF
AVDD_REF
J9-1
J9-2
C40
10µF
C39
0.1µF
AVDD_SIG
J
10-2
J
10-1
C33
10µF
C34
0.1µF
VDD_REF
J1-1
J1-2
+
Figure 27.

Preliminary Technical Data EVAL AD5933-U1
Rev. PrA | Page 15 of 16
ORDERING INFORMATION
ORDERING GUIDE
Model Package Description
EVAL AD5933-U1 Evaluation Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada-
tion or loss of functionality.

EVAL AD5933-U1 Preliminary Technical Data
Rev. PrA | Page 16 of 16
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
EB05435–0–3/05(PrA)